Lines Matching +full:36 +full:- +full:bit
1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
11 //===----------------------------------------------------------------------===//
55 UNW_EUNSPEC = -6540, /* unspecified (general) error */
56 UNW_ENOMEM = -6541, /* out of memory */
57 UNW_EBADREG = -6542, /* bad register number */
58 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */
59 UNW_ESTOPUNWIND = -6544, /* stop unwinding */
60 UNW_EINVALIDIP = -6545, /* invalid IP */
61 UNW_EBADFRAME = -6546, /* bad frame */
62 UNW_EINVAL = -6547, /* unsupported operation or bad value */
63 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */
64 UNW_ENOINFO = -6549 /* no unwind info found */
66 , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
101 unw_word_t extra; /* mach_header of mach-o image containing func */
142 UNW_REG_IP = -1, // instruction pointer
143 UNW_REG_SP = -2, // stack pointer
146 // 32-bit x86 registers
158 // 64-bit x86_64 registers
196 // 32-bit ppc register numbers
234 UNW_PPC_F4 = 36,
313 // 64-bit ppc register numbers
351 UNW_PPC64_F4 = 36,
424 // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
497 // 64-bit ARM64 registers
645 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
646 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
647 // In this scheme, even though the 64-bit floating point registers D0-D31
648 // overlap physically with the 32-bit floating pointer registers S0-S31,
649 // they are given a non-overlapping range of register numbers.
672 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
705 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
706 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
723 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
724 // 134-142 -- Reserved
726 // 144-150 -- R8_USR-R14_USR
727 // 151-157 -- R8_FIQ-R14_FIQ
728 // 158-159 -- R13_IRQ-R14_IRQ
729 // 160-161 -- R13_ABT-R14_ABT
730 // 162-163 -- R13_UND-R14_UND
731 // 164-165 -- R13_SVC-R14_SVC
732 // 166-191 -- Reserved
737 // 196-199 -- wC4-wC7 (Intel wireless MMX control)
738 // 200-255 -- Reserved
771 // 288-319 -- Reserved for VFP/Neon
772 // 320-8191 -- Reserved
773 // 8192-16383 -- Unspecified vendor co-processor register.
851 UNW_MIPS_F4 = 36,
881 // for r6 and pre-r6.
960 // RISC-V registers. These match the DWARF register numbers defined by section
961 // 4 of the RISC-V ELF psABI specification, which can be found at:
963 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
1001 UNW_RISCV_F4 = 36,
1029 // 65-95 -- Reserved for future standard extensions
1030 // 96-127 -- v0-v31 (Vector registers)
1031 // 128-3071 -- Reserved for future standard extensions
1032 // 3072-4095 -- Reserved for custom extensions
1033 // 4096-8191 -- CSRs
1035 // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec:
1036 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model
1079 UNW_VE_S36 = 36,
1143 UNW_VE_V36 = 64 + 36,
1227 // 32-47 Control Registers
1228 // 48-63 Access Registers
1231 // 66-67 Reserved
1232 // 68-83 Vector Registers %v16-%v31
1273 UNW_LOONGARCH_F4 = 36,