Lines Matching +full:23 +full:- +full:64
1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
11 //===----------------------------------------------------------------------===//
55 UNW_EUNSPEC = -6540, /* unspecified (general) error */
56 UNW_ENOMEM = -6541, /* out of memory */
57 UNW_EBADREG = -6542, /* bad register number */
58 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */
59 UNW_ESTOPUNWIND = -6544, /* stop unwinding */
60 UNW_EINVALIDIP = -6545, /* invalid IP */
61 UNW_EBADFRAME = -6546, /* bad frame */
62 UNW_EINVAL = -6547, /* unsupported operation or bad value */
63 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */
64 UNW_ENOINFO = -6549 /* no unwind info found */
66 , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
101 unw_word_t extra; /* mach_header of mach-o image containing func */
142 UNW_REG_IP = -1, // instruction pointer
143 UNW_REG_SP = -2, // stack pointer
146 // 32-bit x86 registers
158 // 64-bit x86_64 registers
183 UNW_X86_64_XMM6 = 23,
196 // 32-bit ppc register numbers
221 UNW_PPC_R23 = 23,
262 UNW_PPC_MQ = 64,
313 // 64-bit ppc register numbers
338 UNW_PPC64_R23 = 23,
379 // 64: reserved
424 // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
497 // 64-bit ARM64 registers
522 UNW_AARCH64_X23 = 23,
540 UNW_AARCH64_V0 = 64,
645 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
646 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
647 // In this scheme, even though the 64-bit floating point registers D0-D31
648 // overlap physically with the 32-bit floating pointer registers S0-S31,
649 // they are given a non-overlapping range of register numbers.
672 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
673 UNW_ARM_S0 = 64,
705 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
706 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
723 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
724 // 134-142 -- Reserved
726 // 144-150 -- R8_USR-R14_USR
727 // 151-157 -- R8_FIQ-R14_FIQ
728 // 158-159 -- R13_IRQ-R14_IRQ
729 // 160-161 -- R13_ABT-R14_ABT
730 // 162-163 -- R13_UND-R14_UND
731 // 164-165 -- R13_SVC-R14_SVC
732 // 166-191 -- Reserved
737 // 196-199 -- wC4-wC7 (Intel wireless MMX control)
738 // 200-255 -- Reserved
771 // 288-319 -- Reserved for VFP/Neon
772 // 320-8191 -- Reserved
773 // 8192-16383 -- Unspecified vendor co-processor register.
801 UNW_OR1K_R23 = 23,
838 UNW_MIPS_R23 = 23,
881 // for r6 and pre-r6.
882 UNW_MIPS_HI = 64,
911 UNW_SPARC_L7 = 23,
960 // RISC-V registers. These match the DWARF register numbers defined by section
961 // 4 of the RISC-V ELF psABI specification, which can be found at:
963 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
988 UNW_RISCV_X23 = 23,
1029 // 65-95 -- Reserved for future standard extensions
1030 // 96-127 -- v0-v31 (Vector registers)
1031 // 128-3071 -- Reserved for future standard extensions
1032 // 3072-4095 -- Reserved for custom extensions
1033 // 4096-8191 -- CSRs
1035 // VLENB CSR number: 0xC22 -- defined by section 3 of v-spec:
1036 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model
1066 UNW_VE_S23 = 23,
1107 UNW_VE_V0 = 64 + 0,
1108 UNW_VE_V1 = 64 + 1,
1109 UNW_VE_V2 = 64 + 2,
1110 UNW_VE_V3 = 64 + 3,
1111 UNW_VE_V4 = 64 + 4,
1112 UNW_VE_V5 = 64 + 5,
1113 UNW_VE_V6 = 64 + 6,
1114 UNW_VE_V7 = 64 + 7,
1115 UNW_VE_V8 = 64 + 8,
1116 UNW_VE_V9 = 64 + 9,
1117 UNW_VE_V10 = 64 + 10,
1118 UNW_VE_V11 = 64 + 11,
1119 UNW_VE_V12 = 64 + 12,
1120 UNW_VE_V13 = 64 + 13,
1121 UNW_VE_V14 = 64 + 14,
1122 UNW_VE_V15 = 64 + 15,
1123 UNW_VE_V16 = 64 + 16,
1124 UNW_VE_V17 = 64 + 17,
1125 UNW_VE_V18 = 64 + 18,
1126 UNW_VE_V19 = 64 + 19,
1127 UNW_VE_V20 = 64 + 20,
1128 UNW_VE_V21 = 64 + 21,
1129 UNW_VE_V22 = 64 + 22,
1130 UNW_VE_V23 = 64 + 23,
1131 UNW_VE_V24 = 64 + 24,
1132 UNW_VE_V25 = 64 + 25,
1133 UNW_VE_V26 = 64 + 26,
1134 UNW_VE_V27 = 64 + 27,
1135 UNW_VE_V28 = 64 + 28,
1136 UNW_VE_V29 = 64 + 29,
1137 UNW_VE_V30 = 64 + 30,
1138 UNW_VE_V31 = 64 + 31,
1139 UNW_VE_V32 = 64 + 32,
1140 UNW_VE_V33 = 64 + 33,
1141 UNW_VE_V34 = 64 + 34,
1142 UNW_VE_V35 = 64 + 35,
1143 UNW_VE_V36 = 64 + 36,
1144 UNW_VE_V37 = 64 + 37,
1145 UNW_VE_V38 = 64 + 38,
1146 UNW_VE_V39 = 64 + 39,
1147 UNW_VE_V40 = 64 + 40,
1148 UNW_VE_V41 = 64 + 41,
1149 UNW_VE_V42 = 64 + 42,
1150 UNW_VE_V43 = 64 + 43,
1151 UNW_VE_V44 = 64 + 44,
1152 UNW_VE_V45 = 64 + 45,
1153 UNW_VE_V46 = 64 + 46,
1154 UNW_VE_V47 = 64 + 47,
1155 UNW_VE_V48 = 64 + 48,
1156 UNW_VE_V49 = 64 + 49,
1157 UNW_VE_V50 = 64 + 50,
1158 UNW_VE_V51 = 64 + 51,
1159 UNW_VE_V52 = 64 + 52,
1160 UNW_VE_V53 = 64 + 53,
1161 UNW_VE_V54 = 64 + 54,
1162 UNW_VE_V55 = 64 + 55,
1163 UNW_VE_V56 = 64 + 56,
1164 UNW_VE_V57 = 64 + 57,
1165 UNW_VE_V58 = 64 + 58,
1166 UNW_VE_V59 = 64 + 59,
1167 UNW_VE_V60 = 64 + 60,
1168 UNW_VE_V61 = 64 + 61,
1169 UNW_VE_V62 = 64 + 62,
1170 UNW_VE_V63 = 64 + 63,
1218 UNW_S390X_F7 = 23,
1227 // 32-47 Control Registers
1228 // 48-63 Access Registers
1229 UNW_S390X_PSWM = 64,
1231 // 66-67 Reserved
1232 // 68-83 Vector Registers %v16-%v31
1260 UNW_LOONGARCH_R23 = 23,