Lines Matching +full:0 +full:x34000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 PO_DADDIU = 0x64000000, // daddiu rt, rs, imm
24 PO_SD = 0xFC000000, // sd rt, base(offset)
25 PO_LUI = 0x3C000000, // lui rt, imm
26 PO_ORI = 0x34000000, // ori rt, rs, imm
27 PO_DSLL = 0x00000038, // dsll rd, rt, sa
28 PO_JALR = 0x00000009, // jalr rs
29 PO_LD = 0xDC000000, // ld rt, base(offset)
30 PO_B60 = 0x1000000f, // b #60
31 PO_NOP = 0x0, // nop
35 RN_T0 = 0xC,
36 RN_T9 = 0x19,
37 RN_RA = 0x1F,
38 RN_SP = 0x1D,
70 // sd t9, 0(sp) ;save register t9 in patchSled()
80 // ld t9, 0(sp) ;restore register t9 in patchSled()
95 reinterpret_cast<int64_t>(TracingHook) & 0xffff; in patchSled()
97 (reinterpret_cast<int64_t>(TracingHook) >> 16) & 0xffff; in patchSled()
99 (reinterpret_cast<int64_t>(TracingHook) >> 32) & 0xffff; in patchSled()
101 (reinterpret_cast<int64_t>(TracingHook) >> 48) & 0xffff; in patchSled()
102 uint32_t LoFunctionID = FuncId & 0xffff; in patchSled()
103 uint32_t HiFunctionID = (FuncId >> 16) & 0xffff; in patchSled()
105 RegNum::RN_RA, 0x8); in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
112 Address[6] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0, in patchSled()
113 RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
116 Address[8] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0, in patchSled()
117 RegNum::RN_T9, RegNum::RN_T9, 0x10); in patchSled()
120 Address[10] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, in patchSled()
123 0x0, RegNum::RN_RA, 0X0); in patchSled()
127 RegNum::RN_T9, 0x0); in patchSled()
129 RegNum::RN_RA, 0x8); in patchSled()
131 RegNum::RN_SP, 0x10); in patchSled()
133 PatchOpcodes::PO_DADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xfff0); in patchSled()