Lines Matching +full:0 +full:x34000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 PO_ADDIU = 0x24000000, // addiu rt, rs, imm
24 PO_SW = 0xAC000000, // sw rt, offset(sp)
25 PO_LUI = 0x3C000000, // lui rs, %hi(address)
26 PO_ORI = 0x34000000, // ori rt, rs, %lo(address)
27 PO_JALR = 0x0000F809, // jalr rs
28 PO_LW = 0x8C000000, // lw rt, offset(address)
29 PO_B44 = 0x1000000b, // b #44
30 PO_NOP = 0x0, // nop
34 RN_T0 = 0x8,
35 RN_T9 = 0x19,
36 RN_RA = 0x1F,
37 RN_SP = 0x1D,
70 // sw t9, 0(sp) ;save register t9 in patchSled()
76 // lw t9, 0(sp) ;restore register t9 in patchSled()
99 reinterpret_cast<int32_t>(TracingHook) & 0xffff; in patchSled()
101 (reinterpret_cast<int32_t>(TracingHook) >> 16) & 0xffff; in patchSled()
102 uint32_t LoFunctionID = FuncId & 0xffff; in patchSled()
103 uint32_t HiFunctionID = (FuncId >> 16) & 0xffff; in patchSled()
105 RegNum::RN_RA, 0x4); in patchSled()
107 RegNum::RN_T9, 0x0); in patchSled()
108 Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, in patchSled()
112 Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, in patchSled()
115 0x0, RegNum::RN_RA, 0X0); in patchSled()
119 RegNum::RN_T9, 0x0); in patchSled()
121 RegNum::RN_RA, 0x4); in patchSled()
123 RegNum::RN_SP, 0x8); in patchSled()
125 PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xFFF8); in patchSled()