Lines Matching refs:phases

340 // affect the phase, starting with the earliest phases, and record which
342 phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
345   phases::ID FinalPhase;
353     FinalPhase = phases::Preprocess;
362     FinalPhase = phases::Precompile;
375     FinalPhase = phases::Compile;
379     FinalPhase = phases::Backend;
383     FinalPhase = phases::Assemble;
386     FinalPhase = phases::IfsMerge;
390     FinalPhase = phases::Link;
2862     typedef const llvm::SmallVectorImpl<phases::ID> PhasesTy;
2904                          phases::ID CurPhase, phases::ID FinalPhase,
3296                          phases::ID CurPhase, phases::ID FinalPhase,
3317       if (CompileDeviceOnly || CurPhase == phases::Backend) {
3323             // Skip the phases that were already dealt with.
3333             if (Ph == phases::Assemble)
3379       } else if (CurPhase > phases::Backend) {
3386       assert(CurPhase < phases::Backend && "Generating single CUDA "
3470                          phases::ID CurPhase, phases::ID FinalPhase,
3476       // backend and assemble phases to output LLVM IR. Except for generating
3482       assert(((CurPhase == phases::Link && Relocatable) ||
3490       if (!Relocatable && CurPhase == phases::Backend && !EmitLLVM &&
3499             // When LTO is enabled, skip the backend and assemble phases and
3509             // compiler phases, including backend and assemble phases.
3522                   C, Args, phases::Backend, CudaDeviceActions[I],
3525                 C, Args, phases::Assemble, BackendAction,
3566       } else if (CurPhase == phases::Link) {
3608                (!ShouldLink && CurPhase == phases::Assemble)))
3739                                    phases::ID CurPhase, phases::ID FinalPhase,
3995   phases::ID FinalPhase = getFinalPhase(Args, &FinalPhaseArg);
3997   if (FinalPhase == phases::Link) {
4028   if (FinalPhase == phases::Preprocess || Args.hasArg(options::OPT__SLASH_Y_)) {
4048     phases::ID InitialPhase = PL[0];
4067       else if (InitialPhase == phases::Compile &&
4086       if (FinalPhase >= phases::Compile) {
4090         for (phases::ID Phase : types::getCompilationPhases(HeaderType))
4106   if (FinalPhase == phases::Link && LastPLSize == 1) {
4191     for (phases::ID Phase : PL) {
4201       if (Phase == phases::Link) {
4217       if (Phase == phases::IfsMerge) {
4224       if (Phase == phases::Precompile && ExtractAPIAction) {
4275     if (getFinalPhase(Args, &FinalPhaseArg) == phases::Link)
4309         Args.hasArg(options::OPT_c) ? phases::Compile : phases::IfsMerge);
4331         case phases::Compile: {
4341         case phases::IfsMerge: {
4583         getFinalPhase(Args) == phases::Preprocess))
4629     for (phases::ID Phase : PL) {
4630       if (Phase == phases::Link) {
4752     Compilation &C, const ArgList &Args, phases::ID Phase, Action *Input,
4759   if (Phase == phases::Assemble && Input->getType() != types::TY_PP_Asm)
4764   case phases::Link:
4766   case phases::IfsMerge:
4768   case phases::Preprocess: {
4792   case phases::Precompile: {
4826   case phases::Compile: {
4850   case phases::Backend: {
4888   case phases::Assemble: