Lines Matching refs:IVSigned
2855 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPOuterLoop() local
2879 RT.emitForNext(*this, S.getBeginLoc(), IVSize, IVSigned, LoopArgs.IL, in EmitOMPOuterLoop()
2920 [&S, &LoopArgs, LoopExit, &CodeGenLoop, IVSize, IVSigned, &CodeGenOrdered, in EmitOMPOuterLoop()
2933 [IVSize, IVSigned, Loc, &CodeGenOrdered](CodeGenFunction &CGF) { in EmitOMPOuterLoop()
2934 CodeGenOrdered(CGF, Loc, IVSize, IVSigned); in EmitOMPOuterLoop()
3029 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPForOuterLoop() local
3039 IVSigned, Ordered, DipatchRTInputValues); in EmitOMPForOuterLoop()
3042 IVSize, IVSigned, Ordered, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, in EmitOMPForOuterLoop()
3050 const bool IVSigned) { in EmitOMPForOuterLoop() argument
3053 IVSigned); in EmitOMPForOuterLoop()
3073 const unsigned IVSize, const bool IVSigned) {} in emitEmptyOrdered() argument
3089 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeOuterLoop() local
3092 IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, in EmitOMPDistributeOuterLoop()
3420 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPWorksharingLoop() local
3453 [IVSize, IVSigned, Ordered, IL, LB, UB, ST, StaticChunkedOne, Chunk, in EmitOMPWorksharingLoop()
3462 IVSize, IVSigned, Ordered, IL.getAddress(), LB.getAddress(), in EmitOMPWorksharingLoop()
5750 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeLoop() local
5767 IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(), in EmitOMPDistributeLoop()