Lines Matching +full:p +full:- +full:tile
1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
140 enum { FE_NOSET = -1, FE_FALSE, FE_TRUE }; in initFeatureMap()
143 bool HasAVX10 = Features.lookup("avx10.1-256"); in initFeatureMap()
144 bool HasAVX10_512 = Features.lookup("avx10.1-512"); in initFeatureMap()
148 // Expand general-regs-only to -x86, -mmx and -sse in initFeatureMap()
149 if (Feature == "+general-regs-only") { in initFeatureMap()
150 UpdatedFeaturesVec.push_back("-x87"); in initFeatureMap()
151 UpdatedFeaturesVec.push_back("-mmx"); in initFeatureMap()
152 UpdatedFeaturesVec.push_back("-sse"); in initFeatureMap()
162 } else if (HasAVX10 && Feature == "-avx10.1-256") { in initFeatureMap()
165 } else if (HasAVX10_512 && Feature == "-avx10.1-512") { in initFeatureMap()
174 } else if (HasAVX512F && Feature == "-avx512f") { in initFeatureMap()
179 } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512") { in initFeatureMap()
187 // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512 in initFeatureMap()
190 UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512" in initFeatureMap()
194 << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512"; in initFeatureMap()
198 << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512"); in initFeatureMap()
199 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512"); in initFeatureMap()
210 if (I != Features.end() && I->getValue() && in initFeatureMap()
211 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) in initFeatureMap()
217 if (I != Features.end() && I->getValue() && in initFeatureMap()
218 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) in initFeatureMap()
223 if (I != Features.end() && I->getValue() && in initFeatureMap()
224 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) in initFeatureMap()
229 if (I != Features.end() && I->getValue() && in initFeatureMap()
230 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) in initFeatureMap()
240 // via the -msse4/-mno-sse4 command line alias. Handle this the same way in setFeatureEnabled()
241 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if in setFeatureEnabled()
253 /// handleTargetFeatures - Perform initialization based on the user
303 } else if (Feature == "+avx10.1-256") { in handleTargetFeatures()
305 } else if (Feature == "+avx10.1-512") { in handleTargetFeatures()
386 } else if (Feature == "+retpoline-external-thunk") { in handleTargetFeatures()
406 } else if (Feature == "+amx-bf16") { in handleTargetFeatures()
408 } else if (Feature == "+amx-fp16") { in handleTargetFeatures()
410 } else if (Feature == "+amx-int8") { in handleTargetFeatures()
412 } else if (Feature == "+amx-tile") { in handleTargetFeatures()
414 } else if (Feature == "+amx-complex") { in handleTargetFeatures()
446 } else if (Feature == "+inline-asm-use-gpr32") { in handleTargetFeatures()
462 } else if (Feature == "+branch-hint") { in handleTargetFeatures()
482 // bfloat16 is treated as a 32-bit float, arithmetic operations are in handleTargetFeatures()
483 // performed in 32-bit, and the result is converted back to bfloat16. in handleTargetFeatures()
484 // Truncation and extension between bfloat16 and 32-bit float are supported in handleTargetFeatures()
485 // by the compiler-rt library. However, native bfloat16 support is currently in handleTargetFeatures()
489 // for bfloat16 arithmetic operations in the front-end. in handleTargetFeatures()
509 // FIXME: We should allow long double type on 32-bits to match with GCC. in handleTargetFeatures()
517 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
549 // FIXME: We are hard-coding the tune parameters based on the CPU, but they in getTargetDefines()
550 // truly should be based on -mtune options. in getTargetDefines()
614 // Gracemont and later atom-cores use P-core cpu macros. in getTargetDefines()
646 // remove it at some point. We've never exposed fine-grained names for in getTargetDefines()
667 // architecture is specified but -m3dnow is explicitly provided. The in getTargetDefines()
754 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, in getTargetDefines()
755 // the feature flag only applies to 64-bit mode. in getTargetDefines()
1000 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. in getTargetDefines()
1004 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. in getTargetDefines()
1054 .Case("amx-bf16", true) in isValidFeatureName()
1055 .Case("amx-complex", true) in isValidFeatureName()
1056 .Case("amx-fp16", true) in isValidFeatureName()
1057 .Case("amx-int8", true) in isValidFeatureName()
1058 .Case("amx-tile", true) in isValidFeatureName()
1060 .Case("avx10.1-256", true) in isValidFeatureName()
1061 .Case("avx10.1-512", true) in isValidFeatureName()
1098 .Case("general-regs-only", true) in isValidFeatureName()
1169 .Case("amx-bf16", HasAMXBF16) in hasFeature()
1170 .Case("amx-complex", HasAMXCOMPLEX) in hasFeature()
1171 .Case("amx-fp16", HasAMXFP16) in hasFeature()
1172 .Case("amx-int8", HasAMXINT8) in hasFeature()
1173 .Case("amx-tile", HasAMXTILE) in hasFeature()
1175 .Case("avx10.1-256", HasAVX10_1) in hasFeature()
1176 .Case("avx10.1-512", HasAVX10_1_512) in hasFeature()
1238 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) in hasFeature()
1281 .Case("branch-hint", HasBranchHint) in hasFeature()
1395 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 in validateAsmConstraint()
1397 case 'Z': // 32-bit unsigned integer constant for use with zero-extending in validateAsmConstraint()
1409 Info.setRequiresImmediate(-128, 127); in validateAsmConstraint()
1432 case 'Y': // 'Y' is the first character for several 2-character constraints. in validateAsmConstraint()
1441 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. in validateAsmConstraint()
1442 case 'm': // Any MMX register, when inter-unit moves enabled. in validateAsmConstraint()
1443 case 'k': // AVX512 arch mask registers: k1-k7. in validateAsmConstraint()
1493 Name += Len - 1; in validateAsmConstraint()
1502 …------------------------------------+-------------------------+-----------------------------------…
1504 …------------------------------------+-------------------------+-----------------------------------…
1505 …intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manua…
1507 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX…
1508 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.ht…
1509 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-18…
1510 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.…
1512 … 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBrid…
1513 … 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu…
1514 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswe…
1515 // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broad…
1516 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/s…
1517 … 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html…
1519 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_L…
1520 … 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory…
1521 …s://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manua…
1522 …------------------------------------+-------------------------+-----------------------------------…
1660 // Registers k0-k7 (AVX512) size limit is 64 bit. in validateOperandSize()
1668 // 'Y' is the first character for several 2-character constraints. in validateOperandSize()
1701 // 512-bit zmm registers can be used if target supports AVX512F and in validateOperandSize()
1705 // 256-bit ymm registers can be used if target supports AVX. in validateOperandSize()
1719 Constraint += Len - 1; in convertConstraint()
1735 case 'p': // Keep 'p' constraint (address). in convertConstraint()
1736 return std::string("p"); in convertConstraint()
1801 return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - in getTargetBuiltins()
1807 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); in getTargetBuiltins()