Lines Matching +full:gpu +full:- +full:id

1 //===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
24 #define BUILTIN(ID, TYPE, ATTRS) \ argument
25 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
26 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ argument
27 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::HEADER, ALL_LANGUAGES},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ argument
29 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
40 "NVPTX only supports 32- and 64-bit modes."); in NVPTXTargetInfo()
62 GPU = OffloadArch::UNUSED; in NVPTXTargetInfo()
69 resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"); in NVPTXTargetInfo()
72 "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"); in NVPTXTargetInfo()
74 resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64"); in NVPTXTargetInfo()
106 PointerWidth = HostTarget->getPointerWidth(LangAS::Default); in NVPTXTargetInfo()
107 PointerAlign = HostTarget->getPointerAlign(LangAS::Default); in NVPTXTargetInfo()
108 BoolWidth = HostTarget->getBoolWidth(); in NVPTXTargetInfo()
109 BoolAlign = HostTarget->getBoolAlign(); in NVPTXTargetInfo()
110 IntWidth = HostTarget->getIntWidth(); in NVPTXTargetInfo()
111 IntAlign = HostTarget->getIntAlign(); in NVPTXTargetInfo()
112 HalfWidth = HostTarget->getHalfWidth(); in NVPTXTargetInfo()
113 HalfAlign = HostTarget->getHalfAlign(); in NVPTXTargetInfo()
114 FloatWidth = HostTarget->getFloatWidth(); in NVPTXTargetInfo()
115 FloatAlign = HostTarget->getFloatAlign(); in NVPTXTargetInfo()
116 DoubleWidth = HostTarget->getDoubleWidth(); in NVPTXTargetInfo()
117 DoubleAlign = HostTarget->getDoubleAlign(); in NVPTXTargetInfo()
118 LongWidth = HostTarget->getLongWidth(); in NVPTXTargetInfo()
119 LongAlign = HostTarget->getLongAlign(); in NVPTXTargetInfo()
120 LongLongWidth = HostTarget->getLongLongWidth(); in NVPTXTargetInfo()
121 LongLongAlign = HostTarget->getLongLongAlign(); in NVPTXTargetInfo()
122 MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0, in NVPTXTargetInfo()
124 NewAlign = HostTarget->getNewAlign(); in NVPTXTargetInfo()
126 HostTarget->getDefaultAlignForAttributeAligned(); in NVPTXTargetInfo()
127 SizeType = HostTarget->getSizeType(); in NVPTXTargetInfo()
128 IntMaxType = HostTarget->getIntMaxType(); in NVPTXTargetInfo()
129 PtrDiffType = HostTarget->getPtrDiffType(LangAS::Default); in NVPTXTargetInfo()
130 IntPtrType = HostTarget->getIntPtrType(); in NVPTXTargetInfo()
131 WCharType = HostTarget->getWCharType(); in NVPTXTargetInfo()
132 WIntType = HostTarget->getWIntType(); in NVPTXTargetInfo()
133 Char16Type = HostTarget->getChar16Type(); in NVPTXTargetInfo()
134 Char32Type = HostTarget->getChar32Type(); in NVPTXTargetInfo()
135 Int64Type = HostTarget->getInt64Type(); in NVPTXTargetInfo()
136 SigAtomicType = HostTarget->getSigAtomicType(); in NVPTXTargetInfo()
137 ProcessIDType = HostTarget->getProcessIDType(); in NVPTXTargetInfo()
139 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); in NVPTXTargetInfo()
140 UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment(); in NVPTXTargetInfo()
141 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); in NVPTXTargetInfo()
142 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); in NVPTXTargetInfo()
148 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); in NVPTXTargetInfo()
151 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the in NVPTXTargetInfo()
153 // - SuitableAlign: Not visible across the host/device boundary, and may in NVPTXTargetInfo()
156 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same in NVPTXTargetInfo()
178 if (GPU == OffloadArch::UNUSED && !HostTarget) in getTargetDefines()
182 // Set __CUDA_ARCH__ for the GPU specified. in getTargetDefines()
184 switch (GPU) { in getTargetDefines()
240 assert(false && "No GPU arch when compiling CUDA device code."); in getTargetDefines()
288 if (GPU == OffloadArch::SM_90a) in getTargetDefines()
295 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); in getTargetBuiltins()