44   // so set preferred for small types to 32.  in setABIAAPCS()
47                         ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"  in setABIAAPCS()
48                         : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",  in setABIAAPCS()
53                     "-m:w"  in setABIAAPCS()
54                     "-p:32:32"  in setABIAAPCS()
58                     "-a:0:32"  in setABIAAPCS()
63     resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");  in setABIAAPCS()
66                         ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"  in setABIAAPCS()
67                         : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");  in setABIAAPCS()
81     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;  in setABIAPCS()
94   ZeroLengthBitfieldBoundary = 32;  in setABIAPCS()
98     resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_");  in setABIAPCS()
102             ? "E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"  in setABIAPCS()
103             : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32",  in setABIAPCS()
108             ? "E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"  in setABIAPCS()
109             : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");  in setABIAPCS()
145   // Cortex M does not support 8 byte atomics, while general Thumb2 does.  in setAtomic()
146   if (ArchProfile == llvm::ARM::ProfileKind::M) {  in setAtomic()
147     MaxAtomicPromoteWidth = 32;  in setAtomic()
149       MaxAtomicInlineWidth = 32;  in setAtomic()
186     return "6M";  in getCPUAttr()
194     return "7M";  in getCPUAttr()
248   case llvm::ARM::ProfileKind::M:  in getCPUProfile()
249     return "M";  in getCPUProfile()
295     // The backend is hardwired to assume AAPCS for M-class processors, ensure  in ARMTargetInfo()
299         ArchProfile == llvm::ARM::ProfileKind::M) {  in ARMTargetInfo()
401   return a.isArmT32() && (Profile == llvm::ARM::ProfileKind::M);  in isBranchProtectionSupportedArch()
575       if (CPUProfile != "M" || ArchVersion != 8) {  in handleTargetFeatures()
616     if (ArchProfile == llvm::ARM::ProfileKind::M)  in handleTargetFeatures()
624     if (ArchProfile == llvm::ARM::ProfileKind::M)  in handleTargetFeatures()
764   // is not defined for the M-profile.  in getTargetDefines()
766   if (CPUProfile.empty() || ArchProfile != llvm::ARM::ProfileKind::M)  in getTargetDefines()
770   // Thumb ISA (including v6-M and v8-M Baseline).  It is set to 2 if the  in getTargetDefines()
772   // v7 and v8 architectures excluding v8-M Baseline.  in getTargetDefines()
778   // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit  in getTargetDefines()
782   // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)  in getTargetDefines()
784   // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.  in getTargetDefines()
797   if (ArchVersion == 5 || (ArchVersion == 6 && CPUProfile != "M") ||  in getTargetDefines()
918   // ACLE 6.4.9 32-bit SIMD instructions  in getTargetDefines()
919   if ((CPUProfile != "M" && ArchVersion >= 6) || (CPUProfile == "M" && DSP))  in getTargetDefines()
977   if (ArchVersion == 8 && ArchProfile == llvm::ARM::ProfileKind::M)  in getTargetDefines()
980   if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {  in getTargetDefines()
994   if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6) {  in getTargetDefines()
1218   case 'M':  in validateAsmConstraint()
1225       // between 0 and 32  in validateAsmConstraint()
1266     case 'm': // valid address for Neon element and structure load/store  in validateAsmConstraint()
1312       // A register of size 32 cannot fit a vector type.  in validateConstraintModifier()
1464   resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");  in CygwinARMTargetInfo()