2  * Double-precision vector log2 function.
4  * Copyright (c) 2022-2024, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19   /* Each coefficient was generated to approximate log(r) for |r| < 0x1.fp-9
22   .c0 = V2 (-0x1.71547652b8300p-1),
23   .c1 = 0x1.ec709dc340953p-2,
24   .c2 = V2 (-0x1.71547651c8f35p-2),
25   .c3 = 0x1.2777ebe12dda5p-2,
26   .c4 = -0x1.ec738d616fe26p-3,
31      optimised register use subnormals are detected after offset has been
32      subtracted, so lower bound - offset (which wraps around).  */
33   .offset_lower_bound = V2 (0x0010000000000000 - 0x3fe6900900000000),
34   .special_bound = V4 (0x7fe00000), /* asuint64(inf) - asuint64(0x1p-1022).  */
38 #define IndexMask (N - 1)
51       = (vgetq_lane_u64 (i, 0) >> (52 - V_LOG2_TABLE_BITS)) & IndexMask;  in lookup()
53       = (vgetq_lane_u64 (i, 1) >> (52 - V_LOG2_TABLE_BITS)) & IndexMask;  in lookup()
62 special_case (float64x2_t hi, uint64x2_t u_off, float64x2_t y, float64x2_t r2,  in special_case()  argument
65   float64x2_t x = vreinterpretq_f64_u64 (vaddq_u64 (u_off, d->off));  in special_case()
66   return v_call_f64 (log2, x, vfmaq_f64 (hi, y, r2), vmovl_u32 (special));  in special_case()
69 /* Double-precision vector log2 routine. Implements the same algorithm as
72    _ZGVnN2v_log2(0x1.0b556b093869bp+0) got 0x1.fffb34198d9dap-5
73 				      want 0x1.fffb34198d9ddp-5.  */
78   /* To avoid having to mov x out of the way, keep u after offset has been  in V_NAME_D1()
79      applied, and recover x by adding the offset back in the special-case  in V_NAME_D1()
82   uint64x2_t u_off = vsubq_u64 (u, d->off);  in V_NAME_D1()
88   uint64x2_t iz = vsubq_u64 (u, vandq_u64 (u_off, d->sign_exp_mask));  in V_NAME_D1()
93   uint32x2_t special = vcge_u32 (vsubhn_u64 (u_off, d->offset_lower_bound),  in V_NAME_D1()
94 				 vget_low_u32 (d->special_bound));  in V_NAME_D1()
96   /* log2(x) = log1p(z/c-1)/log(2) + log2(c) + k.  */  in V_NAME_D1()
97   float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc);  in V_NAME_D1()
100   float64x2_t invln2_and_c4 = vld1q_f64 (&d->invln2);  in V_NAME_D1()
105   float64x2_t odd_coeffs = vld1q_f64 (&d->c1);  in V_NAME_D1()
106   float64x2_t y = vfmaq_laneq_f64 (d->c2, r, odd_coeffs, 1);  in V_NAME_D1()  local
107   float64x2_t p = vfmaq_laneq_f64 (d->c0, r, odd_coeffs, 0);  in V_NAME_D1()
108   y = vfmaq_laneq_f64 (y, r2, invln2_and_c4, 1);  in V_NAME_D1()
109   y = vfmaq_f64 (p, r2, y);  in V_NAME_D1()
112     return special_case (hi, u_off, y, r2, special, d);  in V_NAME_D1()
113   return vfmaq_f64 (hi, y, r2);  in V_NAME_D1()
118 TEST_INTERVAL (V_NAME_D1 (log2), -0.0, -0x1p126, 100)
119 TEST_INTERVAL (V_NAME_D1 (log2), 0x1p-149, 0x1p-126, 4000)
120 TEST_INTERVAL (V_NAME_D1 (log2), 0x1p-126, 0x1p-23, 50000)
121 TEST_INTERVAL (V_NAME_D1 (log2), 0x1p-23, 1.0, 50000)