2  * Double-precision vector log10(x) function.
4  * Copyright (c) 2022-2024, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
22   .c0 = V2 (-0x1.bcb7b1526e506p-3),
23   .c1 = 0x1.287a7636be1d1p-3,
24   .c2 = V2 (-0x1.bcb7b158af938p-4),
25   .c3 = 0x1.63c78734e6d07p-4,
26   .c4 = V2 (-0x1.287461742fee4p-4),
27   .invln10 = 0x1.bcb7b1526e50ep-2,
28   .log10_2 = 0x1.34413509f79ffp-2,
32      optimised register use subnormals are detected after offset has been
33      subtracted, so lower bound - offset (which wraps around).  */
34   .offset_lower_bound = V2 (0x0010000000000000 - 0x3fe6900900000000),
35   .special_bound = V4 (0x7fe00000), /* asuint64(inf) - 0x0010000000000000.  */
39 #define IndexMask (N - 1)
52       = (vgetq_lane_u64 (i, 0) >> (52 - V_LOG10_TABLE_BITS)) & IndexMask;  in lookup()
54       = (vgetq_lane_u64 (i, 1) >> (52 - V_LOG10_TABLE_BITS)) & IndexMask;  in lookup()
63 special_case (float64x2_t hi, uint64x2_t u_off, float64x2_t y, float64x2_t r2,  in special_case()  argument
66   float64x2_t x = vreinterpretq_f64_u64 (vaddq_u64 (u_off, d->off));  in special_case()
67   return v_call_f64 (log10, x, vfmaq_f64 (hi, y, r2), vmovl_u32 (special));  in special_case()
70 /* Fast implementation of double-precision vector log10
71    is a slight modification of double-precision vector log.
74    _ZGVnN2v_log10(0x1.13192407fcb46p+0) got 0x1.fff6be3cae4bbp-6
75 				       want 0x1.fff6be3cae4b9p-6.  */
80   /* To avoid having to mov x out of the way, keep u after offset has been  in V_NAME_D1()
81      applied, and recover x by adding the offset back in the special-case  in V_NAME_D1()
84   uint64x2_t u_off = vsubq_u64 (u, d->off);  in V_NAME_D1()
90   uint64x2_t iz = vsubq_u64 (u, vandq_u64 (u_off, d->sign_exp_mask));  in V_NAME_D1()
95   uint32x2_t special = vcge_u32 (vsubhn_u64 (u_off, d->offset_lower_bound),  in V_NAME_D1()
96 				 vget_low_u32 (d->special_bound));  in V_NAME_D1()
98   /* log10(x) = log1p(z/c-1)/log(10) + log10(c) + k*log10(2).  */  in V_NAME_D1()
99   float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc);  in V_NAME_D1()
105   float64x2_t cte = vld1q_f64 (&d->invln10);  in V_NAME_D1()
108   /* y = log10(1+r) + n * log10(2).  */  in V_NAME_D1()
111   /* y = r2*(A0 + r*A1 + r2*(A2 + r*A3 + r2*A4)) + hi.  */  in V_NAME_D1()
113   float64x2_t odd_coeffs = vld1q_f64 (&d->c1);  in V_NAME_D1()
114   float64x2_t y = vfmaq_laneq_f64 (d->c2, r, odd_coeffs, 1);  in V_NAME_D1()  local
115   float64x2_t p = vfmaq_laneq_f64 (d->c0, r, odd_coeffs, 0);  in V_NAME_D1()
116   y = vfmaq_f64 (y, d->c4, r2);  in V_NAME_D1()
117   y = vfmaq_f64 (p, y, r2);  in V_NAME_D1()
120     return special_case (hi, u_off, y, r2, special, d);  in V_NAME_D1()
121   return vfmaq_f64 (hi, y, r2);  in V_NAME_D1()
126 TEST_INTERVAL (V_NAME_D1 (log10), -0.0, -inf, 1000)
127 TEST_INTERVAL (V_NAME_D1 (log10), 0, 0x1p-149, 1000)
128 TEST_INTERVAL (V_NAME_D1 (log10), 0x1p-149, 0x1p-126, 4000)
129 TEST_INTERVAL (V_NAME_D1 (log10), 0x1p-126, 0x1p-23, 50000)
130 TEST_INTERVAL (V_NAME_D1 (log10), 0x1p-23, 1.0, 50000)