Lines Matching +full:offset +full:- +full:y
2 * Double-precision vector log(x) function.
4 * Copyright (c) 2019-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19 /* Rel error: 0x1.6272e588p-56 in [ -0x1.fc1p-9 0x1.009p-8 ]. */
20 .c0 = V2 (-0x1.ffffffffffff7p-2),
21 .c1 = 0x1.55555555170d4p-2,
22 .c2 = V2 (-0x1.0000000399c27p-2),
23 .c3 = 0x1.999b2e90e94cap-3,
24 .c4 = -0x1.554e550bd501ep-3,
25 .ln2 = 0x1.62e42fefa39efp-1,
29 optimised register use subnormals are detected after offset has been
30 subtracted, so lower bound - offset (which wraps around). */
31 .offset_lower_bound = V2 (0x0010000000000000 - 0x3fe6900900000000),
32 .special_bound = V4 (0x7fe00000), /* asuint64(inf) - asuint64(0x1p-126). */
36 #define IndexMask (N - 1)
47 /* Since N is a power of 2, n % N = n & (N - 1). */ in lookup()
49 uint64_t i0 = (vgetq_lane_u64 (i, 0) >> (52 - V_LOG_TABLE_BITS)) & IndexMask; in lookup()
50 uint64_t i1 = (vgetq_lane_u64 (i, 1) >> (52 - V_LOG_TABLE_BITS)) & IndexMask; in lookup()
59 special_case (float64x2_t hi, uint64x2_t u_off, float64x2_t y, float64x2_t r2, in special_case() argument
62 float64x2_t x = vreinterpretq_f64_u64 (vaddq_u64 (u_off, d->off)); in special_case()
63 return v_call_f64 (log, x, vfmaq_f64 (hi, y, r2), vmovl_u32 (special)); in special_case()
66 /* Double-precision vector log routine.
68 _ZGVnN2v_log(0x1.a6129884398a3p+0) got 0x1.ffffff1cca043p-2
69 want 0x1.ffffff1cca045p-2. */
74 /* To avoid having to mov x out of the way, keep u after offset has been in V_NAME_D1()
75 applied, and recover x by adding the offset back in the special-case in V_NAME_D1()
78 uint64x2_t u_off = vsubq_u64 (u, d->off); in V_NAME_D1()
84 uint64x2_t iz = vsubq_u64 (u, vandq_u64 (u_off, d->sign_exp_mask)); in V_NAME_D1()
89 uint32x2_t special = vcge_u32 (vsubhn_u64 (u_off, d->offset_lower_bound), in V_NAME_D1()
90 vget_low_u32 (d->special_bound)); in V_NAME_D1()
92 /* log(x) = log1p(z/c-1) + log(c) + k*Ln2. */ in V_NAME_D1()
93 float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc); in V_NAME_D1()
97 float64x2_t ln2_and_c4 = vld1q_f64 (&d->ln2); in V_NAME_D1()
100 /* y = r2*(A0 + r*A1 + r2*(A2 + r*A3 + r2*A4)) + hi. */ in V_NAME_D1()
101 float64x2_t odd_coeffs = vld1q_f64 (&d->c1); in V_NAME_D1()
103 float64x2_t y = vfmaq_laneq_f64 (d->c2, r, odd_coeffs, 1); in V_NAME_D1() local
104 float64x2_t p = vfmaq_laneq_f64 (d->c0, r, odd_coeffs, 0); in V_NAME_D1()
105 y = vfmaq_laneq_f64 (y, r2, ln2_and_c4, 1); in V_NAME_D1()
106 y = vfmaq_f64 (p, r2, y); in V_NAME_D1()
109 return special_case (hi, u_off, y, r2, special, d); in V_NAME_D1()
110 return vfmaq_f64 (hi, y, r2); in V_NAME_D1()
117 TEST_INTERVAL (V_NAME_D1 (log), 0x1p-4, 0x1p4, 400000)