Revision tags: release/11.2.0 |
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1de7b4b8 |
| 27-Nov-2017 |
Pedro F. Giffuni <pfg@FreeBSD.org> |
various: general adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error
various: general adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task.
The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
No functional change intended.
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Revision tags: release/10.4.0, release/11.1.0, release/11.0.1, release/11.0.0 |
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3dd79610 |
| 08-Jul-2016 |
Alexander Motin <mav@FreeBSD.org> |
Add emulation for multiple (up to 16) MSI vectors for AHCI.
It was useless before, but may improve performance now if multiple devices are configured and guest supports this feature.
Sponsored by:
Add emulation for multiple (up to 16) MSI vectors for AHCI.
It was useless before, but may improve performance now if multiple devices are configured and guest supports this feature.
Sponsored by: iXsystems, Inc.
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7e12dfe5 |
| 06-Jul-2016 |
Enji Cooper <ngie@FreeBSD.org> |
Fix CTASSERT issue in a more clean way
- Replace all CTASSERT macro instances with static_assert's. - Remove the WRAPPED_CTASSERT macro; it's now an unnecessary obfuscation. - Localize all static_as
Fix CTASSERT issue in a more clean way
- Replace all CTASSERT macro instances with static_assert's. - Remove the WRAPPED_CTASSERT macro; it's now an unnecessary obfuscation. - Localize all static_assert's to the structures being tested. - Sort some headers per-style(9).
Approved by: re (hrs) Differential Revision: https://reviews.freebsd.org/D7130 MFC after: 1 week X-MFC with: r302364 Reviewed by: ed, grehan (maintainer) Submitted by: ed Sponsored by: EMC / Isilon Storage Division
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0edd2576 |
| 16-Apr-2016 |
Glen Barber <gjb@FreeBSD.org> |
MFH
Sponsored by: The FreeBSD Foundation
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5c40acf8 |
| 13-Apr-2016 |
John Baldwin <jhb@FreeBSD.org> |
Handle PBA that shares a page with MSI-X table for passthrough devices.
If the PBA shares a page with the MSI-X table, map the shared page via /dev/mem and emulate accesses to the portion of the PBA
Handle PBA that shares a page with MSI-X table for passthrough devices.
If the PBA shares a page with the MSI-X table, map the shared page via /dev/mem and emulate accesses to the portion of the PBA in the shared page by accessing the mapped page.
Reviewed by: grehan MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D5919
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Revision tags: release/10.3.0, release/10.2.0 |
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9268022b |
| 19-Nov-2014 |
Simon J. Gerraty <sjg@FreeBSD.org> |
Merge from head@274682
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Revision tags: release/10.1.0 |
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246e7a2b |
| 02-Sep-2014 |
Neel Natu <neel@FreeBSD.org> |
IFC @r269962
Submitted by: Anish Gupta (akgupt3@gmail.com)
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ee7b0571 |
| 19-Aug-2014 |
Simon J. Gerraty <sjg@FreeBSD.org> |
Merge head from 7/28
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1b833d53 |
| 13-Aug-2014 |
Alexander V. Chernikov <melifaro@FreeBSD.org> |
Sync to HEAD@r269943.
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12a6eb99 |
| 08-Aug-2014 |
Neel Natu <neel@FreeBSD.org> |
Support PCI extended config space in bhyve.
Add the ACPI MCFG table to advertise the extended config memory window.
Introduce a new flag MEM_F_IMMUTABLE for memory ranges that cannot be deleted or
Support PCI extended config space in bhyve.
Add the ACPI MCFG table to advertise the extended config memory window.
Introduce a new flag MEM_F_IMMUTABLE for memory ranges that cannot be deleted or moved in the guest's address space. The PCI extended config space is an example of an immutable memory range.
Add emulation for the "movzw" instruction. This instruction is used by FreeBSD to read a 16-bit extended config space register.
CR: https://phabric.freebsd.org/D505 Reviewed by: jhb, grehan Requested by: tychon
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Revision tags: release/9.3.0 |
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6cec9cad |
| 03-Jun-2014 |
Peter Grehan <grehan@FreeBSD.org> |
MFC @ r266724
An SVM update will follow this.
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414fdaf0 |
| 21-May-2014 |
Alan Somers <asomers@FreeBSD.org> |
IFC @266473
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b3e9732a |
| 15-May-2014 |
John Baldwin <jhb@FreeBSD.org> |
Implement a PCI interrupt router to route PCI legacy INTx interrupts to the legacy 8259A PICs. - Implement an ICH-comptabile PCI interrupt router on the lpc device with 8 steerable pins configured
Implement a PCI interrupt router to route PCI legacy INTx interrupts to the legacy 8259A PICs. - Implement an ICH-comptabile PCI interrupt router on the lpc device with 8 steerable pins configured via config space access to byte-wide registers at 0x60-63 and 0x68-6b. - For each configured PCI INTx interrupt, route it to both an I/O APIC pin and a PCI interrupt router pin. When a PCI INTx interrupt is asserted, ensure that both pins are asserted. - Provide an initial routing of PCI interrupt router (PIRQ) pins to 8259A pins (ISA IRQs) and initialize the interrupt line config register for the corresponding PCI function with the ISA IRQ as this matches existing hardware. - Add a global _PIC method for OSPM to select the desired interrupt routing configuration. - Update the _PRT methods for PCI bridges to provide both APIC and legacy PRT tables and return the appropriate table based on the configured routing configuration. Note that if the lpc device is not configured, no routing information is provided. - When the lpc device is enabled, provide ACPI PCI link devices corresponding to each PIRQ pin. - Add a VMM ioctl to adjust the trigger mode (edge vs level) for 8259A pins via the ELCR. - Mark the power management SCI as level triggered. - Don't hardcode the number of elements in Packages in the source for the DSDT. iasl(8) will fill in the actual number of elements, and this makes it simpler to generate a Package with a variable number of elements.
Reviewed by: tycho
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cc3f4b99 |
| 09-May-2014 |
Simon J. Gerraty <sjg@FreeBSD.org> |
Merge from head
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b100acf2 |
| 02-May-2014 |
Neel Natu <neel@FreeBSD.org> |
Don't allow MPtable generation if there are multiple PCI hierarchies. This is because there isn't a standard way to relay this information to the guest OS.
Add a command line option "-Y" to bhyve(8)
Don't allow MPtable generation if there are multiple PCI hierarchies. This is because there isn't a standard way to relay this information to the guest OS.
Add a command line option "-Y" to bhyve(8) to inhibit MPtable generation.
If the virtual machine is using PCI devices on buses other than 0 then it can still use ACPI tables to convey this information to the guest.
Discussed with: grehan@
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3b8f0845 |
| 28-Apr-2014 |
Simon J. Gerraty <sjg@FreeBSD.org> |
Merge head
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84e51a1b |
| 23-Apr-2014 |
Alan Somers <asomers@FreeBSD.org> |
IFC @264767
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bf775ebb |
| 25-Feb-2014 |
Peter Grehan <grehan@FreeBSD.org> |
MFC @ r259635
This brings in the "-w" option from bhyve to ignore unknown MSRs. It will make debugging Linux guests a bit easier.
Suggested by: Willem Jan Withagen (wjw at digiware nl)
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c98bb15d |
| 21-Feb-2014 |
Glen Barber <gjb@FreeBSD.org> |
MFH: tracking commit
Sponsored by: The FreeBSD Foundation
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5748b897 |
| 19-Feb-2014 |
Martin Matuska <mm@FreeBSD.org> |
Merge head up to r262222 (last merge was incomplete).
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7a902ec0 |
| 18-Feb-2014 |
Neel Natu <neel@FreeBSD.org> |
Add a check to validate that memory BARs of passthru devices are 4KB aligned.
Also, the MSI-x table offset is not required to be 4KB aligned so take this into account when computing the pages occupi
Add a check to validate that memory BARs of passthru devices are 4KB aligned.
Also, the MSI-x table offset is not required to be 4KB aligned so take this into account when computing the pages occupied by the MSI-x tables.
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a96b8b80 |
| 18-Feb-2014 |
John Baldwin <jhb@FreeBSD.org> |
Tweak the handling of PCI capabilities in emulated devices to remove the non-standard zero capability list terminator. Instead, track the start and end of the most recently added capability and use
Tweak the handling of PCI capabilities in emulated devices to remove the non-standard zero capability list terminator. Instead, track the start and end of the most recently added capability and use that to adjust the previous capability's next pointer when a capability is added and to determine the range of config registers belonging to PCI capability registers.
Reviewed by: neel
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d84882ca |
| 14-Feb-2014 |
Neel Natu <neel@FreeBSD.org> |
Allow PCI devices to be configured on all valid bus numbers from 0 to 255.
This is done by representing each bus as root PCI device in ACPI. The device implements the _BBN method to return the PCI b
Allow PCI devices to be configured on all valid bus numbers from 0 to 255.
This is done by representing each bus as root PCI device in ACPI. The device implements the _BBN method to return the PCI bus number to the guest OS.
Each PCI bus keeps track of the resources that is decodes for devices configured on the bus: i/o, mmio (32-bit) and mmio (64-bit). These windows are advertised to the guest via the _CRS object of the root device.
Bus 0 is treated specially since it consumes the I/O ports to access the PCI config space [0xcf8-0xcff]. It also decodes the legacy I/O ports that are consumed by devices on the LPC bus. For this reason the LPC bridge can be configured only on bus 0.
The bus number can be specified using the following command line option to bhyve(8): "-s <bus>:<slot>:<func>,<emul>[,<config>]"
Discussed with: grehan@ Reviewed by: jhb@
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485ac45a |
| 04-Feb-2014 |
Peter Grehan <grehan@FreeBSD.org> |
MFC @ r259205 in preparation for some SVM updates. (for real this time)
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3cbf3585 |
| 29-Jan-2014 |
John Baldwin <jhb@FreeBSD.org> |
Enhance the support for PCI legacy INTx interrupts and enable them in the virtio backends. - Add a new ioctl to export the count of pins on the I/O APIC from vmm to the hypervisor. - Use pins on th
Enhance the support for PCI legacy INTx interrupts and enable them in the virtio backends. - Add a new ioctl to export the count of pins on the I/O APIC from vmm to the hypervisor. - Use pins on the I/O APIC >= 16 for PCI interrupts leaving 0-15 for ISA interrupts. - Populate the MP Table with I/O interrupt entries for any PCI INTx interrupts. - Create a _PRT table under the PCI root bridge in ACPI to route any PCI INTx interrupts appropriately. - Track which INTx interrupts are in use per-slot so that functions that share a slot attempt to distribute their INTx interrupts across the four available pins. - Implicitly mask INTx interrupts if either MSI or MSI-X is enabled and when the INTx DIS bit is set in a function's PCI command register. Either assert or deassert the associated I/O APIC pin when the state of one of those conditions changes. - Add INTx support to the virtio backends. - Always advertise the MSI capability in the virtio backends.
Submitted by: neel (7) Reviewed by: neel MFC after: 2 weeks
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