When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to c

When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.

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IFC @253398

Merge fresh head.

sync from head

Add hooks for plugging platform-provided transfer backend.

In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
t

Add hooks for plugging platform-provided transfer backend.

In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
to start and finish transfer
- platform_will_handle - check whether transaction is
suitable for backend. If not - driver will fall back
to PIO mode.

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by: ian@

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IFC @247348.

Remove accidentally committed debug panic(9) call

Disable debug accidentally enabled by previous commit

Various timing-related fixes:

- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clo

Various timing-related fixes:

- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
implementation. By re-implementing this method hardware
drivers can control frequency controller operates when
executing initialization sequence

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Sync with HEAD.

IFC @r243836

- Get proper maximum clock frequency for SDHCI v3.0 and higher

MFC

MFC @ r241285

IFC @ r242684

Sync from head

Add new quirks:
- Data timeout is broken
- Data timeout uses SD clock
- Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0

Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for

Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface

No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.

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Merge head r233826 through r239010.

Return back double spacing.

Fix typo in comment, should be MHz here.

Submitted by: Daan Vreeken <Daan vitsch.nl>

MFC

IFC @ r234692

sys/amd64/include/cpufunc.h
sys/amd64/include/fpu.h
sys/amd64/amd64/fpu.c
sys/amd64/vmm/vmm.c

- Add API to allow vmm FPU state init/save/restore.

FP stuff discussed with: kib

IFC @231845

Sponsored by: Cisco Systems, Inc.

Add support for RICOH R5CE823 card reader, that can be found in
some Lenovo laptops.

The conroller needs a quirk to lower its frequency, and after
that it operates normally.