if_dwc: Split init code into sub function

Be clear of what we enable or init.

No functional changes intended

Merge ^/head r364082 through r364250.

MFH

Sponsored by: Rubicon Communications, LLC (netgate.com)

Fix armv{6,7} build after r364088

Sponsored by: The FreeBSD Foundation

Improve Rockchip's integration of if_dwc

- Do not rely on U-Boot for clocks configuration, enable and set frequencies
in the driver's attach method.
- Adjust MAC settings according to detected l

Improve Rockchip's integration of if_dwc

- Do not rely on U-Boot for clocks configuration, enable and set frequencies
in the driver's attach method.
- Adjust MAC settings according to detected linespeed on RK3399 and RK3328.
- Add support for RMII PHY mode on RK3328.

Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D26006

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Improve if_dwc:
- refactorize packet receive path. Make sure that we don't leak mbufs
and/or that we don't create holes in RX descriptor ring
- slightly simplify handling with TX descriptors

MF

Improve if_dwc:
- refactorize packet receive path. Make sure that we don't leak mbufs
and/or that we don't create holes in RX descriptor ring
- slightly simplify handling with TX descriptors

MFC after: 4 weeks

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Finish renaming in if_dwc.
By using DWC TRM terminology, normal descriptor format should be named
extended and alternate descriptor format should be named normal.

Should not been functional change.

Finish renaming in if_dwc.
By using DWC TRM terminology, normal descriptor format should be named
extended and alternate descriptor format should be named normal.

Should not been functional change.

MFC after: 4 weeks

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Use naming nomenclature used in DesignWare TRM.
Use naming nomenclature used in DesignWare TRM.
This driver was written by using Altera (now Intel) documentation for Arria
FPGA manual. Unfortunately

Use naming nomenclature used in DesignWare TRM.
Use naming nomenclature used in DesignWare TRM.
This driver was written by using Altera (now Intel) documentation for Arria
FPGA manual. Unfortunately this manual used very different (and in some cases
opposite naming) for registers and descriptor fields. Unfortunately,
this makes future expansion extremely hard.

Should not been functional change.

MFC after: 4 weeks

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Fix style(9). Strip write only variables.
Not a functional change.

MFC after: 1 week

Convert to if_foreach_llmaddr() KPI.

Merge ^/head r352764 through r353315.

dwc: Add more delay for chip reset

On rockchip board it seems that the value in the DTS
are not enough for reseting the chip, I don't know if
the value are really incorrect or if DELAY is not precis

dwc: Add more delay for chip reset

On rockchip board it seems that the value in the DTS
are not enough for reseting the chip, I don't know if
the value are really incorrect or if DELAY is not precise
enough or if the rockchip gpio driver have some "lag" of some
kind or not.
For now just add more delay.

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ifnet: Replace if_addr_lock rwlock with epoch + mutex

Run on LLNW canaries and tested by pho@

gallatin:
Using a 14-core, 28-HTT single socket E5-2697 v3 with a 40GbE MLX5
based ConnectX 4-LX NIC, I

ifnet: Replace if_addr_lock rwlock with epoch + mutex

Run on LLNW canaries and tested by pho@

gallatin:
Using a 14-core, 28-HTT single socket E5-2697 v3 with a 40GbE MLX5
based ConnectX 4-LX NIC, I see an almost 12% improvement in received
packet rate, and a larger improvement in bytes delivered all the way
to userspace.

When the host receiving 64 streams of netperf -H $DUT -t UDP_STREAM -- -m 1,
I see, using nstat -I mce0 1 before the patch:

InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree
4.98 0.00 4.42 0.00 4235592 33 83.80 4720653 2149771 1235 247.32
4.73 0.00 4.20 0.00 4025260 33 82.99 4724900 2139833 1204 247.32
4.72 0.00 4.20 0.00 4035252 33 82.14 4719162 2132023 1264 247.32
4.71 0.00 4.21 0.00 4073206 33 83.68 4744973 2123317 1347 247.32
4.72 0.00 4.21 0.00 4061118 33 80.82 4713615 2188091 1490 247.32
4.72 0.00 4.21 0.00 4051675 33 85.29 4727399 2109011 1205 247.32
4.73 0.00 4.21 0.00 4039056 33 84.65 4724735 2102603 1053 247.32

After the patch

InMpps OMpps InGbs OGbs err TCP Est %CPU syscalls csw irq GBfree
5.43 0.00 4.20 0.00 3313143 33 84.96 5434214 1900162 2656 245.51
5.43 0.00 4.20 0.00 3308527 33 85.24 5439695 1809382 2521 245.51
5.42 0.00 4.19 0.00 3316778 33 87.54 5416028 1805835 2256 245.51
5.42 0.00 4.19 0.00 3317673 33 90.44 5426044 1763056 2332 245.51
5.42 0.00 4.19 0.00 3314839 33 88.11 5435732 1792218 2499 245.52
5.44 0.00 4.19 0.00 3293228 33 91.84 5426301 1668597 2121 245.52

Similarly, netperf reports 230Mb/s before the patch, and 270Mb/s after the patch

Reviewed by: gallatin
Sponsored by: Limelight Networks
Differential Revision: https://reviews.freebsd.org/D15366

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EXTRES: Add OF node as argument to all <foo>_get_by_ofw_<bar>() functions.
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of

EXTRES: Add OF node as argument to all <foo>_get_by_ofw_<bar>() functions.
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.

MFC after: 3 weeks

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Fix an issue with multicast hash filters on Amlogic and Allwinner boards.

For DWC_GMAC_ALT_DESC implementations, the multicast hash table has only
64 entries. Instead of 8 registers starting at 0x50

Fix an issue with multicast hash filters on Amlogic and Allwinner boards.

For DWC_GMAC_ALT_DESC implementations, the multicast hash table has only
64 entries. Instead of 8 registers starting at 0x500, a pair of registers
at 0x08 and 0x0c are used instead.

Approved by: re (hrs)
Submitted by: Guy Yur <guyyur@gmail.com>

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Multicast filters on DWC_GMAC_ALT_DESC type implementations use a different
hash register setup. In addition, strip trailing FCS in receive path.

Reviewed by: loos
Differential Revision: https://re

Multicast filters on DWC_GMAC_ALT_DESC type implementations use a different
hash register setup. In addition, strip trailing FCS in receive path.

Reviewed by: loos
Differential Revision: https://reviews.freebsd.org/D6653

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sys/dev: use our nitems() macro when it is avaliable through param.h.

No functional change, only trivial cases are done in this sweep,
Drivers that can get further enhancements will be done independ

sys/dev: use our nitems() macro when it is avaliable through param.h.

No functional change, only trivial cases are done in this sweep,
Drivers that can get further enhancements will be done independently.

Discussed in: freebsd-current

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MFH

Sponsored by: The FreeBSD Foundation

Convert Allwinner port to extres clk/hwreset/regulator APIs.

Reviewed by: andrew, gonzo, Emmanuel Vadot <manu@bidouilliste.com>
Approved by: gonzo (mentor)
Differential Revision: https://reviews.f

Convert Allwinner port to extres clk/hwreset/regulator APIs.

Reviewed by: andrew, gonzo, Emmanuel Vadot <manu@bidouilliste.com>
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5752

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MFH

Sponsored by: The FreeBSD Foundation

Merge ^/head r296007 through r296368.

Add support for resetting the PHY via GPIO.

Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: andrew, jmcneill
Approved by: adrian (mentor)
Differential Revision: https://reviews.

Add support for resetting the PHY via GPIO.

Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: andrew, jmcneill
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5505

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Merge from head

Sponsored by: Gandi.net

Merge from head

Merge from head