Add support for the Promise command sequencer present on all modern Promise
controllers (PDC203** PDC206**).

This also adds preliminary support for the Promise SX4/SX4000 but *only*
as a "normal" Pr

Add support for the Promise command sequencer present on all modern Promise
controllers (PDC203** PDC206**).

This also adds preliminary support for the Promise SX4/SX4000 but *only*
as a "normal" Promise ATA controller (ATA RAID's are supported though
but only RAID0, RAID1 and RAID0+1).

This cuts off yet another 5-8% of the command overhead on promise controllers,
making them the fastest we have ever had support for.

Work is now continuing to add support for this in ATA RAID, to accellerate
ATA RAID quite a bit on these controllers, and especially the SX4/SX4000
series as they have quite a few tricks in there..

This commit also adds a few fixes to the SATA code needed for proper support.

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Use UMA instead of plain malloc for getting ATA request storage.
This gives +10% performance on simple tests, so definitly worth it.
A few percent more could be had by not using M_ZERO'd alloc's, but

Use UMA instead of plain malloc for getting ATA request storage.
This gives +10% performance on simple tests, so definitly worth it.
A few percent more could be had by not using M_ZERO'd alloc's, but
we then need to clear fields all over the place to be safe, and
that was deemed not worth the trouble (and it makes life dangerous).

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Overhaul of the timeout/reinit framework. This should clear up most
of the leftovers from the old version that really doesn't work anymore.

Add a reset function for host-end of the ATA channel. This

Overhaul of the timeout/reinit framework. This should clear up most
of the leftovers from the old version that really doesn't work anymore.

Add a reset function for host-end of the ATA channel. This is needed
for the SiI3112 in order to whack it back to reality if a device
locks up the SATA interface (thereby preventing that we can reset the
device). The result is that ATA now recovers from the timeouts that
happens with the SiI3112A and more or less all disks based on old
PATA electronics with a Marvell PATA->SATA converter. This includes
lots of the popular SATA dongles and the WDC Raptor disks..

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Workaround for errata on early versions of the sii3112.

Approved by: re@

Fix the DMA problem that most severely hit on the DS3112a SATA chip
in connection with Marvell based SATA->PATA dongles.

The problem was caused by a combination of things working
together to make it

Fix the DMA problem that most severely hit on the DS3112a SATA chip
in connection with Marvell based SATA->PATA dongles.

The problem was caused by a combination of things working
together to make it hard to spot...

The ATA driver has always started the ATA command, then build
the SG list for DMA and then finally started the DMA engine.
While this is according to specs, it poses a potential
problem as some controllers apparently do not allow for unlimitted
time between starting the ATA command and starting the DMA engine.

At about the same time as ATAng was committed there were lots
of other changes applied, some of which was locking in parts
that causes the busdma load functions to take significantly
longer to load the SG list.

This pushed the time spent between starting the ATA command and
starting the DMA engine over the hill for some controllers
(especially the Silicon Image DS3112a) and caused what looked
like lost interrupts.

The solution is to get all the SG list work or rather all
busdma related stuff done before we even try to start anything.

This has the nice side effect of seperating busdma out the
way it should be, so the working of the ATA machinery is not
cluttered up with busdma droppings, making the code easier
to read and understand.

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Give more correct params to busdma_*

Cleanup the dma int/alloc/free code.

Use __FBSDID().
Also some minor style cleanups.

This is a major rework of the ATA driver (ATAng)

Restructure the way ATA/ATAPI commands are processed, use a common
ata_request structure for both. This centralises the way requests
are handled so l

This is a major rework of the ATA driver (ATAng)

Restructure the way ATA/ATAPI commands are processed, use a common
ata_request structure for both. This centralises the way requests
are handled so locking is much easier to handle.

The driver is now layered much more cleanly to seperate the lowlevel
HW access so it can be tailored to specific controllers without touching
the upper layers. This is needed to support some of the newer
semi-intelligent ATA controllers showing up.

The top level drivers (disk, ATAPI devices) are more or less still
the same with just corrections to use the new interface.

Pull ATA out from under Gaint now that locking can be done in a sane way.

Add support for a the National Geode SC1100. Thanks to Soekris engineering
for sponsoring a Soekris 4801 to make this support.

Fixed alot of small bugs in the chipset code for various chips now
we are around in that corner anyways.

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Prefer new location of pci include files (which have only been in the
tree for two or more years now), except in a few places where there's
code to be compatible with older versions of FreeBSD.

Mega busdma API commit.

Add two new arguments to bus_dma_tag_create(): lockfunc and lockfuncarg.
Lockfunc allows a driver to provide a function for managing its locking
semantics while using busdma.

Mega busdma API commit.

Add two new arguments to bus_dma_tag_create(): lockfunc and lockfuncarg.
Lockfunc allows a driver to provide a function for managing its locking
semantics while using busdma. At the moment, this is used for the
asynchronous busdma_swi and callback mechanism. Two lockfunc implementations
are provided: busdma_lock_mutex() performs standard mutex operations on the
mutex that is specified from lockfuncarg. dftl_lock() is a panic
implementation and is defaulted to when NULL, NULL are passed to
bus_dma_tag_create(). The only time that NULL, NULL should ever be used is
when the driver ensures that bus_dmamap_load() will not be deferred.
Drivers that do not provide their own locking can pass
busdma_lock_mutex,&Giant args in order to preserve the former behaviour.

sparc64 and powerpc do not provide real busdma_swi functions, so this is
largely a noop on those platforms. The busdma_swi on is64 is not properly
locked yet, so warnings will be emitted on this platform when busdma
callback deferrals happen.

If anyone gets panics or warnings from dflt_lock() being called, please
let me know right away.

Reviewed by: tmm, gibbs

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Third round of updates to the ATA driver.

More DMA cleanups, including fix for breakage on older Promise controllers.

Add more ways of getting to the ATA registers.

Second round of updates to the ATA driver.

Clean up the DMA interface too much unneeded stuff crept in with
the busdma code back when.

Modify the ATA_IN* / ATA_OUT* macros so that resource and offs

Second round of updates to the ATA driver.

Clean up the DMA interface too much unneeded stuff crept in with
the busdma code back when.

Modify the ATA_IN* / ATA_OUT* macros so that resource and offset
are gotten from a table. That allows for new chipsets that doesn't
nessesarily have things ordered the good old way. This also removes
the need for the wierd PC98 resource functions.

Tested on: i386, PC98, Alpha, Sparc64

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First round off updates/fixes to the ATA driver.

This moves all chipset specific code to a new file 'ata-chipset.c'.
Extensive use of tables and pointers to avoid having the same switch
on chipset t

First round off updates/fixes to the ATA driver.

This moves all chipset specific code to a new file 'ata-chipset.c'.
Extensive use of tables and pointers to avoid having the same switch
on chipset type in several places, and to allow substituting various
functions for different HW arch needs.
Added PIO mode setup and all DMA modes.
Support for all known SiS chipsets. Thanks to Christoph Kukulies for
sponsoring a nice ASUS P4S8X SiS648 based board for this work!

Tested on: i386, PC98, alpha and sparc64

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Small change to the previous commit, zero out the 48BIT flag in ata_command
instead of in dmadone.

Add support for the ServerWorks CSB6.
The support for the 3'rd channel is only experimental.

Fix the 48bit access support for the older Promise 66/100 controllers, the
first attempt was wrong and could cause r/w timeouts.

Add yet another Promise PCI id.

Fix typo

PR: 45375

Add support for the nVidia nForce2 ATA part.

Fix support for the nForce1 as well, registers are offset 0x10
against the AMD/VIA parts.

Add code that works around the problem that the older Promise
controllers (ultra/fasttrak-66/100) fails on 48bit accesses.

Add support for the PC98 platform to the ATA driver.
This mostly consists of functionality to serialize accesses to
the two ATA channels (which can also be used to "fix" certain
PCI based controllers

Add support for the PC98 platform to the ATA driver.
This mostly consists of functionality to serialize accesses to
the two ATA channels (which can also be used to "fix" certain
PCI based controllers).
Add support for Acard controllers.
Enable the ATA driver in PC98 GENERIC, and add device hints.
Update man page with latest support.

The PC98 core team has kindly provided me with a PC98
machine that made this all possible, thanks to all that
contributed to that effort, without that this would
probably newer have been possible..

Approved by: re@

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Add yet another Promise PCI id.

Remove unused #includes: <sys/disk.h> <sys/devicestat.h> and <sys/sysctl.h>

Sponsored by: DARPA & NAI Labs.
Approved by: sos

Add support for the VIA 8235.

Submitted by: Jason Dambrosio <jason@wiz.cx>

remove #includes of <sys/bio.h> where not needed.