History log of /freebsd/sys/arm64/include/armreg.h (Results 76 – 100 of 193)
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# 27340501 21-Sep-2021 Olivier Houchard <cognet@FreeBSD.org>

arm64: Handle 32bits breakpoint exception.

A different exception is raised when we hit a 32bits breakpoint, rather than
a 64bits one, so handle those as well when COMPAT_FREEBSD32 is defined.
This s

arm64: Handle 32bits breakpoint exception.

A different exception is raised when we hit a 32bits breakpoint, rather than
a 64bits one, so handle those as well when COMPAT_FREEBSD32 is defined.
This should fix SIGBUS at least when using breakpoints with thumb2 code.

PR: 256468
MFC After: 1 week

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# 17b6ee96 09-Aug-2021 Andrew Turner <andrew@FreeBSD.org>

Enable arm64 SError exceptions in the kernel

These are needed to signal to the kernel when a Reliability,
Availability, and Serviceability (RAS) exception has triggered.

Reviewed by: mhorne
Sponsor

Enable arm64 SError exceptions in the kernel

These are needed to signal to the kernel when a Reliability,
Availability, and Serviceability (RAS) exception has triggered.

Reviewed by: mhorne
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31477

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# 337eb2ab 03-Aug-2021 Andrew Turner <andrew@FreeBSD.org>

Add macros for the arm64 daifset/daifclr flags

Sponsored by: The FreeBSD Foundation


# 10f6680f 28-Jul-2021 Andrew Turner <andrew@FreeBSD.org>

Add macros for arm64 special reg op and CR values

Use these to simplify the definition of the user_regs array.

Reviewed by: imp, markj
Sponsored by: The FreeBSD Foundation
Differential Revision: ht

Add macros for arm64 special reg op and CR values

Use these to simplify the definition of the user_regs array.

Reviewed by: imp, markj
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31333

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# bbe80bff 25-Jul-2021 Peter Grehan <grehan@FreeBSD.org>

arm64: HWCAP/HWCAP2 aux args support for 32-bit ARM binaries.

This fixes build/run of golang under COMPAT32 emulation.

PR: 256897
Reviewed by: andrew, mmel, manu, jhb, cognet, Robert Clausecker
Tes

arm64: HWCAP/HWCAP2 aux args support for 32-bit ARM binaries.

This fixes build/run of golang under COMPAT32 emulation.

PR: 256897
Reviewed by: andrew, mmel, manu, jhb, cognet, Robert Clausecker
Tested by: brd, andrew, Robert Clausecker
MFC after: 3 weeks
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D31175

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# 5484e6d9 08-Jul-2021 Andrew Turner <andrew@FreeBSD.org>

Update the SCTLR_EL1 register definitions

They are valid as of the ARMv8.7 XML.

While here remove SCTLR_RES0 as it's unused and depends on which CPU
the kernel is running on and switch to shifted v

Update the SCTLR_EL1 register definitions

They are valid as of the ARMv8.7 XML.

While here remove SCTLR_RES0 as it's unused and depends on which CPU
the kernel is running on and switch to shifted values as they are
easier to compare with the documentation.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31120

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# c0edde30 08-Jul-2021 Andrew Turner <andrew@FreeBSD.org>

Fix the name of the arm64 SCTLR_E0E register

The character between the E's was the letter O, however in the Arm
Documentation and XML the character is the number 0 (zero).

Sponsored by: The FreeBSD

Fix the name of the arm64 SCTLR_E0E register

The character between the E's was the letter O, however in the Arm
Documentation and XML the character is the number 0 (zero).

Sponsored by: The FreeBSD Foundation

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# a7b05eb1 01-Jul-2021 Andrew Turner <andrew@FreeBSD.org>

Sync the arm64 special registers with the Armv8.5 XML

Add the missing macros and decode all the fields as described in the
Arm Architecture System Registers XML corresponding to Armv8.5.

Sponsored

Sync the arm64 special registers with the Armv8.5 XML

Add the missing macros and decode all the fields as described in the
Arm Architecture System Registers XML corresponding to Armv8.5.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D30983

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Revision tags: release/13.0.0
# f2583be1 28-Jan-2021 Mitchell Horne <mhorne@FreeBSD.org>

arm64: extend struct db_reg to include watchpoint registers

The motivation is to provide access to these registers from userspace
via ptrace(2) requests PT_GETDBREGS and PT_SETDBREGS.

This change b

arm64: extend struct db_reg to include watchpoint registers

The motivation is to provide access to these registers from userspace
via ptrace(2) requests PT_GETDBREGS and PT_SETDBREGS.

This change breaks the ABI of these particular requests, but is
justified by the fact that the intended consumers (debuggers) have not
been taught to use them yet. Making this change now enables active
upstream work on lldb to begin using this interface, and take advantage
of the hardware debugging registers available on the platform.

PR: 252860
Reported by: Michał Górny (mgorny@gentoo.org)
Reviewed by: andrew, markj (earlier version)
Tested by: Michał Górny (mgorny@gentoo.org)
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D28415

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# bd012c71 05-Feb-2021 Mitchell Horne <mhorne@FreeBSD.org>

arm64: handle watchpoint exceptions from EL0

This is a prerequisite to allowing the use of hardware watchpoints for
userspace debuggers.

This is also a slight departure from the x86 behaviour, sinc

arm64: handle watchpoint exceptions from EL0

This is a prerequisite to allowing the use of hardware watchpoints for
userspace debuggers.

This is also a slight departure from the x86 behaviour, since `si_addr`
returns the data address that triggered the watchpoint, not the
address of the instruction that was executed. Otherwise, there is no
straightforward way for the application to determine which watchpoint
was triggered. Make a note of this in the siginfo(3) man page.

Reviewed by: jhb, markj (earlier version)
Tested by: Michał Górny (mgorny@gentoo.org)
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D28561

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# de2b9422 09-Feb-2021 Mitchell Horne <mhorne@FreeBSD.org>

arm64: validate breakpoint registers

In particular, we want to disallow setting breakpoints on kernel
addresses from userspace. The control register fields are validated or
ignored as appropriate.

arm64: validate breakpoint registers

In particular, we want to disallow setting breakpoints on kernel
addresses from userspace. The control register fields are validated or
ignored as appropriate.

Reviewed by: markj
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D28560

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# 13ec5a6d 05-Feb-2021 Andrew Turner <andrew@FreeBSD.org>

Add support for arm64 nGnRE device memory

On arm64 we can select how strongly we order device memory. Currently
we use the strongest type of non-Gathering, non-Reordering, no Early
write acknowledge

Add support for arm64 nGnRE device memory

On arm64 we can select how strongly we order device memory. Currently
we use the strongest type of non-Gathering, non-Reordering, no Early
write acknowledgement. This is equivalent to VM_MEMATTR_SO in the 32-bit
arm code.

Create a new memory type to remove the no Early write acknowledgement
option to create a memory attribute that is equivalent to the arm
VM_MEMATTR_DEVICE.

Keep the the old nGnRnE memory as what we provide for VM_MEMATTR_DEVICE
until we can test nGnRE on more hardware. A method for dynamically
switching back may be needed as at least one vendor is known to have
broken nGnRE memory.

Sponsored by: Innovate UK

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# f64329bc 15-Jan-2021 Andrew Turner <andrew@FreeBSD.org>

Extract the logic from pmap_kextract

This allows us to use it when we only need to check if the virtual address
is valid. For example when checking if an address in the DMAP region is
mapped.

Revie

Extract the logic from pmap_kextract

This allows us to use it when we only need to check if the virtual address
is valid. For example when checking if an address in the DMAP region is
mapped.

Reviewed by: kib, markj
Sponsored by: Innovate UK
Differential Revision: https://reviews.freebsd.org/D27621

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Revision tags: release/12.2.0
# 0387f2aa 16-Oct-2020 Mitchell Horne <mhorne@FreeBSD.org>

Update the ID_AA64MMFR2_EL1 register definitions

This brings these definitions in sync with the ARMv8.6 version of the
architecture reference manual.

Sponsored by: The FreeBSD Foundation
Differenti

Update the ID_AA64MMFR2_EL1 register definitions

This brings these definitions in sync with the ARMv8.6 version of the
architecture reference manual.

Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D26706

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# 50cedfed 01-Sep-2020 Mateusz Guzik <mjg@FreeBSD.org>

arm64: clean up empty lines in .c and .h files


# e2515283 27-Aug-2020 Glen Barber <gjb@FreeBSD.org>

MFH

Sponsored by: Rubicon Communications, LLC (netgate.com)


# 518eb03e 16-Aug-2020 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r364251 through r364263.


# 61949736 15-Aug-2020 Mitchell Horne <mhorne@FreeBSD.org>

arm64: update instruction set attribute register definitions

This adds definitions for the latest additions to the AA64ISAR[01] ID
registers. This brings these registers in sync with ARMv8.6 initial

arm64: update instruction set attribute register definitions

This adds definitions for the latest additions to the AA64ISAR[01] ID
registers. This brings these registers in sync with ARMv8.6 initial spec
release.

An future change will parse many of these fields for HWCAP features.

Reviewed by: andrew, manu, markj (all previous versions)
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D26029

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# de6fc2e3 15-Aug-2020 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r364082 through r364250.


# 440cec3f 12-Aug-2020 Glen Barber <gjb@FreeBSD.org>

MFH

Sponsored by: Rubicon Communications, LLC (netgate.com)


# da11e1f9 12-Aug-2020 Andrew Turner <andrew@FreeBSD.org>

Add support for Cortex-A76/Neoverse-N1 to hwpmc

This adds support for the Cortex-A76 and Neoverse-N1 PMU counters to pmc.

While here add more PMCR_IDCODE values and check the implementers code is
c

Add support for Cortex-A76/Neoverse-N1 to hwpmc

This adds support for the Cortex-A76 and Neoverse-N1 PMU counters to pmc.

While here add more PMCR_IDCODE values and check the implementers code is
correct before setting the PMU type.

Reviewed by: bz, emaste (looks reasonable to me)
Sponsored by: Innovate UK
Differential Revision: https://reviews.freebsd.org/D25959

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# e46cf959 23-Jun-2020 Ed Maste <emaste@FreeBSD.org>

arm64 armreg.h: fix TCR_TBI1 definition

Submitted by: Greg V <greg@unrelenting.technology>
Differential Revision: https://reviews.freebsd.org/D25411


# f3e9395d 17-Jun-2020 Andrew Turner <andrew@FreeBSD.org>

Add all the TCR_EL1 fields

These will be used when adding support for new Armv8 extensions.

Sponsored by: Innovate UK


Revision tags: release/11.4.0
# f7ed37c5 06-Mar-2020 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r358678 through r358711.


# 3a1c1a30 06-Mar-2020 Andrew Turner <andrew@FreeBSD.org>

Add more are64 special register fields

Obtained from: https://github.com/FreeBSD-UPB/freebsd


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