History log of /freebsd/sys/arm64/include/armreg.h (Results 176 – 193 of 193)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
# 11d38a57 28-Oct-2015 Baptiste Daroussin <bapt@FreeBSD.org>

Merge from head

Sponsored by: Gandi.net


# 80c4b9e5 19-Oct-2015 Andrew Turner <andrew@FreeBSD.org>

Use 4 levels of page tables when enabling the MMU. This will allow us to
boot on an SoC that places physical memory at an address past where three
levels of page tables can access in an identity mapp

Use 4 levels of page tables when enabling the MMU. This will allow us to
boot on an SoC that places physical memory at an address past where three
levels of page tables can access in an identity mapping.

Submitted by: Wojciech Macek <wma@semihalf.com>,
Patrick Wildt <patrick@bitrig.org>
Differential Revision: https://reviews.freebsd.org/D3885 (partial)
Differential Revision: https://reviews.freebsd.org/D3744

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# f94594b3 12-Sep-2015 Baptiste Daroussin <bapt@FreeBSD.org>

Finish merging from head, messed up in previous attempt


# b5ff185e 12-Sep-2015 Baptiste Daroussin <bapt@FreeBSD.org>

Merge from head


# 23a32822 25-Aug-2015 Baptiste Daroussin <bapt@FreeBSD.org>

Merge from HEAD


# ab875b71 14-Aug-2015 Navdeep Parhar <np@FreeBSD.org>

Catch up with head, primarily for the 1.14.4.0 firmware.


# f98ee844 12-Aug-2015 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r286422 through r286684.


# b1bacc1c 12-Aug-2015 Andrew Turner <andrew@FreeBSD.org>

Add the CNTHCTL_EL2 register bits missed in r286674


Revision tags: release/10.2.0
# 8d0f1085 22-Jul-2015 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r285341 through r285792.


# 1038d102 16-Jul-2015 Zbigniew Bodek <zbb@FreeBSD.org>

Set-up proper TCR values for memory related to Translation Table Walking

This commit adds proper cache and shareability attributes to
the TCR register.
Set memory attributes to Normal, outer and inn

Set-up proper TCR values for memory related to Translation Table Walking

This commit adds proper cache and shareability attributes to
the TCR register.
Set memory attributes to Normal, outer and inner cacheable WBWA.
Set shareability to inner and outer shareable when SMP is enabled.

Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3093

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# 416ba5c7 22-Jun-2015 Navdeep Parhar <np@FreeBSD.org>

Catch up with HEAD (r280229-r284686).


# 37a48d40 28-May-2015 Glen Barber <gjb@FreeBSD.org>

MFH: r282615-r283655

Sponsored by: The FreeBSD Foundation


# 98e0ffae 27-May-2015 Simon J. Gerraty <sjg@FreeBSD.org>

Merge sync of head


# bc88bb2b 19-May-2015 Ruslan Bukin <br@FreeBSD.org>

Add Performance Monitoring Counters support for AArch64.
Family-common and CPU-specific counters implemented.

Supported CPUs: ARM Cortex A53/57/72.

Reviewed by: andrew, bz, emaste, gnn, jhb
Sponsor

Add Performance Monitoring Counters support for AArch64.
Family-common and CPU-specific counters implemented.

Supported CPUs: ARM Cortex A53/57/72.

Reviewed by: andrew, bz, emaste, gnn, jhb
Sponsored by: ARM Limited
Differential Revision: https://reviews.freebsd.org/D2555

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# 42cb216a 13-May-2015 Zbigniew Bodek <zbb@FreeBSD.org>

Add support for ARM GICv3 interrupt controller used in some ARM64 chips

GICv3 allows to distribute interrupts to more than 8 cores served by
the previous GIC revisions. GICv3 introduces additional l

Add support for ARM GICv3 interrupt controller used in some ARM64 chips

GICv3 allows to distribute interrupts to more than 8 cores served by
the previous GIC revisions. GICv3 introduces additional logic in form
of Re-Distributors associated with particular CPUs to determine
the highest priority interrupts and manage PPIs and LPIs
(Locality-specific Peripheral Interrupts). Interrupts routing is
based on CPUs' affinity numbers. CPU interface was changed to be
accessible via CPU System Registers and this is the preferred
(and supported) method in this driver.

Obtained from: Semihalf
Reviewed by: andrew, emaste, ian, imp
Sponsored by: The FreeBSD Foundation

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# 7757a1b4 03-May-2015 Baptiste Daroussin <bapt@FreeBSD.org>

Merge from head


# 7263c8c0 22-Apr-2015 Glen Barber <gjb@FreeBSD.org>

MFH: r280643-r281852

Sponsored by: The FreeBSD Foundation


# e5acd89c 13-Apr-2015 Andrew Turner <andrew@FreeBSD.org>

Bring in the start of the arm64 kernel.

This is only the minimum set of files needed to boot in qemu. As such it is
missing a few things.

The bus_dma code is currently only stub functions with a fu

Bring in the start of the arm64 kernel.

This is only the minimum set of files needed to boot in qemu. As such it is
missing a few things.

The bus_dma code is currently only stub functions with a full implementation
from the development tree to follow.

The gic driver has been copied as the interrupt framework is different. It
is expected the two drivers will be merged by the arm intrng project,
however this will need to be imported into the tree and support for arm64
would need to be added.

This includes code developed by myself, SemiHalf, Ed Maste, and Robin
Randhawa from ARM. This has been funded by the FreeBSD Foundation, with
early development by myself in my spare time with assistance from Robin.

Differential Revision: https://reviews.freebsd.org/D2199
Reviewed by: emaste, imp
Relnotes: yes
Sponsored by: The FreeBSD Foundation

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