History log of /freebsd/sys/arm64/include/armreg.h (Results 126 – 150 of 193)
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# a9725b63 01-Nov-2018 Andrew Turner <andrew@FreeBSD.org>

Add the ARMv8.3 SCTLR_EL1 fields.

While here tag which architecture release fields were added and remove a
field that only existed in very early releases of the ARMv8 spec.

Sponsored by: DARPA, AFRL


# c6879c6c 23-Oct-2018 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r339015 through r339669.


# 5bb9cd61 22-Oct-2018 Andrew Turner <andrew@FreeBSD.org>

Fix the ID_AA64ISAR0_EL1 dot product field shift.

It's 44 in the documentation, use this correct value.

MFC after: 3 days


# 71374d5d 22-Oct-2018 Andrew Turner <andrew@FreeBSD.org>

Correctly set the DAIF bits in new threads

We should only unmask interrupts when creating a new thread and leave the
other exceptions in teh same state as before creating the thread.

Reported by: j

Correctly set the DAIF bits in new threads

We should only unmask interrupts when creating a new thread and leave the
other exceptions in teh same state as before creating the thread.

Reported by: jhibbits
Reviewed by: jhibbits
MFC after: 1 month
Sponsored by: https://reviews.freebsd.org/D17497

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Revision tags: release/11.2.0
# 2b6a8dd5 26-Nov-2017 Ed Schouten <ed@FreeBSD.org>

Add a Saved Process Status Register bit for AArch32 execution mode.

The documentation on the Saved Process Status Register (SPSR) is a bit
weird; the M[4] bit is documented separately from M[3:0]. T

Add a Saved Process Status Register bit for AArch32 execution mode.

The documentation on the Saved Process Status Register (SPSR) is a bit
weird; the M[4] bit is documented separately from M[3:0]. The M[4] bit
can be toggled to switch to 32-bit execution mode. This functionality is
orthogonal to M[3:0].

Change the definition of PSR_M_MASK to no longer include M[4]. Add a new
definition, PSR_AARCH32 that can be used to toggle 32-bit independently.
This bit will be used by the cloudabi32 code to force execution of
userspace code in 32-bit mode.

Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D13148

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# 7af24ff7 26-Nov-2017 Ed Schouten <ed@FreeBSD.org>

Make 32-bit system calls end up in svc_handler().

The nice thing about ARM64 is that it's pretty elegant to install
separate trap/exception handlers for 32-bit and 64-bit processes. That
said, for a

Make 32-bit system calls end up in svc_handler().

The nice thing about ARM64 is that it's pretty elegant to install
separate trap/exception handlers for 32-bit and 64-bit processes. That
said, for all other architectures (e.g., i386 on amd64) we always let
32-bit counterparts go through the regular system call codepath. Let's
do the same on ARM64.

Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D13146

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# 8a53e134 24-Nov-2017 Hans Petter Selasky <hselasky@FreeBSD.org>

Merge ^/head r326132 through r326161.


# 521018d3 23-Nov-2017 Andrew Turner <andrew@FreeBSD.org>

Ensure we check the program state set in the trap frame on arm and arm64.
This value may be set by userspace so we need to check it before using it.
If this is not done correctly on exception return

Ensure we check the program state set in the trap frame on arm and arm64.
This value may be set by userspace so we need to check it before using it.
If this is not done correctly on exception return the kernel may continue
in kernel mode with all registers set to a userspace controlled value. Fix
this by moving the check into set_mcontext, and also add the missing
sanitisation from the arm64 set_regs.

Discussed with: security-officer@
MFC after: 3 days
Sponsored by: DARPA, AFRL

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# c2c014f2 07-Nov-2017 Hans Petter Selasky <hselasky@FreeBSD.org>

Merge ^/head r323559 through r325504.


Revision tags: release/10.4.0
# 8fcbcc2d 16-Sep-2017 Enji Cooper <ngie@FreeBSD.org>

MFhead@r323635


# ca289945 15-Sep-2017 Andrew Turner <andrew@FreeBSD.org>

Add the ARMv8.3 ID register fields. These were found in the A-Profile
exploration tools documentation:
https://developer.arm.com/products/architecture/a-profile/exploration-tools

Sponsored by: DARPA

Add the ARMv8.3 ID register fields. These were found in the A-Profile
exploration tools documentation:
https://developer.arm.com/products/architecture/a-profile/exploration-tools

Sponsored by: DARPA, AFRL

show more ...


# b754c279 13-Sep-2017 Navdeep Parhar <np@FreeBSD.org>

MFH @ r323558.


# 5be4ad9e 09-Sep-2017 Enji Cooper <ngie@FreeBSD.org>

MFhead@r323343


# f9fc9faa 07-Sep-2017 Andrew Turner <andrew@FreeBSD.org>

Fix the SVE ID field shift.

Sponsored by: DARPA, AFRL


# 1a2e5c00 07-Sep-2017 Andrew Turner <andrew@FreeBSD.org>

Fix the value of ID_AA64ISAR1_DPB_SHIFT, the field is bits 3:0.

Sponsored by: DARPA, AFRL


# f45dc694 07-Sep-2017 Andrew Turner <andrew@FreeBSD.org>

Add the ARMv8.2 ID register additions and use them to decode the register
values. As not all assemblers understand the new ID_AA64MMFR2_EL1 register
add a macro to access it. This seems to be safe fo

Add the ARMv8.2 ID register additions and use them to decode the register
values. As not all assemblers understand the new ID_AA64MMFR2_EL1 register
add a macro to access it. This seems to be safe for older CPUs to read this
new register, with them returning zero.

Sponsored by: DARPA, AFRL

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Revision tags: release/11.1.0
# 209be205 16-May-2017 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r317971 through r318379.


# 2438ef76 13-May-2017 Andrew Turner <andrew@FreeBSD.org>

Allocate a cacheline when reading or writing to write through memory. The
hardware will still write to memory, however following reads will be from
the cache.

MFC after: 1 week
Sponsored by: DARPA,

Allocate a cacheline when reading or writing to write through memory. The
hardware will still write to memory, however following reads will be from
the cache.

MFC after: 1 week
Sponsored by: DARPA, AFRL

show more ...


# d6a0af23 13-Apr-2017 Andrew Turner <andrew@FreeBSD.org>

In ARMv8.1 ARM has added a process state bit to disable access to userspace
from the kernel. Make use of this to restrict accessing userspace to just
the functions that explicitly handle crossing the

In ARMv8.1 ARM has added a process state bit to disable access to userspace
from the kernel. Make use of this to restrict accessing userspace to just
the functions that explicitly handle crossing the user kernel boundary.

Reported by: kib
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D10371

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# aec085f4 13-Apr-2017 Andrew Turner <andrew@FreeBSD.org>

Add SCTLR bits added in ARMv8.1 and ARMv8.2 and start to use them in the
early boot code.

Sponsored by: DARPA, AFRL


# 33e643f7 28-Nov-2016 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r309213 through r309262.


# a70475ca 28-Nov-2016 Andrew Turner <andrew@FreeBSD.org>

Fix ISS_DATA_DFSC_MASK, it should include all bits in the field.


# dc836c65 25-Nov-2016 Andrew Turner <andrew@FreeBSD.org>

Fix the TLB conflict abort value. This should be a no-op as we don't use
this value in the code.


# a0e610c4 16-Oct-2016 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r306906 through r307382.


# 401d3029 15-Oct-2016 Andrew Turner <andrew@FreeBSD.org>

Create macros for the MAIR memory attributes. While here add an uncached
memory type, however the VM code still needs to be taught about this.

MFC after: 1 week
Sponsored by: ABT Systems Ltd


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