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db724d90 |
| 06-Mar-2020 |
Andrew Turner <andrew@FreeBSD.org> |
Update the hypervisor registers
- Add more registers needed by bhyve [1] - Move EL2 registers from armreg.h to hypervisor.h - Add the register name to hypervisor.h
Obtained from: https://github.
Update the hypervisor registers
- Add more registers needed by bhyve [1] - Move EL2 registers from armreg.h to hypervisor.h - Add the register name to hypervisor.h
Obtained from: https://github.com/FreeBSD-UPB/freebsd [1]
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e43d33d2 |
| 05-Mar-2020 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r358466 through r358677.
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2923027c |
| 03-Mar-2020 |
Andrew Turner <andrew@FreeBSD.org> |
Fix the spelling of the VIPT cache type field
Sponsored by: Innovate UK
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75dfc66c |
| 27-Feb-2020 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r358269 through r358399.
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c32e28d5 |
| 26-Feb-2020 |
Andrew Turner <andrew@FreeBSD.org> |
Add more arm64 CTR_EL0 register fields
While here make the _SIZE macros return the size in bytes, not the log2 of the size
Sponsored by: Innovate UK
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051669e8 |
| 25-Jan-2020 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r356931 through r357118.
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b6cf94ae |
| 23-Jan-2020 |
Mark Johnston <markj@FreeBSD.org> |
Print missing ID_AA64PFR{0,1}_EL1 register fields.
MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D23213
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b0a0152a |
| 30-Dec-2019 |
Alan Cox <alc@FreeBSD.org> |
Determine whether the MMU hardware is capable of updating a page table entry's access flag and dirty state, and enable this feature when it's available.
Ensure that we don't overlook a dirty state u
Determine whether the MMU hardware is capable of updating a page table entry's access flag and dirty state, and enable this feature when it's available.
Ensure that we don't overlook a dirty state update that is concurrent with a call to pmap_enter(). (Previously, all dirty state updates would have occurred with the containing pmap's lock held, so a page table entry's dirty state could not have changed while pmap_enter() held that same lock.)
Reviewed by: andrew, markj MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D22907
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65565c97 |
| 12-Dec-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Add comments and macros to the tcr_el1 setting code to help understand it.
This code is non-obvious when reading for the first time. To help with understanding of it add comments explaining what it'
Add comments and macros to the tcr_el1 setting code to help understand it.
This code is non-obvious when reading for the first time. To help with understanding of it add comments explaining what it's doing.
While here use macros from armreg.h rather than magic numbers.
Sponsored by: DARPA, AFRL
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50e3ab6b |
| 03-Nov-2019 |
Alan Cox <alc@FreeBSD.org> |
Utilize ASIDs to reduce both the direct and indirect costs of context switching. The indirect costs being unnecessary TLB misses that are incurred when ASIDs are not used. In fact, currently, when
Utilize ASIDs to reduce both the direct and indirect costs of context switching. The indirect costs being unnecessary TLB misses that are incurred when ASIDs are not used. In fact, currently, when we perform a context switch on one processor, we issue a broadcast TLB invalidation that flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page table was being initialized to the root of the kernel-space page table rather than a user-space page table. However, the root of the page table that was being cached in process 0's md_l0addr field correctly pointed to a user-space page table. As long as ASIDs weren't being used, this was harmless, except that it led to some unnecessary page table switches in pmap_switch(). Specifically, other kernel processes besides process 0 would have their md_l0addr field set to the root of the kernel-space page table, and so pmap_switch() would actually change page tables when switching between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines. (I would like to thank andrew@ for providing the code to detect the affected machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG, can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D21922
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05f39d1a |
| 03-Nov-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Add support for setting hardware breakpoints from ptrace on arm64.
Implement get/fill_dbregs on arm64. This is used by ptrace with the PT_GETDBREGS and PT_SETDBREGS requests. It allows userspace to
Add support for setting hardware breakpoints from ptrace on arm64.
Implement get/fill_dbregs on arm64. This is used by ptrace with the PT_GETDBREGS and PT_SETDBREGS requests. It allows userspace to set hardware breakpoints.
The struct dbreg is based on Linux to ease adding hardware breakpoint support to debuggers.
Reviewed by: jhb Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D22195
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Revision tags: release/12.1.0 |
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739e4482 |
| 30-Oct-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Allow exceptions to be masked when in userspace
We may want to mask exceptions when in userspace. This was previously impossible as threads are created with all exceptions unmasked and signals expec
Allow exceptions to be masked when in userspace
We may want to mask exceptions when in userspace. This was previously impossible as threads are created with all exceptions unmasked and signals expected userspace to mask any. Fix these by copying the mask state on thread creation and allow exceptions to be masked on signal return, as long as they don't change.
Sponsored by: DARPA, AFRL
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e68508e1 |
| 30-Oct-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Allow the userspace ID register fields to be read from the kernel
To allow consistent values to be used in both the kernel and userspace create a function for these to be read from the kernel. They
Allow the userspace ID register fields to be read from the kernel
To allow consistent values to be used in both the kernel and userspace create a function for these to be read from the kernel. They use a newly created macro with the name of the ID register to read. For now there is redundant information in the user_regs array as it still holds the CRm and Op2 values, however this will be fixed in a later change.
This will be used by ptrace to allow hardware breakpoints in userspace.
Sponsored by: DARPA, AFRL
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cb5343c2 |
| 30-Oct-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Move the MRS instruction decode macros to armreg.h
These instructions are used to access the registers described in armreg.h, and will be used in a future change to create a per-register identificat
Move the MRS instruction decode macros to armreg.h
These instructions are used to access the registers described in armreg.h, and will be used in a future change to create a per-register identification macro.
Sponsored by: DARPA, AFRL
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44e446a1 |
| 30-Oct-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Rename the macros to extract a single arm64 ID field.
Because of the previous naming scheme the old ID_AA64PFR0_EL1 macro collided with a potential macro for the register of the same name. To fix th
Rename the macros to extract a single arm64 ID field.
Because of the previous naming scheme the old ID_AA64PFR0_EL1 macro collided with a potential macro for the register of the same name. To fix this collision rename these macros.
Sponsored by: DARPA, AFRL
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6c1633e1 |
| 25-Oct-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Remove the arm4 ID register masks, they are not needed after r353641.
Sponsored by: DARPA, AFRL
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a63915c2 |
| 28-Jul-2019 |
Alan Somers <asomers@FreeBSD.org> |
MFHead @r350386
Sponsored by: The FreeBSD Foundation
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ac4e5827 |
| 23-Jul-2019 |
Andrew Turner <andrew@FreeBSD.org> |
As with r350241 use the new UL macro on the main register mask.
MFC after: 1 week Sponsored by: DARPA, AFRL
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f31c5955 |
| 23-Jul-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Ensure the arm64 ID register fields are 64 bit types.
Previously only some of the ID register fields were 64 bit. To allow for a script to generate these mark them all 64 bit. To allow for their use
Ensure the arm64 ID register fields are 64 bit types.
Previously only some of the ID register fields were 64 bit. To allow for a script to generate these mark them all 64 bit. To allow for their use in assembly we need to use the UINT64_C macro via a new UL macro to stop the lines from being too long.
MFC after: 1 week Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20977
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f1fbf9c3 |
| 18-Jul-2019 |
Andrew Turner <andrew@FreeBSD.org> |
Rename arm64 macros in preperation for a script to generate them.
I have a script to generate most of the ID_AA64* macros from the Arm XML source [1]. In preperation for using this we need to clean
Rename arm64 macros in preperation for a script to generate them.
I have a script to generate most of the ID_AA64* macros from the Arm XML source [1]. In preperation for using this we need to clean up the macros to be in line with what the script will generate. This is the first step, rename the macros to follow the names in said XML.
[1] https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
MFC after: 1 week Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20976
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a9da8477 |
| 11-Jul-2019 |
Mark Johnston <markj@FreeBSD.org> |
Fix some ISS bit definitions for data aborts.
MFC after: 1 week Sponsored by: The FreeBSD Foundation
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Revision tags: release/11.3.0 |
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e532a999 |
| 20-Jun-2019 |
Alan Somers <asomers@FreeBSD.org> |
MFHead @349234
Sponsored by: The FreeBSD Foundation
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c749d685 |
| 15-Jun-2019 |
Julian Elischer <julian@FreeBSD.org> |
Lightly hide the 'var' inside the macros to read the arm special registers. I just happenned to have 3rd party code using 'var' as the output variable which drew my attention to this. variables defin
Lightly hide the 'var' inside the macros to read the arm special registers. I just happenned to have 3rd party code using 'var' as the output variable which drew my attention to this. variables defined inside macros should be prefixed to avoid getting shadowed varable wanrings from clang.
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8c9c3144 |
| 13-Jan-2019 |
Olivier Houchard <cognet@FreeBSD.org> |
Impleent COMPAT_FREEBSD32 for arm64. This is based on early work by andrew@.
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Revision tags: release/12.0.0 |
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2a22df74 |
| 04-Nov-2018 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r339813 through r340125.
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