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2498f259 |
| 20-Mar-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name in comment.
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ab5916a5 |
| 12-Mar-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add another CPUID for AMD CPUs and fix style(9) while I am here.
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Revision tags: release/6.2.0_cvs, release/6.2.0 |
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5efc6c44 |
| 09-Jan-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.
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0758eaa2 |
| 13-Jul-2006 |
Jung-uk Kim <jkim@FreeBSD.org> |
Sync specialreg.h changes between amd64 and i386 with few fixes.
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444576c0 |
| 12-Jul-2006 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.
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Revision tags: release/5.5.0_cvs, release/5.5.0, release/6.1.0_cvs, release/6.1.0 |
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2b8a339c |
| 02-May-2006 |
John Baldwin <jhb@FreeBSD.org> |
Add various constants for the PAT MSR and the PAT PTE and PDE flags. Initialize the PAT MSR during boot to map PAT type 2 to Write-Combining (WC) instead of Uncached (UC-).
MFC after: 1 month
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Revision tags: release/6.0.0_cvs, release/6.0.0 |
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25736eb6 |
| 15-Oct-2005 |
Jung-uk Kim <jkim@FreeBSD.org> |
Correct few MSR addresses.
PR: amd64/85852 Submitted by: Nate Eldredge <nge at cs dot hmc dot edu>
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9c3acb0b |
| 15-Oct-2005 |
Jung-uk Kim <jkim@FreeBSD.org> |
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pen
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2.
Approved by: anholt (mentor)
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Revision tags: release/5.4.0_cvs, release/5.4.0, release/4.11.0_cvs, release/4.11.0, release/5.3.0_cvs, release/5.3.0 |
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430e272c |
| 08-Jun-2004 |
Peter Wemm <peter@FreeBSD.org> |
Initial PG_NX support (no-execute page bit) - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in ord
Initial PG_NX support (no-execute page bit) - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in order to stop treating the amd features as second class features (since it is now a primary feature bit set) and make it easier to export.
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Revision tags: release/4.10.0_cvs, release/4.10.0 |
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29ae923f |
| 05-Apr-2004 |
Warner Losh <imp@FreeBSD.org> |
Remove advertising clause from University of California Regent's license, per letter dated July 22, 1999.
Approved by: core
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Revision tags: release/5.2.1_cvs, release/5.2.1 |
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5e465ab9 |
| 29-Jan-2004 |
Peter Wemm <peter@FreeBSD.org> |
MFi386: add THERMTRIP msr values
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Revision tags: release/5.2.0_cvs, release/5.2.0 |
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cda07865 |
| 21-Nov-2003 |
Peter Wemm <peter@FreeBSD.org> |
Cosmetic and/or trivial sync up with i386.
Approved by: re (rwatson)
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bf2f09ee |
| 08-Nov-2003 |
Peter Wemm <peter@FreeBSD.org> |
The great s/npx/fpu/gi
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Revision tags: release/4.9.0_cvs, release/4.9.0 |
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13a27f29 |
| 23-Sep-2003 |
Peter Wemm <peter@FreeBSD.org> |
MFi386 rev 1.25 by jhb: add new MSR's and some missing older ones and APICBASE MSR constants.
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Revision tags: release/5.1.0_cvs, release/5.1.0 |
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afa88623 |
| 01-May-2003 |
Peter Wemm <peter@FreeBSD.org> |
Commit MD parts of a loosely functional AMD64 port. This is based on a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a
Commit MD parts of a loosely functional AMD64 port. This is based on a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
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Revision tags: release/4.8.0_cvs, release/4.8.0 |
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f4e27c44 |
| 22-Jan-2003 |
John Baldwin <jhb@FreeBSD.org> |
Bah, add in a missing space char I noticed when MFC'ing this.
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Revision tags: release/5.0.0_cvs, release/5.0.0 |
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72a1e0e2 |
| 08-Jan-2003 |
John Baldwin <jhb@FreeBSD.org> |
- Fix the name of the hyperthreading cpuid feature flag to be HTT instead of HHT. - Document fields returned in %ebx by a cpuid with %eax of 1.
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Revision tags: release/4.7.0_cvs, release/4.6.2_cvs, release/4.6.2, release/4.6.1, release/4.6.0_cvs |
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73cb2270 |
| 23-Jun-2002 |
Mark Peek <mp@FreeBSD.org> |
Add additional cpuid feature flags and put into a canonical format.
MFC after: 1 week
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Revision tags: release/4.5.0_cvs, release/4.4.0_cvs |
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9d146ac5 |
| 12-Jul-2001 |
Peter Wemm <peter@FreeBSD.org> |
Activate SSE/SIMD. This is the extra context switching support that we are required to do if we let user processes use the extra 128 bit registers etc.
This is the base part of the diff I got from:
Activate SSE/SIMD. This is the extra context switching support that we are required to do if we let user processes use the extra 128 bit registers etc.
This is the base part of the diff I got from: http://www.issei.org/issei/FreeBSD/sse.html I believe this is by: Mr. SUZUKI Issei <issei@issei.org> SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp> Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see http://kobe1995.net/~kaz/FreeBSD/SSE.en.html
I have fixed a couple of style(9) deviations. I have some followup commits to fix a couple of non-style things.
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Revision tags: release/4.3.0_cvs, release/4.3.0, release/4.2.0, release/4.1.1_cvs, release/4.1.0, release/3.5.0_cvs, release/4.0.0_cvs, release/3.4.0_cvs, release/3.3.0_cvs |
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ebb30c0b |
| 10-Sep-1999 |
Peter Wemm <peter@FreeBSD.org> |
Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during context switching and also enables SIMD since this ena
Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during context switching and also enables SIMD since this enables saving the extra CPU context that isn't saved with normal FPU regs. The other enables the SIMD instructions to use exception 16 (FPU) error reporting. Note, this doesn't turn on SIMD, just defines the bits.
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c3aac50f |
| 28-Aug-1999 |
Peter Wemm <peter@FreeBSD.org> |
$Id$ -> $FreeBSD$
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Revision tags: release/3.2.0 |
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1f2d03c0 |
| 07-Apr-1999 |
Mike Smith <msmith@FreeBSD.org> |
Add defines for the P6 model-specific registers.
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Revision tags: release/3.1.0, release/3.0.0, release/2.2.8 |
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4536af6a |
| 06-Oct-1998 |
KATO Takenori <kato@FreeBSD.org> |
- Implement enabling write allocate on AMD K5/K6/K6-2 cpus. The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow
- Implement enabling write allocate on AMD K5/K6/K6-2 cpus. The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>. - Fix stylistic bug in identcpu.c. - Update copyright in initcpu.c - Fix typo in LINT.
PR: 6269 and 6270
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Revision tags: release/2.2.7, release/2.2.6 |
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3a94cb7f |
| 04-Mar-1998 |
KATO Takenori <kato@FreeBSD.org> |
Defined CCR6 and CCR7 (configuration registers of M2 CPU.)
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Revision tags: release/2.2.5_cvs |
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9a9ad9f7 |
| 21-Jul-1997 |
Steve Passe <fsmp@FreeBSD.org> |
Enabled the FPU emilaute bit define: CR0_EM
Reviewed by: Bruce Evans <bde@zeta.org.au>
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