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92df0bda |
| 12-Jan-2009 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add basic amd64 support for VIA Nano processors.
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6811e5d4 |
| 05-Jan-2009 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.
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Revision tags: release/7.1.0_cvs, release/7.1.0 |
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41fe50f5 |
| 20-Dec-2008 |
Sam Leffler <sam@FreeBSD.org> |
MFH @ 186335
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39e52304 |
| 13-Dec-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add more CPUID bits from AMD CPUID Specification Rev. 2.28.
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5113aa0a |
| 26-Nov-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by: jhb, peter (early amd64 version)
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Revision tags: release/6.4.0_cvs, release/6.4.0 |
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e39dddd4 |
| 22-Oct-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Simplify AMD64_CPU_MODEL() and AMD64_CPU_FAMILY() macros as the base family should be at least 0xf00 for all supported platforms.
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87c919e8 |
| 22-Oct-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher even if BIOS does not advertise it.
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780f139b |
| 21-Oct-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Detect Advanced Power Management Information for AMD CPUs.
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e085f869 |
| 08-Aug-2008 |
Stanislav Sedov <stas@FreeBSD.org> |
- Add cpuctl(4) pseudo-device driver to provide access to some low-level features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpu
- Add cpuctl(4) pseudo-device driver to provide access to some low-level features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpucontrol(8) utility, that provides userland access to the features of cpuctl(4). - Add subsequent manpages.
The cpuctl(4) device operates as follows. The pseudo-device node cpuctlX is created for each cpu present in the systems. The pseudo-device minor number corresponds to the cpu number in the system. The cpuctl(4) pseudo- device allows a number of ioctl to be preformed, namely RDMSR/WRMSR/CPUID and UPDATE. The first pair alows the caller to read/write machine-specific registers from the correspondent CPU. cpuid data could be retrieved using the CPUID call, and microcode updates are applied via UPDATE.
The permissions are inforced based on the pseudo-device file permissions. RDMSR/CPUID will be allowed when the caller has read access to the device node, while WRMSR/UPDATE will be granted only when the node is opened for writing. There're also a number of priv(9) checks.
The cpucontrol(8) utility is intened to provide userland access to the cpuctl(4) device features. The utility also allows one to apply cpu microcode updates.
Currently only Intel and AMD cpus are supported and were tested.
Approved by: kib Reviewed by: rpaulo, cokane, Peter Jeremy MFC after: 1 month
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391664b1 |
| 12-Mar-2008 |
John Baldwin <jhb@FreeBSD.org> |
The variable MTRR registers actually have variable-sized PhysBase and PhysMask fields based on the number of physical address bits supported by the current CPU. The old code assumed 36 bits on i386
The variable MTRR registers actually have variable-sized PhysBase and PhysMask fields based on the number of physical address bits supported by the current CPU. The old code assumed 36 bits on i386 and 40 bits on amd64. In truth, all Intel CPUs up until recently used 36 bits (a newer Intel CPU uses 38 bits) and all the Opteron CPUs used 40 bits.
In at least one case (the new Intel CPU) having the size of the mask field wrong resulted in writing questionable values into the MTRR registers on the application processors (BSP as well if you modify the MTRRs via memcontrol or running X, etc.). The result of the questionable physmask was that all of memory was apparently treated as uncached rather than write-back resulting in a very significant performance hit.
Fix this by constructing a run-time mask for the PhysBase and PhysMask fields based on the number of physical address bits supported by the CPU. All 64-bit capable CPUs provide a count of PA bits supported via the 0x80000008 extended CPUID feature, so use that if it is available. If that feature is not available, then assume 36 PA bits.
While I'm here, expand the (now-unused) macros for the PhysBase and PhysMask fields to the current largest possible value (52 PA bits).
MFC after: 1 week PR: i386/120516 Reported by: Nokia
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336d8e55 |
| 11-Mar-2008 |
John Baldwin <jhb@FreeBSD.org> |
Add constants for the various fields in MTRR registers.
MFC after: 1 week Verified by: md5(1)
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Revision tags: release/7.0.0_cvs, release/7.0.0 |
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2cb23596 |
| 03-Feb-2008 |
David Schultz <das@FreeBSD.org> |
Add a few more CPUID feature bits while here. We don't support these features yet.
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67f6aa5c |
| 02-Feb-2008 |
David Schultz <das@FreeBSD.org> |
SSE4 CPUID bits
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Revision tags: release/6.3.0_cvs, release/6.3.0 |
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4ad86324 |
| 08-Dec-2007 |
Alan Cox <alc@FreeBSD.org> |
Recognize architectural support for 1GB virtual pages.
MFC after: 6 weeks
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83d18f22 |
| 15-Aug-2007 |
Dag-Erling Smørgrav <des@FreeBSD.org> |
Add a driver for the on-die digital thermal sensor found on Intel Core and newer CPUs (including Core 2 and Core / Core 2 based Xeons). The driver attaches to each cpu device and creates a sysctl no
Add a driver for the on-die digital thermal sensor found on Intel Core and newer CPUs (including Core 2 and Core / Core 2 based Xeons). The driver attaches to each cpu device and creates a sysctl node in that device's sysctl context (dev.cpu.N.temperature). When invoked, the handler binds to the appropriate CPU to ensure a correct reading.
Submitted by: Rui Paulo <rpaulo@fnop.net> Sponsored by: Google Summer of Code 2007 Tested by: des, marcus, Constantine A. Murenin, Ian FREISLICH Approved by: re (kensmith) MFC after: 3 weeks
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753bcb5c |
| 31-May-2007 |
Dag-Erling Smørgrav <des@FreeBSD.org> |
Add CPUID2_PDCM
Requested by: jkim MFC after: 3 days
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2498f259 |
| 20-Mar-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name in comment.
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ab5916a5 |
| 12-Mar-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add another CPUID for AMD CPUs and fix style(9) while I am here.
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Revision tags: release/6.2.0_cvs, release/6.2.0 |
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5efc6c44 |
| 09-Jan-2007 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.
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0758eaa2 |
| 13-Jul-2006 |
Jung-uk Kim <jkim@FreeBSD.org> |
Sync specialreg.h changes between amd64 and i386 with few fixes.
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444576c0 |
| 12-Jul-2006 |
Jung-uk Kim <jkim@FreeBSD.org> |
Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.
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Revision tags: release/5.5.0_cvs, release/5.5.0, release/6.1.0_cvs, release/6.1.0 |
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2b8a339c |
| 02-May-2006 |
John Baldwin <jhb@FreeBSD.org> |
Add various constants for the PAT MSR and the PAT PTE and PDE flags. Initialize the PAT MSR during boot to map PAT type 2 to Write-Combining (WC) instead of Uncached (UC-).
MFC after: 1 month
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Revision tags: release/6.0.0_cvs, release/6.0.0 |
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25736eb6 |
| 15-Oct-2005 |
Jung-uk Kim <jkim@FreeBSD.org> |
Correct few MSR addresses.
PR: amd64/85852 Submitted by: Nate Eldredge <nge at cs dot hmc dot edu>
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9c3acb0b |
| 15-Oct-2005 |
Jung-uk Kim <jkim@FreeBSD.org> |
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pen
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2.
Approved by: anholt (mentor)
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Revision tags: release/5.4.0_cvs, release/5.4.0, release/4.11.0_cvs, release/4.11.0, release/5.3.0_cvs, release/5.3.0 |
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430e272c |
| 08-Jun-2004 |
Peter Wemm <peter@FreeBSD.org> |
Initial PG_NX support (no-execute page bit) - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in ord
Initial PG_NX support (no-execute page bit) - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in order to stop treating the amd features as second class features (since it is now a primary feature bit set) and make it easier to export.
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