| nvme.h (d7b72f7b52f902da47cc7210a9121f4caabbcb9c) | nvme.h (4f3f3e9a1dee62c031fa67cfe64e11d6dd3fab1b) |
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| 1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 59 unchanged lines hidden (view full) --- 68#define NVME_MINOR(r) (((r) >> 8) & 0xff) 69 70/* 71 * Use to mark a command to apply to all namespaces, or to retrieve global 72 * log pages. 73 */ 74#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 75 | 1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 59 unchanged lines hidden (view full) --- 68#define NVME_MINOR(r) (((r) >> 8) & 0xff) 69 70/* 71 * Use to mark a command to apply to all namespaces, or to retrieve global 72 * log pages. 73 */ 74#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 75 |
| 76/* Cap transfers by the maximum addressable by page-sized PRP (4KB -> 2MB). */ 77#define NVME_MAX_XFER_SIZE MIN(maxphys, (PAGE_SIZE/8*PAGE_SIZE)) | 76/* Host memory buffer sizes are always in 4096 byte chunks */ 77#define NVME_HMB_UNITS 4096 |
| 78 | 78 |
| 79/* Many items are expressed in terms of power of two times MPS */ 80#define NVME_MPS_SHIFT 12 81 |
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| 79/* Register field definitions */ 80#define NVME_CAP_LO_REG_MQES_SHIFT (0) 81#define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 82#define NVME_CAP_LO_REG_CQR_SHIFT (16) 83#define NVME_CAP_LO_REG_CQR_MASK (0x1) 84#define NVME_CAP_LO_REG_AMS_SHIFT (17) 85#define NVME_CAP_LO_REG_AMS_MASK (0x3) 86#define NVME_CAP_LO_REG_TO_SHIFT (24) --- 123 unchanged lines hidden (view full) --- 210#define NVME_STATUS_M_SHIFT (14) 211#define NVME_STATUS_M_MASK (0x1) 212#define NVME_STATUS_DNR_SHIFT (15) 213#define NVME_STATUS_DNR_MASK (0x1) 214 215#define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 216#define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 217#define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) | 82/* Register field definitions */ 83#define NVME_CAP_LO_REG_MQES_SHIFT (0) 84#define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 85#define NVME_CAP_LO_REG_CQR_SHIFT (16) 86#define NVME_CAP_LO_REG_CQR_MASK (0x1) 87#define NVME_CAP_LO_REG_AMS_SHIFT (17) 88#define NVME_CAP_LO_REG_AMS_MASK (0x3) 89#define NVME_CAP_LO_REG_TO_SHIFT (24) --- 123 unchanged lines hidden (view full) --- 213#define NVME_STATUS_M_SHIFT (14) 214#define NVME_STATUS_M_MASK (0x1) 215#define NVME_STATUS_DNR_SHIFT (15) 216#define NVME_STATUS_DNR_MASK (0x1) 217 218#define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 219#define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 220#define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) |
| 221#define NVME_STATUS_GET_CRD(st) (((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK) |
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| 218#define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 219#define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 220 221#define NVME_PWR_ST_MPS_SHIFT (0) 222#define NVME_PWR_ST_MPS_MASK (0x1) 223#define NVME_PWR_ST_NOPS_SHIFT (1) 224#define NVME_PWR_ST_NOPS_MASK (0x1) 225#define NVME_PWR_ST_RRT_SHIFT (0) --- 1882 unchanged lines hidden --- | 222#define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 223#define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 224 225#define NVME_PWR_ST_MPS_SHIFT (0) 226#define NVME_PWR_ST_MPS_MASK (0x1) 227#define NVME_PWR_ST_NOPS_SHIFT (1) 228#define NVME_PWR_ST_NOPS_MASK (0x1) 229#define NVME_PWR_ST_RRT_SHIFT (0) --- 1882 unchanged lines hidden --- |