atpic.c (ebf5747bdb4c8c502d56f86f341be0f2a9080109) atpic.c (bd50262f705c4fed70ea94d16a0f19b5f5497cf2)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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75
76inthand_t
77 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
78 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
79 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
80 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
81 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
82 IDTVEC(atpic_intr15);
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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75
76inthand_t
77 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
78 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
79 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
80 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
81 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
82 IDTVEC(atpic_intr15);
83/* XXXKIB i386 uses stubs until pti comes */
84inthand_t
85 IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti),
86 IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti),
87 IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti),
88 IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti),
89 IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti),
90 IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti),
91 IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti),
92 IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti);
83
84#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
85
86#define ATPIC(io, base, eoi, imenptr) \
87 { { atpic_enable_source, atpic_disable_source, (eoi), \
88 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
89 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
90 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
91 (imenptr) }
92
93#define INTSRC(irq) \
94 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
93
94#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
95
96#define ATPIC(io, base, eoi, imenptr) \
97 { { atpic_enable_source, atpic_disable_source, (eoi), \
98 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
99 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
100 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
101 (imenptr) }
102
103#define INTSRC(irq) \
104 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
95 (irq) % 8 }
105 IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 }
96
97struct atpic {
98 struct pic at_pic;
99 int at_ioaddr;
100 int at_irqbase;
101 uint8_t at_intbase;
102 uint8_t *at_imen;
103};
104
105struct atpic_intsrc {
106 struct intsrc at_intsrc;
106
107struct atpic {
108 struct pic at_pic;
109 int at_ioaddr;
110 int at_irqbase;
111 uint8_t at_intbase;
112 uint8_t *at_imen;
113};
114
115struct atpic_intsrc {
116 struct intsrc at_intsrc;
107 inthand_t *at_intr;
117 inthand_t *at_intr, *at_intr_pti;
108 int at_irq; /* Relative to PIC base. */
109 enum intr_trigger at_trigger;
110 u_long at_count;
111 u_long at_straycount;
112};
113
114static void atpic_enable_source(struct intsrc *isrc);
115static void atpic_disable_source(struct intsrc *isrc, int eoi);

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403
404 /* Install low-level interrupt handlers for all of our IRQs. */
405 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
406 if (i == ICU_SLAVEID)
407 continue;
408 ai->at_intsrc.is_count = &ai->at_count;
409 ai->at_intsrc.is_straycount = &ai->at_straycount;
410 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
118 int at_irq; /* Relative to PIC base. */
119 enum intr_trigger at_trigger;
120 u_long at_count;
121 u_long at_straycount;
122};
123
124static void atpic_enable_source(struct intsrc *isrc);
125static void atpic_disable_source(struct intsrc *isrc, int eoi);

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413
414 /* Install low-level interrupt handlers for all of our IRQs. */
415 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
416 if (i == ICU_SLAVEID)
417 continue;
418 ai->at_intsrc.is_count = &ai->at_count;
419 ai->at_intsrc.is_straycount = &ai->at_straycount;
420 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
411 ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
421 ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC,
422 SEL_KPL, GSEL_ATPIC);
412 }
413
414 /*
415 * Look for an ELCR. If we find one, update the trigger modes.
416 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
417 * edge triggered and that everything else is level triggered.
418 * We only use the trigger information to reprogram the ELCR if
419 * we have one and as an optimization to avoid masking edge

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424
425 /*
426 * Look for an ELCR. If we find one, update the trigger modes.
427 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
428 * edge triggered and that everything else is level triggered.
429 * We only use the trigger information to reprogram the ELCR if
430 * we have one and as an optimization to avoid masking edge

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