est.c (f6e61711eddfa193d1c3e8a1ffd53c6395e9b8c8) est.c (4577cf3744b98d0fa7cea80c75079c3cf5155471)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004 Colin Percival
5 * Copyright (c) 2005 Nate Lawson
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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45#include <machine/md_var.h>
46#include <machine/specialreg.h>
47
48#include <contrib/dev/acpica/include/acpi.h>
49
50#include <dev/acpica/acpivar.h>
51#include "acpi_if.h"
52
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004 Colin Percival
5 * Copyright (c) 2005 Nate Lawson
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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45#include <machine/md_var.h>
46#include <machine/specialreg.h>
47
48#include <contrib/dev/acpica/include/acpi.h>
49
50#include <dev/acpica/acpivar.h>
51#include "acpi_if.h"
52
53#include <x86/cpufreq/hwpstate_intel_internal.h>
54
53/* Status/control registers (from the IA-32 System Programming Guide). */
54#define MSR_PERF_STATUS 0x198
55#define MSR_PERF_CTL 0x199
56
57/* Register and bit for enabling SpeedStep. */
58#define MSR_MISC_ENABLE 0x1a0
59#define MSR_SS_ENABLE (1<<16)
60

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893static driver_t est_driver = {
894 "est",
895 est_methods,
896 sizeof(struct est_softc),
897};
898
899static devclass_t est_devclass;
900DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
55/* Status/control registers (from the IA-32 System Programming Guide). */
56#define MSR_PERF_STATUS 0x198
57#define MSR_PERF_CTL 0x199
58
59/* Register and bit for enabling SpeedStep. */
60#define MSR_MISC_ENABLE 0x1a0
61#define MSR_SS_ENABLE (1<<16)
62

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895static driver_t est_driver = {
896 "est",
897 est_methods,
898 sizeof(struct est_softc),
899};
900
901static devclass_t est_devclass;
902DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
903MODULE_DEPEND(est, hwpstate_intel, 1, 1, 1);
901
902static int
903est_features(driver_t *driver, u_int *features)
904{
905
906 /*
907 * Notify the ACPI CPU that we support direct access to MSRs.
908 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS.
909 */
910 *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT;
911 return (0);
912}
913
914static void
915est_identify(driver_t *driver, device_t parent)
916{
917 device_t child;
918
904
905static int
906est_features(driver_t *driver, u_int *features)
907{
908
909 /*
910 * Notify the ACPI CPU that we support direct access to MSRs.
911 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS.
912 */
913 *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT;
914 return (0);
915}
916
917static void
918est_identify(driver_t *driver, device_t parent)
919{
920 device_t child;
921
922 /*
923 * Defer to hwpstate if it is present. This priority logic
924 * should be replaced with normal newbus probing in the
925 * future.
926 */
927 intel_hwpstate_identify(NULL, parent);
928 if (device_find_child(parent, "hwpstate_intel", -1) != NULL)
929 return;
930
919 /* Make sure we're not being doubly invoked. */
920 if (device_find_child(parent, "est", -1) != NULL)
921 return;
922
923 /* Check that CPUID is supported and the vendor is Intel.*/
924 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
925 cpu_vendor_id != CPU_VENDOR_CENTAUR))
926 return;

--- 431 unchanged lines hidden --- 		931 /* Make sure we're not being doubly invoked. */
932 if (device_find_child(parent, "est", -1) != NULL)
933 return;
934
935 /* Check that CPUID is supported and the vendor is Intel.*/
936 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
937 cpu_vendor_id != CPU_VENDOR_CENTAUR))
938 return;

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