| pte.h (de09dcebd720d5776df4cc4e67ffc7da757e4305) | pte.h (b7312c3df83df96662e83aaa0eaadda7ef66c8e3) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. --- 69 unchanged lines hidden (view full) --- 78#define PTE_R (1 << 1) /* Read */ 79#define PTE_V (1 << 0) /* Valid */ 80#define PTE_RWX (PTE_R | PTE_W | PTE_X) 81#define PTE_RX (PTE_R | PTE_X) 82#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D) 83#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_G | PTE_U | \ 84 PTE_SW_MANAGED | PTE_SW_WIRED) 85 | 1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. --- 69 unchanged lines hidden (view full) --- 78#define PTE_R (1 << 1) /* Read */ 79#define PTE_V (1 << 0) /* Valid */ 80#define PTE_RWX (PTE_R | PTE_W | PTE_X) 81#define PTE_RX (PTE_R | PTE_X) 82#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D) 83#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_G | PTE_U | \ 84 PTE_SW_MANAGED | PTE_SW_WIRED) 85 |
| 86/* 87 * Svpbmt Memory Attribute (MA) bits [62:61]. 88 * 89 * +------+-------+------------------------------------------------------------+ 90 * | Mode | Value | Requested Memory Attributes | 91 * +------+-------+------------------------------------------------------------+ 92 * | PMA | 00 | None, inherited from Physical Memory Attributes (firmware) | 93 * | NC | 01 | Non-cacheable, idempotent, weakly-ordered (RVWMO), | 94 * | | | main memory | 95 * | IO | 10 | Non-cacheable, non-idempotent, strongly-ordered, I/O | 96 * | -- | 11 | Reserved | 97 * +------+-------+------------------------------------------------------------+ 98 */ 99#define PTE_MA_SHIFT 61 100#define PTE_MA_MASK (0x3ul << PTE_MA_SHIFT) 101#define PTE_MA_NONE (0ul) 102#define PTE_MA_NC (1ul << PTE_MA_SHIFT) 103#define PTE_MA_IO (2ul << PTE_MA_SHIFT) 104 |
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| 86/* Bits 63 - 54 are reserved for future use. */ 87#define PTE_HI_MASK 0xFFC0000000000000ULL 88 89#define PTE_PPN0_S 10 90#define PTE_PPN1_S 19 91#define PTE_PPN2_S 28 92#define PTE_PPN3_S 37 93#define PTE_SIZE 8 94 95#endif /* !_MACHINE_PTE_H_ */ | 105/* Bits 63 - 54 are reserved for future use. */ 106#define PTE_HI_MASK 0xFFC0000000000000ULL 107 108#define PTE_PPN0_S 10 109#define PTE_PPN1_S 19 110#define PTE_PPN2_S 28 111#define PTE_PPN3_S 37 112#define PTE_SIZE 8 113 114#endif /* !_MACHINE_PTE_H_ */ |