ata_macio.c (10b3b54548f2290bbe8d8f88c59c28d12b7a635d) ata_macio.c (066f913a94b134b6d5e32b6af88f297c7da9c031)
1/*-
2 * Copyright 2002 by Peter Grehan. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.

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106 { 45, 90 }, /* UDMA 3 */
107 { 30, 90 } /* UDMA 4 */
108};
109
110/*
111 * Define the macio ata bus attachment.
112 */
113static int ata_macio_probe(device_t dev);
1/*-
2 * Copyright 2002 by Peter Grehan. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.

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106 { 45, 90 }, /* UDMA 3 */
107 { 30, 90 } /* UDMA 4 */
108};
109
110/*
111 * Define the macio ata bus attachment.
112 */
113static int ata_macio_probe(device_t dev);
114static void ata_macio_setmode(device_t parent, device_t dev);
114static int ata_macio_setmode(device_t dev, int target, int mode);
115static int ata_macio_attach(device_t dev);
116static int ata_macio_begin_transaction(struct ata_request *request);
117
118static device_method_t ata_macio_methods[] = {
119 /* Device interface */
120 DEVMETHOD(device_probe, ata_macio_probe),
121 DEVMETHOD(device_attach, ata_macio_attach),
122

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188 ch->r_io[i].res = sc->sc_mem;
189 ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
190 }
191 ch->r_io[ATA_CONTROL].res = sc->sc_mem;
192 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
193 ata_default_registers(dev);
194
195 ch->unit = 0;
115static int ata_macio_attach(device_t dev);
116static int ata_macio_begin_transaction(struct ata_request *request);
117
118static device_method_t ata_macio_methods[] = {
119 /* Device interface */
120 DEVMETHOD(device_probe, ata_macio_probe),
121 DEVMETHOD(device_attach, ata_macio_attach),
122

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188 ch->r_io[i].res = sc->sc_mem;
189 ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
190 }
191 ch->r_io[ATA_CONTROL].res = sc->sc_mem;
192 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
193 ata_default_registers(dev);
194
195 ch->unit = 0;
196 ch->flags |= ATA_USE_16BIT;
196 ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA;
197 ata_generic_hw(dev);
198
199 return (ata_probe(dev));
200}
201
202static int
203ata_macio_attach(device_t dev)
204{

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242#endif
243
244 /* Set begin_transaction */
245 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
246
247 return ata_attach(dev);
248}
249
197 ata_generic_hw(dev);
198
199 return (ata_probe(dev));
200}
201
202static int
203ata_macio_attach(device_t dev)
204{

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242#endif
243
244 /* Set begin_transaction */
245 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
246
247 return ata_attach(dev);
248}
249
250static void
251ata_macio_setmode(device_t parent, device_t dev)
250static int
251ata_macio_setmode(device_t dev, int target, int mode)
252{
252{
253 struct ata_device *atadev = device_get_softc(dev);
254 struct ata_macio_softc *sc = device_get_softc(parent);
255 int mode = atadev->mode;
253 struct ata_macio_softc *sc = device_get_softc(dev);
256
257 int min_cycle = 0, min_active = 0;
258 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
259
254
255 int min_cycle = 0, min_active = 0;
256 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
257
260 mode = ata_limit_mode(dev, mode, sc->max_mode);
258 mode = min(mode, sc->max_mode);
261
259
262 /* XXX Some controllers don't work correctly with ATAPI DMA */
263 if (atadev->param.config & ATA_PROTO_ATAPI)
264 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
265
266 if (ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
267 return;
268
269 atadev->mode = mode;
270
271 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
272 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
273 min_active = udma_timings[mode & ATA_MODE_MASK].active;
274
275 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
276 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
277
278 /* mask: 0x1ff00000 */
260 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
261 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
262 min_active = udma_timings[mode & ATA_MODE_MASK].active;
263
264 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
265 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
266
267 /* mask: 0x1ff00000 */
279 sc->udmaconf[atadev->unit] =
268 sc->udmaconf[target] =
280 (cycle_tick << 21) | (act_tick << 25) | 0x100000;
281 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
282 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
283 min_active = dma_timings[mode & ATA_MODE_MASK].active;
284
285 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
286 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
287
288 if (sc->rev == 4) {
289 inact_tick = cycle_tick - act_tick;
290 /* mask: 0x001ffc00 */
269 (cycle_tick << 21) | (act_tick << 25) | 0x100000;
270 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
271 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
272 min_active = dma_timings[mode & ATA_MODE_MASK].active;
273
274 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
275 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
276
277 if (sc->rev == 4) {
278 inact_tick = cycle_tick - act_tick;
279 /* mask: 0x001ffc00 */
291 sc->wdmaconf[atadev->unit] =
280 sc->wdmaconf[target] =
292 (act_tick << 10) | (inact_tick << 15);
293 } else {
294 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
295 if (inact_tick < DMA_REC_MIN)
296 inact_tick = DMA_REC_MIN;
297 half_tick = 0; /* XXX */
298
299 /* mask: 0xfffff800 */
281 (act_tick << 10) | (inact_tick << 15);
282 } else {
283 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
284 if (inact_tick < DMA_REC_MIN)
285 inact_tick = DMA_REC_MIN;
286 half_tick = 0; /* XXX */
287
288 /* mask: 0xfffff800 */
300 sc->wdmaconf[atadev->unit] = (half_tick << 21)
289 sc->wdmaconf[target] = (half_tick << 21)
301 | (inact_tick << 16) | (act_tick << 11);
302 }
303 } else {
304 min_cycle =
305 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
306 min_active =
307 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
308
309 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
310 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
311
312 if (sc->rev == 4) {
313 inact_tick = cycle_tick - act_tick;
314
315 /* mask: 0x000003ff */
290 | (inact_tick << 16) | (act_tick << 11);
291 }
292 } else {
293 min_cycle =
294 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
295 min_active =
296 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
297
298 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
299 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
300
301 if (sc->rev == 4) {
302 inact_tick = cycle_tick - act_tick;
303
304 /* mask: 0x000003ff */
316 sc->pioconf[atadev->unit] =
305 sc->pioconf[target] =
317 (inact_tick << 5) | act_tick;
318 } else {
319 if (act_tick < PIO_ACT_MIN)
320 act_tick = PIO_ACT_MIN;
321
322 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
323 if (inact_tick < PIO_REC_MIN)
324 inact_tick = PIO_REC_MIN;
325
326 /* mask: 0x000007ff */
306 (inact_tick << 5) | act_tick;
307 } else {
308 if (act_tick < PIO_ACT_MIN)
309 act_tick = PIO_ACT_MIN;
310
311 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
312 if (inact_tick < PIO_REC_MIN)
313 inact_tick = PIO_REC_MIN;
314
315 /* mask: 0x000007ff */
327 sc->pioconf[atadev->unit] =
316 sc->pioconf[target] =
328 (inact_tick << 5) | act_tick;
329 }
330 }
317 (inact_tick << 5) | act_tick;
318 }
319 }
320
321 return (mode);
331}
332
333static int
334ata_macio_begin_transaction(struct ata_request *request)
335{
322}
323
324static int
325ata_macio_begin_transaction(struct ata_request *request)
326{
336 struct ata_device *atadev = device_get_softc(request->dev);
337 struct ata_macio_softc *sc = device_get_softc(request->parent);
338
339 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
327 struct ata_macio_softc *sc = device_get_softc(request->parent);
328
329 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
340 sc->udmaconf[atadev->unit] | sc->wdmaconf[atadev->unit]
341 | sc->pioconf[atadev->unit]);
330 sc->udmaconf[request->unit] | sc->wdmaconf[request->unit]
331 | sc->pioconf[request->unit]);
342
343 return ata_begin_transaction(request);
344}
345
332
333 return ata_begin_transaction(request);
334}
335