| i2c.c (b652778e426d00b6a1df29bbd86869db86f36e25) | i2c.c (d1e99670ae56b733bfffe627047eb0a552b5ac7e) |
|---|---|
| 1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 270 unchanged lines hidden (view full) --- 279 280 mtx_lock(&sc->mutex); 281 status = i2c_read_reg(sc, I2C_STATUS_REG); 282 /* Check if bus is idle or busy */ 283 if (status & I2CSR_MBB) { 284 debugf("bus busy"); 285 mtx_unlock(&sc->mutex); 286 i2c_stop(dev); | 1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 270 unchanged lines hidden (view full) --- 279 280 mtx_lock(&sc->mutex); 281 status = i2c_read_reg(sc, I2C_STATUS_REG); 282 /* Check if bus is idle or busy */ 283 if (status & I2CSR_MBB) { 284 debugf("bus busy"); 285 mtx_unlock(&sc->mutex); 286 i2c_stop(dev); |
| 287 return (IIC_EBUSBSY); | 287 return (IIC_EBUSERR); |
| 288 } 289 290 /* Set start condition */ 291 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 292 /* Write target address - LSB is R/W bit */ 293 i2c_write_reg(sc, I2C_DATA_REG, slave); 294 DELAY(1250); 295 --- 132 unchanged lines hidden --- | 288 } 289 290 /* Set start condition */ 291 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 292 /* Write target address - LSB is R/W bit */ 293 i2c_write_reg(sc, I2C_DATA_REG, slave); 294 DELAY(1250); 295 --- 132 unchanged lines hidden --- |