mp_cpudep.c (10b3b54548f2290bbe8d8f88c59c28d12b7a635d) mp_cpudep.c (999987e51a2db77e5407c5a2cdb5d759b1317714)
1/*-
2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 33 unchanged lines hidden (view full) ---

42
43extern void dcache_enable(void);
44extern void dcache_inval(void);
45extern void icache_enable(void);
46extern void icache_inval(void);
47
48volatile void *ap_pcpu;
49
1/*-
2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 33 unchanged lines hidden (view full) ---

42
43extern void dcache_enable(void);
44extern void dcache_inval(void);
45extern void icache_enable(void);
46extern void icache_inval(void);
47
48volatile void *ap_pcpu;
49
50uint32_t
50uintptr_t
51cpudep_ap_bootstrap()
52{
53 uint32_t msr, sp, csr;
54
55 /* Enable L1 caches */
56 csr = mfspr(SPR_L1CSR0);
57 if ((csr & L1CSR0_DCE) == 0) {
58 dcache_inval();

--- 14 unchanged lines hidden (view full) ---

73 pcpup->pc_curthread = pcpup->pc_idlethread;
74 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
75 sp = pcpup->pc_curpcb->pcb_sp;
76
77 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */
78
79 return (sp);
80}
51cpudep_ap_bootstrap()
52{
53 uint32_t msr, sp, csr;
54
55 /* Enable L1 caches */
56 csr = mfspr(SPR_L1CSR0);
57 if ((csr & L1CSR0_DCE) == 0) {
58 dcache_inval();

--- 14 unchanged lines hidden (view full) ---

73 pcpup->pc_curthread = pcpup->pc_idlethread;
74 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
75 sp = pcpup->pc_curpcb->pcb_sp;
76
77 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */
78
79 return (sp);
80}
81
82void
83cpudep_ap_setup()
84{
85}