mmu_oea.c (8d8cca480cf154b46c59a691aed5abbaea4ef377) mmu_oea.c (c139f23d171c1a032ae57608f8dd72c47cda701e)
1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
7 *
8 * Redistribution and use in source and binary forms, with or without

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599 return (-1);
600 else if (mapa->om_pa > mapb->om_pa)
601 return (1);
602 else
603 return (0);
604}
605
606void
1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
7 *
8 * Redistribution and use in source and binary forms, with or without

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599 return (-1);
600 else if (mapa->om_pa > mapb->om_pa)
601 return (1);
602 else
603 return (0);
604}
605
606void
607pmap_cpu_bootstrap(volatile uint32_t *trcp, int ap)
607pmap_cpu_bootstrap(int ap)
608{
609 u_int sdr;
610 int i;
611
608{
609 u_int sdr;
610 int i;
611
612 trcp[0] = 0x1000;
613 trcp[1] = (uint32_t)&pmap_cpu_bootstrap;
614
615 if (ap) {
616 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
617 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
618 isync();
619 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
620 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
621 isync();
622 }
623
612 if (ap) {
613 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
614 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
615 isync();
616 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
617 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
618 isync();
619 }
620
624 trcp[0] = 0x1001;
625
626 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
627 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
628 isync();
629
621 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
622 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
623 isync();
624
630 trcp[0] = 0x1002;
631
632 __asm __volatile("mtibatu 1,%0" :: "r"(0));
633 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
634 __asm __volatile("mtibatu 2,%0" :: "r"(0));
635 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
636 __asm __volatile("mtibatu 3,%0" :: "r"(0));
637 isync();
638
625 __asm __volatile("mtibatu 1,%0" :: "r"(0));
626 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
627 __asm __volatile("mtibatu 2,%0" :: "r"(0));
628 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
629 __asm __volatile("mtibatu 3,%0" :: "r"(0));
630 isync();
631
639 trcp[0] = 0x1003;
640
641 for (i = 0; i < 16; i++)
642 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
643
632 for (i = 0; i < 16; i++)
633 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
634
644 trcp[0] = 0x1004;
645
646 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
647 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
648 __asm __volatile("sync");
649
635 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
636 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
637 __asm __volatile("sync");
638
650 trcp[0] = 0x1005;
651
652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
653 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
654 isync();
655
639 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
640 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
641 isync();
642
656 trcp[0] = 0x1006;
657 trcp[1] = sdr;
658
659 tlbia();
643 tlbia();
660
661 trcp[0] = 0x1007;
662}
663
664void
665moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
666{
667 ihandle_t mmui;
668 phandle_t chosen, mmu;
669 int sz;
670 int i, j;
671 int ofw_mappings;
644}
645
646void
647moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
648{
649 ihandle_t mmui;
650 phandle_t chosen, mmu;
651 int sz;
652 int i, j;
653 int ofw_mappings;
672 uint32_t trace[2];
673 vm_size_t size, physsz, hwphyssz;
674 vm_offset_t pa, va, off;
675
676 /*
677 * Set up BAT0 to map the lowest 256 MB area
678 */
679 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
680 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);

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893 PMAP_LOCK_INIT(kernel_pmap);
894 for (i = 0; i < 16; i++) {
895 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
896 }
897 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
898 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
899 kernel_pmap->pm_active = ~0;
900
654 vm_size_t size, physsz, hwphyssz;
655 vm_offset_t pa, va, off;
656
657 /*
658 * Set up BAT0 to map the lowest 256 MB area
659 */
660 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
661 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);

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874 PMAP_LOCK_INIT(kernel_pmap);
875 for (i = 0; i < 16; i++) {
876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
877 }
878 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
879 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
880 kernel_pmap->pm_active = ~0;
881
901 pmap_cpu_bootstrap(trace, 0);
882 pmap_cpu_bootstrap(0);
902
903 pmap_bootstrapped++;
904
905 /*
906 * Set the start and end of kva.
907 */
908 virtual_avail = VM_MIN_KERNEL_ADDRESS;
909 virtual_end = VM_MAX_KERNEL_ADDRESS;

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884 pmap_bootstrapped++;
885
886 /*
887 * Set the start and end of kva.
888 */
889 virtual_avail = VM_MIN_KERNEL_ADDRESS;
890 virtual_end = VM_MAX_KERNEL_ADDRESS;

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