| if_xl.c (4f58a95ce1229a3d20a787f37863fc91af9ab98a) | if_xl.c (0ecf6b16c82b7801d64bd221f566fc89482fb719) |
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| 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 2630 unchanged lines hidden (view full) --- 2639 /* 2640 * Place the request for the upload interrupt 2641 * in the last descriptor in the chain. This way, if 2642 * we're chaining several packets at once, we'll only 2643 * get an interrupt once for the whole chain rather than 2644 * once for each packet. 2645 */ 2646 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); | 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 2630 unchanged lines hidden (view full) --- 2639 /* 2640 * Place the request for the upload interrupt 2641 * in the last descriptor in the chain. This way, if 2642 * we're chaining several packets at once, we'll only 2643 * get an interrupt once for the whole chain rather than 2644 * once for each packet. 2645 */ 2646 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); |
| 2647 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2648 BUS_DMASYNC_PREWRITE); | |
| 2649 2650 /* 2651 * Queue the packets. If the TX channel is clear, update 2652 * the downlist pointer register. 2653 */ 2654 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2655 xl_wait(sc); 2656 --- 4 unchanged lines hidden (view full) --- 2661 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2662 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2663 htole32(~XL_TXSTAT_DL_INTR); 2664 sc->xl_cdata.xl_tx_tail = cur_tx; 2665 } else { 2666 sc->xl_cdata.xl_tx_head = start_tx; 2667 sc->xl_cdata.xl_tx_tail = cur_tx; 2668 } | 2647 2648 /* 2649 * Queue the packets. If the TX channel is clear, update 2650 * the downlist pointer register. 2651 */ 2652 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2653 xl_wait(sc); 2654 --- 4 unchanged lines hidden (view full) --- 2659 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2660 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2661 htole32(~XL_TXSTAT_DL_INTR); 2662 sc->xl_cdata.xl_tx_tail = cur_tx; 2663 } else { 2664 sc->xl_cdata.xl_tx_head = start_tx; 2665 sc->xl_cdata.xl_tx_tail = cur_tx; 2666 } |
| 2667 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2668 BUS_DMASYNC_PREWRITE); |
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| 2669 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2670 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2671 2672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2673 2674 XL_SEL_WIN(7); 2675 2676 /* --- 83 unchanged lines hidden (view full) --- 2760 /* 2761 * Place the request for the upload interrupt 2762 * in the last descriptor in the chain. This way, if 2763 * we're chaining several packets at once, we'll only 2764 * get an interrupt once for the whole chain rather than 2765 * once for each packet. 2766 */ 2767 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); | 2669 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2670 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2671 2672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2673 2674 XL_SEL_WIN(7); 2675 2676 /* --- 83 unchanged lines hidden (view full) --- 2760 /* 2761 * Place the request for the upload interrupt 2762 * in the last descriptor in the chain. This way, if 2763 * we're chaining several packets at once, we'll only 2764 * get an interrupt once for the whole chain rather than 2765 * once for each packet. 2766 */ 2767 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); |
| 2768 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2769 BUS_DMASYNC_PREWRITE); | |
| 2770 2771 /* Start transmission */ 2772 sc->xl_cdata.xl_tx_prod = idx; 2773 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); | 2768 2769 /* Start transmission */ 2770 sc->xl_cdata.xl_tx_prod = idx; 2771 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); |
| 2772 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2773 BUS_DMASYNC_PREWRITE); |
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| 2774 2775 /* 2776 * Set a timeout in case the chip goes out to lunch. 2777 */ 2778 sc->xl_wdog_timer = 5; 2779} 2780 2781static void --- 635 unchanged lines hidden --- | 2774 2775 /* 2776 * Set a timeout in case the chip goes out to lunch. 2777 */ 2778 sc->xl_wdog_timer = 5; 2779} 2780 2781static void --- 635 unchanged lines hidden --- |