| if_stereg.h (9199c09a159c4e3e98c212d4eec1edc5252d9e33) | if_stereg.h (c8befdd5b608fa02cda3cdd4fe8b5a9eb87c6cad) |
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| 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 49 unchanged lines hidden (view full) --- 58#define STE_TX_DMABURST_THRESH 0x08 59#define STE_TX_DMAURG_THRESH 0x09 60#define STE_TX_DMAPOLL_PERIOD 0x0A 61#define STE_RX_DMASTATUS 0x0C 62#define STE_RX_DMALIST_PTR 0x10 63#define STE_RX_DMABURST_THRESH 0x14 64#define STE_RX_DMAURG_THRESH 0x15 65#define STE_RX_DMAPOLL_PERIOD 0x16 | 1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 49 unchanged lines hidden (view full) --- 58#define STE_TX_DMABURST_THRESH 0x08 59#define STE_TX_DMAURG_THRESH 0x09 60#define STE_TX_DMAPOLL_PERIOD 0x0A 61#define STE_RX_DMASTATUS 0x0C 62#define STE_RX_DMALIST_PTR 0x10 63#define STE_RX_DMABURST_THRESH 0x14 64#define STE_RX_DMAURG_THRESH 0x15 65#define STE_RX_DMAPOLL_PERIOD 0x16 |
| 66#define STE_COUNTDOWN 0x18 | |
| 67#define STE_DEBUGCTL 0x1A 68#define STE_ASICCTL 0x30 69#define STE_EEPROM_DATA 0x34 70#define STE_EEPROM_CTL 0x36 71#define STE_FIFOCTL 0x3A 72#define STE_TX_STARTTHRESH 0x3C 73#define STE_RX_EARLYTHRESH 0x3E 74#define STE_EXT_ROMADDR 0x40 75#define STE_EXT_ROMDATA 0x44 76#define STE_WAKE_EVENT 0x45 77#define STE_TX_STATUS 0x46 78#define STE_TX_FRAMEID 0x47 | 66#define STE_DEBUGCTL 0x1A 67#define STE_ASICCTL 0x30 68#define STE_EEPROM_DATA 0x34 69#define STE_EEPROM_CTL 0x36 70#define STE_FIFOCTL 0x3A 71#define STE_TX_STARTTHRESH 0x3C 72#define STE_RX_EARLYTHRESH 0x3E 73#define STE_EXT_ROMADDR 0x40 74#define STE_EXT_ROMDATA 0x44 75#define STE_WAKE_EVENT 0x45 76#define STE_TX_STATUS 0x46 77#define STE_TX_FRAMEID 0x47 |
| 78#define STE_COUNTDOWN 0x48 |
|
| 79#define STE_ISR_ACK 0x4A 80#define STE_IMR 0x4C 81#define STE_ISR 0x4E 82#define STE_MACCTL0 0x50 83#define STE_MACCTL1 0x52 84#define STE_PAR0 0x54 85#define STE_PAR1 0x56 86#define STE_PAR2 0x58 87#define STE_MAX_FRAMELEN 0x5A 88#define STE_RX_MODE 0x5C 89#define STE_TX_RECLAIM_THRESH 0x5D 90#define STE_PHYCTL 0x5E 91#define STE_MAR0 0x60 92#define STE_MAR1 0x62 93#define STE_MAR2 0x64 94#define STE_MAR3 0x66 | 79#define STE_ISR_ACK 0x4A 80#define STE_IMR 0x4C 81#define STE_ISR 0x4E 82#define STE_MACCTL0 0x50 83#define STE_MACCTL1 0x52 84#define STE_PAR0 0x54 85#define STE_PAR1 0x56 86#define STE_PAR2 0x58 87#define STE_MAX_FRAMELEN 0x5A 88#define STE_RX_MODE 0x5C 89#define STE_TX_RECLAIM_THRESH 0x5D 90#define STE_PHYCTL 0x5E 91#define STE_MAR0 0x60 92#define STE_MAR1 0x62 93#define STE_MAR2 0x64 94#define STE_MAR3 0x66 |
| 95#define STE_STATS 0x68 |
|
| 95 | 96 |
| 96#define STE_STAT_RX_OCTETS_LO 0x68 97#define STE_STAT_RX_OCTETS_HI 0x6A 98#define STE_STAT_TX_OCTETS_LO 0x6C 99#define STE_STAT_TX_OCTETS_HI 0x6E 100#define STE_STAT_TX_FRAMES 0x70 101#define STE_STAT_RX_FRAMES 0x72 102#define STE_STAT_CARRIER_ERR 0x74 103#define STE_STAT_LATE_COLLS 0x75 104#define STE_STAT_MULTI_COLLS 0x76 105#define STE_STAT_SINGLE_COLLS 0x77 106#define STE_STAT_TX_DEFER 0x78 107#define STE_STAT_RX_LOST 0x79 108#define STE_STAT_TX_EXDEFER 0x7A 109#define STE_STAT_TX_ABORT 0x7B 110#define STE_STAT_TX_BCAST 0x7C 111#define STE_STAT_RX_BCAST 0x7D 112#define STE_STAT_TX_MCAST 0x7E 113#define STE_STAT_RX_MCAST 0x7F | 97#define STE_LATE_COLLS 0x75 98#define STE_MULTI_COLLS 0x76 99#define STE_SINGLE_COLLS 0x77 |
| 114 115#define STE_DMACTL_RXDMA_STOPPED 0x00000001 116#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 117#define STE_DMACTL_TXDMA_STOPPED 0x00000004 118#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 119#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 120#define STE_DMACTL_RXDMA_STALL 0x00000100 121#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 --- 86 unchanged lines hidden (view full) --- 208#define STE_ASICCTL_FIFO_RESET 0x00100000 209#define STE_ASICCTL_NETWORK_RESET 0x00200000 210#define STE_ASICCTL_HOST_RESET 0x00400000 211#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 212#define STE_ASICCTL_EXTRESET_RESET 0x01000000 213#define STE_ASICCTL_SOFTINTR 0x02000000 214#define STE_ASICCTL_RESET_BUSY 0x04000000 215 | 100 101#define STE_DMACTL_RXDMA_STOPPED 0x00000001 102#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 103#define STE_DMACTL_TXDMA_STOPPED 0x00000004 104#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 105#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 106#define STE_DMACTL_RXDMA_STALL 0x00000100 107#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 --- 86 unchanged lines hidden (view full) --- 194#define STE_ASICCTL_FIFO_RESET 0x00100000 195#define STE_ASICCTL_NETWORK_RESET 0x00200000 196#define STE_ASICCTL_HOST_RESET 0x00400000 197#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 198#define STE_ASICCTL_EXTRESET_RESET 0x01000000 199#define STE_ASICCTL_SOFTINTR 0x02000000 200#define STE_ASICCTL_RESET_BUSY 0x04000000 201 |
| 202#define STE_ASICCTL1_GLOBAL_RESET 0x0001 203#define STE_ASICCTL1_RX_RESET 0x0002 204#define STE_ASICCTL1_TX_RESET 0x0004 205#define STE_ASICCTL1_DMA_RESET 0x0008 206#define STE_ASICCTL1_FIFO_RESET 0x0010 207#define STE_ASICCTL1_NETWORK_RESET 0x0020 208#define STE_ASICCTL1_HOST_RESET 0x0040 209#define STE_ASICCTL1_AUTOINIT_RESET 0x0080 210#define STE_ASICCTL1_EXTRESET_RESET 0x0100 211#define STE_ASICCTL1_SOFTINTR 0x0200 212#define STE_ASICCTL1_RESET_BUSY 0x0400 213 |
|
| 216#define STE_EECTL_ADDR 0x00FF 217#define STE_EECTL_OPCODE 0x0300 218#define STE_EECTL_BUSY 0x1000 219 220#define STE_EEOPCODE_WRITE 0x0100 221#define STE_EEOPCODE_READ 0x0200 222#define STE_EEOPCODE_ERASE 0x0300 223 --- 26 unchanged lines hidden (view full) --- 250 251#define STE_TXSTATUS_RECLAIMERR 0x02 252#define STE_TXSTATUS_STATSOFLOW 0x04 253#define STE_TXSTATUS_EXCESSCOLLS 0x08 254#define STE_TXSTATUS_UNDERRUN 0x10 255#define STE_TXSTATUS_TXINTR_REQ 0x40 256#define STE_TXSTATUS_TXDONE 0x80 257 | 214#define STE_EECTL_ADDR 0x00FF 215#define STE_EECTL_OPCODE 0x0300 216#define STE_EECTL_BUSY 0x1000 217 218#define STE_EEOPCODE_WRITE 0x0100 219#define STE_EEOPCODE_READ 0x0200 220#define STE_EEOPCODE_ERASE 0x0300 221 --- 26 unchanged lines hidden (view full) --- 248 249#define STE_TXSTATUS_RECLAIMERR 0x02 250#define STE_TXSTATUS_STATSOFLOW 0x04 251#define STE_TXSTATUS_EXCESSCOLLS 0x08 252#define STE_TXSTATUS_UNDERRUN 0x10 253#define STE_TXSTATUS_TXINTR_REQ 0x40 254#define STE_TXSTATUS_TXDONE 0x80 255 |
| 258#define STE_ERR_BITS "\20" \ 259 "\2RECLAIM\3STSOFLOW" \ 260 "\4EXCESSCOLLS\5UNDERRUN" \ 261 "\6INTREQ\7DONE" 262 | |
| 263#define STE_ISRACK_INTLATCH 0x0001 264#define STE_ISRACK_HOSTERR 0x0002 265#define STE_ISRACK_TX_DONE 0x0004 266#define STE_ISRACK_MACCTL_FRAME 0x0008 267#define STE_ISRACK_RX_DONE 0x0010 268#define STE_ISRACK_RX_EARLY 0x0020 269#define STE_ISRACK_SOFTINTR 0x0040 270#define STE_ISRACK_STATS_OFLOW 0x0080 --- 7 unchanged lines hidden (view full) --- 278#define STE_IMR_RX_DONE 0x0010 279#define STE_IMR_RX_EARLY 0x0020 280#define STE_IMR_SOFTINTR 0x0040 281#define STE_IMR_STATS_OFLOW 0x0080 282#define STE_IMR_LINKEVENT 0x0100 283#define STE_IMR_TX_DMADONE 0x0200 284#define STE_IMR_RX_DMADONE 0x0400 285 | 256#define STE_ISRACK_INTLATCH 0x0001 257#define STE_ISRACK_HOSTERR 0x0002 258#define STE_ISRACK_TX_DONE 0x0004 259#define STE_ISRACK_MACCTL_FRAME 0x0008 260#define STE_ISRACK_RX_DONE 0x0010 261#define STE_ISRACK_RX_EARLY 0x0020 262#define STE_ISRACK_SOFTINTR 0x0040 263#define STE_ISRACK_STATS_OFLOW 0x0080 --- 7 unchanged lines hidden (view full) --- 271#define STE_IMR_RX_DONE 0x0010 272#define STE_IMR_RX_EARLY 0x0020 273#define STE_IMR_SOFTINTR 0x0040 274#define STE_IMR_STATS_OFLOW 0x0080 275#define STE_IMR_LINKEVENT 0x0100 276#define STE_IMR_TX_DMADONE 0x0200 277#define STE_IMR_RX_DMADONE 0x0400 278 |
| 286#define STE_INTRS \ | 279#define STE_INTRS \ |
| 287 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ | 280 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ |
| 288 STE_IMR_TX_DONE|STE_IMR_SOFTINTR| \ 289 STE_IMR_HOSTERR) | 281 STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 282 STE_IMR_LINKEVENT) |
| 290 291#define STE_ISR_INTLATCH 0x0001 292#define STE_ISR_HOSTERR 0x0002 293#define STE_ISR_TX_DONE 0x0004 294#define STE_ISR_MACCTL_FRAME 0x0008 295#define STE_ISR_RX_DONE 0x0010 296#define STE_ISR_RX_EARLY 0x0020 297#define STE_ISR_SOFTINTR 0x0040 --- 47 unchanged lines hidden (view full) --- 345#define STE_PHYCTL_MDATA 0x02 346#define STE_PHYCTL_MDIR 0x04 347#define STE_PHYCTL_CLK25_DISABLE 0x08 348#define STE_PHYCTL_DUPLEXPOLARITY 0x10 349#define STE_PHYCTL_DUPLEXSTAT 0x20 350#define STE_PHYCTL_SPEEDSTAT 0x40 351#define STE_PHYCTL_LINKSTAT 0x80 352 | 283 284#define STE_ISR_INTLATCH 0x0001 285#define STE_ISR_HOSTERR 0x0002 286#define STE_ISR_TX_DONE 0x0004 287#define STE_ISR_MACCTL_FRAME 0x0008 288#define STE_ISR_RX_DONE 0x0010 289#define STE_ISR_RX_EARLY 0x0020 290#define STE_ISR_SOFTINTR 0x0040 --- 47 unchanged lines hidden (view full) --- 338#define STE_PHYCTL_MDATA 0x02 339#define STE_PHYCTL_MDIR 0x04 340#define STE_PHYCTL_CLK25_DISABLE 0x08 341#define STE_PHYCTL_DUPLEXPOLARITY 0x10 342#define STE_PHYCTL_DUPLEXSTAT 0x20 343#define STE_PHYCTL_SPEEDSTAT 0x40 344#define STE_PHYCTL_LINKSTAT 0x80 345 |
| 353#define STE_TIMER_TICKS 32 354#define STE_TIMER_USECS(x) ((x * 10) / STE_TIMER_TICKS) 355 356#define STE_IM_RX_TIMER_MIN 0 357#define STE_IM_RX_TIMER_MAX 209712 358#define STE_IM_RX_TIMER_DEFAULT 150 359 | |
| 360/* 361 * EEPROM offsets. 362 */ 363#define STE_EEADDR_CONFIGPARM 0x00 364#define STE_EEADDR_ASICCTL 0x02 365#define STE_EEADDR_SUBSYS_ID 0x04 366#define STE_EEADDR_SUBVEN_ID 0x08 367 --- 25 unchanged lines hidden (view full) --- 393#define STE_PSTATE_MASK 0x0003 394#define STE_PSTATE_D0 0x0000 395#define STE_PSTATE_D1 0x0002 396#define STE_PSTATE_D2 0x0002 397#define STE_PSTATE_D3 0x0003 398#define STE_PME_EN 0x0010 399#define STE_PME_STATUS 0x8000 400 | 346/* 347 * EEPROM offsets. 348 */ 349#define STE_EEADDR_CONFIGPARM 0x00 350#define STE_EEADDR_ASICCTL 0x02 351#define STE_EEADDR_SUBSYS_ID 0x04 352#define STE_EEADDR_SUBVEN_ID 0x08 353 --- 25 unchanged lines hidden (view full) --- 379#define STE_PSTATE_MASK 0x0003 380#define STE_PSTATE_D0 0x0000 381#define STE_PSTATE_D1 0x0002 382#define STE_PSTATE_D2 0x0002 383#define STE_PSTATE_D3 0x0003 384#define STE_PME_EN 0x0010 385#define STE_PME_STATUS 0x8000 386 |
| 401struct ste_hw_stats { 402 uint64_t rx_bytes; 403 uint32_t rx_frames; 404 uint32_t rx_bcast_frames; 405 uint32_t rx_mcast_frames; 406 uint32_t rx_lost_frames; 407 uint64_t tx_bytes; 408 uint32_t tx_frames; 409 uint32_t tx_bcast_frames; 410 uint32_t tx_mcast_frames; 411 uint32_t tx_carrsense_errs; 412 uint32_t tx_single_colls; 413 uint32_t tx_multi_colls; 414 uint32_t tx_late_colls; 415 uint32_t tx_frames_defered; 416 uint32_t tx_excess_defers; 417 uint32_t tx_abort; | 387 388struct ste_stats { 389 u_int32_t ste_rx_bytes; 390 u_int32_t ste_tx_bytes; 391 u_int16_t ste_tx_frames; 392 u_int16_t ste_rx_frames; 393 u_int8_t ste_carrsense_errs; 394 u_int8_t ste_late_colls; 395 u_int8_t ste_multi_colls; 396 u_int8_t ste_single_colls; 397 u_int8_t ste_tx_frames_defered; 398 u_int8_t ste_rx_lost_frames; 399 u_int8_t ste_tx_excess_defers; 400 u_int8_t ste_tx_abort_excess_colls; 401 u_int8_t ste_tx_bcast_frames; 402 u_int8_t ste_rx_bcast_frames; 403 u_int8_t ste_tx_mcast_frames; 404 u_int8_t ste_rx_mcast_frames; |
| 418}; 419 420struct ste_frag { | 405}; 406 407struct ste_frag { |
| 421 uint32_t ste_addr; 422 uint32_t ste_len; | 408 u_int32_t ste_addr; 409 u_int32_t ste_len; |
| 423}; 424 425#define STE_FRAG_LAST 0x80000000 426#define STE_FRAG_LEN 0x00001FFF 427 | 410}; 411 412#define STE_FRAG_LAST 0x80000000 413#define STE_FRAG_LEN 0x00001FFF 414 |
| 428/* 429 * A TFD is 16 to 512 bytes in length which means it can have up to 126 430 * fragments for a single Tx frame. Since most frames used in stack have 431 * 3-4 fragments supporting 8 fragments would be enough for normal 432 * operation. If we encounter more than 8 fragments we'll collapse them 433 * into a frame that has less than or equal to 8 fragments. Each buffer 434 * address of a fragment has no alignment limitation. 435 */ | |
| 436#define STE_MAXFRAGS 8 437 438struct ste_desc { | 415#define STE_MAXFRAGS 8 416 417struct ste_desc { |
| 439 uint32_t ste_next; 440 uint32_t ste_ctl; | 418 u_int32_t ste_next; 419 u_int32_t ste_ctl; |
| 441 struct ste_frag ste_frags[STE_MAXFRAGS]; 442}; 443 | 420 struct ste_frag ste_frags[STE_MAXFRAGS]; 421}; 422 |
| 444/* 445 * A RFD has the same structure of TFD which in turn means hardware 446 * supports scatter operation in Rx buffer. Since we just allocate Rx 447 * buffer with m_getcl(9) there is no fragmentation at all so use 448 * single fragment for RFD. 449 */ | |
| 450struct ste_desc_onefrag { | 423struct ste_desc_onefrag { |
| 451 uint32_t ste_next; 452 uint32_t ste_status; | 424 u_int32_t ste_next; 425 u_int32_t ste_status; |
| 453 struct ste_frag ste_frag; 454}; 455 456#define STE_TXCTL_WORDALIGN 0x00000003 | 426 struct ste_frag ste_frag; 427}; 428 429#define STE_TXCTL_WORDALIGN 0x00000003 |
| 457#define STE_TXCTL_ALIGN_DIS 0x00000001 | |
| 458#define STE_TXCTL_FRAMEID 0x000003FC 459#define STE_TXCTL_NOCRC 0x00002000 460#define STE_TXCTL_TXINTR 0x00008000 461#define STE_TXCTL_DMADONE 0x00010000 462#define STE_TXCTL_DMAINTR 0x80000000 463 464#define STE_RXSTAT_FRAMELEN 0x00001FFF 465#define STE_RXSTAT_FRAME_ERR 0x00004000 466#define STE_RXSTAT_DMADONE 0x00008000 467#define STE_RXSTAT_FIFO_OFLOW 0x00010000 468#define STE_RXSTAT_RUNT 0x00020000 469#define STE_RXSTAT_ALIGNERR 0x00040000 470#define STE_RXSTAT_CRCERR 0x00080000 471#define STE_RXSTAT_GIANT 0x00100000 472#define STE_RXSTAT_DRIBBLEBITS 0x00800000 473#define STE_RXSTAT_DMA_OFLOW 0x01000000 474#define STE_RXATAT_ONEBUF 0x10000000 475 | 430#define STE_TXCTL_FRAMEID 0x000003FC 431#define STE_TXCTL_NOCRC 0x00002000 432#define STE_TXCTL_TXINTR 0x00008000 433#define STE_TXCTL_DMADONE 0x00010000 434#define STE_TXCTL_DMAINTR 0x80000000 435 436#define STE_RXSTAT_FRAMELEN 0x00001FFF 437#define STE_RXSTAT_FRAME_ERR 0x00004000 438#define STE_RXSTAT_DMADONE 0x00008000 439#define STE_RXSTAT_FIFO_OFLOW 0x00010000 440#define STE_RXSTAT_RUNT 0x00020000 441#define STE_RXSTAT_ALIGNERR 0x00040000 442#define STE_RXSTAT_CRCERR 0x00080000 443#define STE_RXSTAT_GIANT 0x00100000 444#define STE_RXSTAT_DRIBBLEBITS 0x00800000 445#define STE_RXSTAT_DMA_OFLOW 0x01000000 446#define STE_RXATAT_ONEBUF 0x10000000 447 |
| 476#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN) 477 | |
| 478/* 479 * register space access macros 480 */ 481#define CSR_WRITE_4(sc, reg, val) \ | 448/* 449 * register space access macros 450 */ 451#define CSR_WRITE_4(sc, reg, val) \ |
| 482 bus_write_4((sc)->ste_res, reg, val) | 452 bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) |
| 483#define CSR_WRITE_2(sc, reg, val) \ | 453#define CSR_WRITE_2(sc, reg, val) \ |
| 484 bus_write_2((sc)->ste_res, reg, val) | 454 bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) |
| 485#define CSR_WRITE_1(sc, reg, val) \ | 455#define CSR_WRITE_1(sc, reg, val) \ |
| 486 bus_write_1((sc)->ste_res, reg, val) | 456 bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) |
| 487 488#define CSR_READ_4(sc, reg) \ | 457 458#define CSR_READ_4(sc, reg) \ |
| 489 bus_read_4((sc)->ste_res, reg) | 459 bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) |
| 490#define CSR_READ_2(sc, reg) \ | 460#define CSR_READ_2(sc, reg) \ |
| 491 bus_read_2((sc)->ste_res, reg) | 461 bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) |
| 492#define CSR_READ_1(sc, reg) \ | 462#define CSR_READ_1(sc, reg) \ |
| 493 bus_read_1((sc)->ste_res, reg) | 463 bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) |
| 494 | 464 |
| 495#define STE_DESC_ALIGN 8 496#define STE_RX_LIST_CNT 128 497#define STE_TX_LIST_CNT 128 498#define STE_RX_LIST_SZ \ 499 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT) 500#define STE_TX_LIST_SZ \ 501 (sizeof(struct ste_desc) * STE_TX_LIST_CNT) 502#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 503#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32) 504 505/* 506 * Since Tx status can hold up to 31 status bytes we should 507 * check Tx status before controller fills it up. Otherwise 508 * Tx MAC stalls. 509 */ 510#define STE_TX_INTR_FRAMES 16 511#define STE_TX_TIMEOUT 5 | |
| 512#define STE_TIMEOUT 1000 513#define STE_MIN_FRAMELEN 60 514#define STE_PACKET_SIZE 1536 | 465#define STE_TIMEOUT 1000 466#define STE_MIN_FRAMELEN 60 467#define STE_PACKET_SIZE 1536 |
| 468#define ETHER_ALIGN 2 469#define STE_RX_LIST_CNT 64 470#define STE_TX_LIST_CNT 128 |
|
| 515#define STE_INC(x, y) (x) = (x + 1) % y | 471#define STE_INC(x, y) (x) = (x + 1) % y |
| 516#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y) | |
| 517#define STE_NEXT(x, y) (x + 1) % y 518 519struct ste_type { | 472#define STE_NEXT(x, y) (x + 1) % y 473 474struct ste_type { |
| 520 uint16_t ste_vid; 521 uint16_t ste_did; | 475 u_int16_t ste_vid; 476 u_int16_t ste_did; |
| 522 char *ste_name; 523}; 524 525struct ste_list_data { | 477 char *ste_name; 478}; 479 480struct ste_list_data { |
| 526 struct ste_desc_onefrag *ste_rx_list; 527 bus_addr_t ste_rx_list_paddr; 528 struct ste_desc *ste_tx_list; 529 bus_addr_t ste_tx_list_paddr; | 481 struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 482 struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; |
| 530}; 531 532struct ste_chain { 533 struct ste_desc *ste_ptr; 534 struct mbuf *ste_mbuf; 535 struct ste_chain *ste_next; | 483}; 484 485struct ste_chain { 486 struct ste_desc *ste_ptr; 487 struct mbuf *ste_mbuf; 488 struct ste_chain *ste_next; |
| 536 uint32_t ste_phys; 537 bus_dmamap_t ste_map; | 489 u_int32_t ste_phys; |
| 538}; 539 540struct ste_chain_onefrag { 541 struct ste_desc_onefrag *ste_ptr; 542 struct mbuf *ste_mbuf; 543 struct ste_chain_onefrag *ste_next; | 490}; 491 492struct ste_chain_onefrag { 493 struct ste_desc_onefrag *ste_ptr; 494 struct mbuf *ste_mbuf; 495 struct ste_chain_onefrag *ste_next; |
| 544 bus_dmamap_t ste_map; | |
| 545}; 546 547struct ste_chain_data { | 496}; 497 498struct ste_chain_data { |
| 548 bus_dma_tag_t ste_parent_tag; 549 bus_dma_tag_t ste_rx_tag; 550 bus_dma_tag_t ste_tx_tag; 551 bus_dma_tag_t ste_rx_list_tag; 552 bus_dmamap_t ste_rx_list_map; 553 bus_dma_tag_t ste_tx_list_tag; 554 bus_dmamap_t ste_tx_list_map; 555 bus_dmamap_t ste_rx_sparemap; | |
| 556 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; | 499 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; |
| 557 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; | 500 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; |
| 558 struct ste_chain_onefrag *ste_rx_head; | 501 struct ste_chain_onefrag *ste_rx_head; |
| 559 struct ste_chain *ste_last_tx; | 502 |
| 560 int ste_tx_prod; 561 int ste_tx_cons; | 503 int ste_tx_prod; 504 int ste_tx_cons; |
| 562 int ste_tx_cnt; | |
| 563}; 564 565struct ste_softc { 566 struct ifnet *ste_ifp; | 505}; 506 507struct ste_softc { 508 struct ifnet *ste_ifp; |
| 509 bus_space_tag_t ste_btag; 510 bus_space_handle_t ste_bhandle; |
|
| 567 struct resource *ste_res; | 511 struct resource *ste_res; |
| 568 int ste_res_id; 569 int ste_res_type; | |
| 570 struct resource *ste_irq; 571 void *ste_intrhand; 572 struct ste_type *ste_info; 573 device_t ste_miibus; 574 device_t ste_dev; 575 int ste_tx_thresh; | 512 struct resource *ste_irq; 513 void *ste_intrhand; 514 struct ste_type *ste_info; 515 device_t ste_miibus; 516 device_t ste_dev; 517 int ste_tx_thresh; |
| 576 int ste_flags; 577#define STE_FLAG_ONE_PHY 0x0001 578#define STE_FLAG_LINK 0x8000 | 518 u_int8_t ste_link; |
| 579 int ste_if_flags; | 519 int ste_if_flags; |
| 580 int ste_timer; 581 int ste_int_rx_act; 582 int ste_int_rx_mod; 583 struct ste_list_data ste_ldata; | 520 struct ste_chain *ste_tx_prev; 521 struct ste_list_data *ste_ldata; |
| 584 struct ste_chain_data ste_cdata; | 522 struct ste_chain_data ste_cdata; |
| 585 struct callout ste_callout; 586 struct ste_hw_stats ste_stats; | 523 struct callout ste_stat_callout; |
| 587 struct mtx ste_mtx; | 524 struct mtx ste_mtx; |
| 525 u_int8_t ste_one_phy; 526#ifdef DEVICE_POLLING 527 int rxcycles; 528#endif |
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| 588}; 589 590#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 591#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 592#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 593 594struct ste_mii_frame { | 529}; 530 531#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 532#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 533#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 534 535struct ste_mii_frame { |
| 595 uint8_t mii_stdelim; 596 uint8_t mii_opcode; 597 uint8_t mii_phyaddr; 598 uint8_t mii_regaddr; 599 uint8_t mii_turnaround; 600 uint16_t mii_data; | 536 u_int8_t mii_stdelim; 537 u_int8_t mii_opcode; 538 u_int8_t mii_phyaddr; 539 u_int8_t mii_regaddr; 540 u_int8_t mii_turnaround; 541 u_int16_t mii_data; |
| 601}; 602 603/* 604 * MII constants 605 */ 606#define STE_MII_STARTDELIM 0x01 607#define STE_MII_READOP 0x02 608#define STE_MII_WRITEOP 0x01 609#define STE_MII_TURNAROUND 0x02 | 542}; 543 544/* 545 * MII constants 546 */ 547#define STE_MII_STARTDELIM 0x01 548#define STE_MII_READOP 0x02 549#define STE_MII_WRITEOP 0x01 550#define STE_MII_TURNAROUND 0x02 |