if_ste.c (e036acc008f9798df462877df467b3c9333cf3bc) if_ste.c (c8befdd5b608fa02cda3cdd4fe8b5a9eb87c6cad)
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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34__FBSDID("$FreeBSD$");
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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34__FBSDID("$FreeBSD$");
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_device_polling.h"
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/kernel.h>
45#include <sys/lock.h>
46#include <sys/malloc.h>
42#include <sys/sockio.h>
47#include <sys/mbuf.h>
43#include <sys/mbuf.h>
44#include <sys/malloc.h>
45#include <sys/kernel.h>
48#include <sys/module.h>
46#include <sys/module.h>
49#include <sys/rman.h>
50#include <sys/socket.h>
47#include <sys/socket.h>
51#include <sys/sockio.h>
52#include <sys/sysctl.h>
53
48#include <sys/sysctl.h>
49
54#include <net/bpf.h>
55#include <net/if.h>
56#include <net/if_arp.h>
57#include <net/ethernet.h>
58#include <net/if_dl.h>
59#include <net/if_media.h>
60#include <net/if_types.h>
61#include <net/if_vlan_var.h>
62
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/ethernet.h>
53#include <net/if_dl.h>
54#include <net/if_media.h>
55#include <net/if_types.h>
56#include <net/if_vlan_var.h>
57
58#include <net/bpf.h>
59
60#include <vm/vm.h> /* for vtophys */
61#include <vm/pmap.h> /* for vtophys */
63#include <machine/bus.h>
64#include <machine/resource.h>
62#include <machine/bus.h>
63#include <machine/resource.h>
64#include <sys/bus.h>
65#include <sys/rman.h>
65
66#include <dev/mii/mii.h>
67#include <dev/mii/miivar.h>
68
69#include <dev/pci/pcireg.h>
70#include <dev/pci/pcivar.h>
71
66
67#include <dev/mii/mii.h>
68#include <dev/mii/miivar.h>
69
70#include <dev/pci/pcireg.h>
71#include <dev/pci/pcivar.h>
72
72#include <dev/ste/if_stereg.h>
73
74/* "device miibus" required. See GENERIC if you get errors here. */
75#include "miibus_if.h"
76
73/* "device miibus" required. See GENERIC if you get errors here. */
74#include "miibus_if.h"
75
76#define STE_USEIOSPACE
77
78#include <dev/ste/if_stereg.h>
79
77MODULE_DEPEND(ste, pci, 1, 1, 1);
78MODULE_DEPEND(ste, ether, 1, 1, 1);
79MODULE_DEPEND(ste, miibus, 1, 1, 1);
80
80MODULE_DEPEND(ste, pci, 1, 1, 1);
81MODULE_DEPEND(ste, ether, 1, 1, 1);
82MODULE_DEPEND(ste, miibus, 1, 1, 1);
83
81/* Define to show Tx error status. */
82#define STE_SHOW_TXERRORS
83
84/*
85 * Various supported device vendors/types and their names.
86 */
87static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
91 { 0, 0, NULL }
92};
93
84/*
85 * Various supported device vendors/types and their names.
86 */
87static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
91 { 0, 0, NULL }
92};
93
94static int ste_attach(device_t);
95static int ste_detach(device_t);
96static int ste_probe(device_t);
97static int ste_resume(device_t);
98static int ste_shutdown(device_t);
99static int ste_suspend(device_t);
94static int ste_probe(device_t);
95static int ste_attach(device_t);
96static int ste_detach(device_t);
97static void ste_init(void *);
98static void ste_init_locked(struct ste_softc *);
99static void ste_intr(void *);
100static void ste_rxeoc(struct ste_softc *);
101static void ste_rxeof(struct ste_softc *);
102static void ste_txeoc(struct ste_softc *);
103static void ste_txeof(struct ste_softc *);
104static void ste_stats_update(void *);
105static void ste_stop(struct ste_softc *);
106static void ste_reset(struct ste_softc *);
107static int ste_ioctl(struct ifnet *, u_long, caddr_t);
108static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *);
109static void ste_start(struct ifnet *);
110static void ste_start_locked(struct ifnet *);
111static void ste_watchdog(struct ifnet *);
112static int ste_shutdown(device_t);
113static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *,
114 struct mbuf *);
115static int ste_ifmedia_upd(struct ifnet *);
116static void ste_ifmedia_upd_locked(struct ifnet *);
117static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
100
118
101static int ste_dma_alloc(struct ste_softc *);
102static void ste_dma_free(struct ste_softc *);
103static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
104static int ste_eeprom_wait(struct ste_softc *);
105static int ste_encap(struct ste_softc *, struct mbuf **,
106 struct ste_chain *);
107static int ste_ifmedia_upd(struct ifnet *);
108static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
109static void ste_init(void *);
110static void ste_init_locked(struct ste_softc *);
111static int ste_init_rx_list(struct ste_softc *);
112static void ste_init_tx_list(struct ste_softc *);
113static void ste_intr(void *);
114static int ste_ioctl(struct ifnet *, u_long, caddr_t);
115static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
116static void ste_mii_send(struct ste_softc *, uint32_t, int);
117static void ste_mii_sync(struct ste_softc *);
118static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
119static int ste_miibus_readreg(device_t, int, int);
120static void ste_miibus_statchg(device_t);
121static int ste_miibus_writereg(device_t, int, int, int);
122static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
123static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
124static void ste_reset(struct ste_softc *);
125static void ste_restart_tx(struct ste_softc *);
126static int ste_rxeof(struct ste_softc *, int);
127static void ste_rxfilter(struct ste_softc *);
128static void ste_setwol(struct ste_softc *);
129static void ste_start(struct ifnet *);
130static void ste_start_locked(struct ifnet *);
131static void ste_stats_clear(struct ste_softc *);
132static void ste_stats_update(struct ste_softc *);
133static void ste_stop(struct ste_softc *);
134static void ste_sysctl_node(struct ste_softc *);
135static void ste_tick(void *);
136static void ste_txeoc(struct ste_softc *);
137static void ste_txeof(struct ste_softc *);
138static void ste_wait(struct ste_softc *);
139static void ste_watchdog(struct ste_softc *);
119static void ste_mii_sync(struct ste_softc *);
120static void ste_mii_send(struct ste_softc *, u_int32_t, int);
121static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
122static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
123static int ste_miibus_readreg(device_t, int, int);
124static int ste_miibus_writereg(device_t, int, int, int);
125static void ste_miibus_statchg(device_t);
140
126
127static int ste_eeprom_wait(struct ste_softc *);
128static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int);
129static void ste_wait(struct ste_softc *);
130static void ste_setmulti(struct ste_softc *);
131static int ste_init_rx_list(struct ste_softc *);
132static void ste_init_tx_list(struct ste_softc *);
133
134#ifdef STE_USEIOSPACE
135#define STE_RES SYS_RES_IOPORT
136#define STE_RID STE_PCI_LOIO
137#else
138#define STE_RES SYS_RES_MEMORY
139#define STE_RID STE_PCI_LOMEM
140#endif
141
141static device_method_t ste_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, ste_probe),
144 DEVMETHOD(device_attach, ste_attach),
145 DEVMETHOD(device_detach, ste_detach),
146 DEVMETHOD(device_shutdown, ste_shutdown),
142static device_method_t ste_methods[] = {
143 /* Device interface */
144 DEVMETHOD(device_probe, ste_probe),
145 DEVMETHOD(device_attach, ste_attach),
146 DEVMETHOD(device_detach, ste_detach),
147 DEVMETHOD(device_shutdown, ste_shutdown),
147 DEVMETHOD(device_suspend, ste_suspend),
148 DEVMETHOD(device_resume, ste_resume),
149
150 /* bus interface */
151 DEVMETHOD(bus_print_child, bus_generic_print_child),
152 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
153
154 /* MII interface */
155 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
156 DEVMETHOD(miibus_writereg, ste_miibus_writereg),

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165 sizeof(struct ste_softc)
166};
167
168static devclass_t ste_devclass;
169
170DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
171DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
172
148
149 /* bus interface */
150 DEVMETHOD(bus_print_child, bus_generic_print_child),
151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
152
153 /* MII interface */
154 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
155 DEVMETHOD(miibus_writereg, ste_miibus_writereg),

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164 sizeof(struct ste_softc)
165};
166
167static devclass_t ste_devclass;
168
169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
171
172SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
173
174static int ste_rxsyncs;
175SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
176
173#define STE_SETBIT4(sc, reg, x) \
174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
175
176#define STE_CLRBIT4(sc, reg, x) \
177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
178
179#define STE_SETBIT2(sc, reg, x) \
180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

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185#define STE_SETBIT1(sc, reg, x) \
186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
187
188#define STE_CLRBIT1(sc, reg, x) \
189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
190
191
192#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
177#define STE_SETBIT4(sc, reg, x) \
178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
179
180#define STE_CLRBIT4(sc, reg, x) \
181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
182
183#define STE_SETBIT2(sc, reg, x) \
184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

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189#define STE_SETBIT1(sc, reg, x) \
190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
191
192#define STE_CLRBIT1(sc, reg, x) \
193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
194
195
196#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
193#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
197#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
194
195/*
196 * Sync the PHYs by setting data bit and strobing the clock 32 times.
197 */
198static void
198
199/*
200 * Sync the PHYs by setting data bit and strobing the clock 32 times.
201 */
202static void
199ste_mii_sync(struct ste_softc *sc)
203ste_mii_sync(sc)
204 struct ste_softc *sc;
200{
205{
201 int i;
206 register int i;
202
203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
204
205 for (i = 0; i < 32; i++) {
206 MII_SET(STE_PHYCTL_MCLK);
207 DELAY(1);
208 MII_CLR(STE_PHYCTL_MCLK);
209 DELAY(1);
210 }
207
208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
209
210 for (i = 0; i < 32; i++) {
211 MII_SET(STE_PHYCTL_MCLK);
212 DELAY(1);
213 MII_CLR(STE_PHYCTL_MCLK);
214 DELAY(1);
215 }
216
217 return;
211}
212
213/*
214 * Clock a series of bits through the MII.
215 */
216static void
218}
219
220/*
221 * Clock a series of bits through the MII.
222 */
223static void
217ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt)
224ste_mii_send(sc, bits, cnt)
225 struct ste_softc *sc;
226 u_int32_t bits;
227 int cnt;
218{
228{
219 int i;
229 int i;
220
221 MII_CLR(STE_PHYCTL_MCLK);
222
223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
224 if (bits & i) {
225 MII_SET(STE_PHYCTL_MDATA);
226 } else {
227 MII_CLR(STE_PHYCTL_MDATA);

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232 MII_SET(STE_PHYCTL_MCLK);
233 }
234}
235
236/*
237 * Read an PHY register through the MII.
238 */
239static int
230
231 MII_CLR(STE_PHYCTL_MCLK);
232
233 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
234 if (bits & i) {
235 MII_SET(STE_PHYCTL_MDATA);
236 } else {
237 MII_CLR(STE_PHYCTL_MDATA);

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242 MII_SET(STE_PHYCTL_MCLK);
243 }
244}
245
246/*
247 * Read an PHY register through the MII.
248 */
249static int
240ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame)
250ste_mii_readreg(sc, frame)
251 struct ste_softc *sc;
252 struct ste_mii_frame *frame;
253
241{
254{
242 int i, ack;
255 int i, ack;
243
244 /*
245 * Set up frame for RX.
246 */
247 frame->mii_stdelim = STE_MII_STARTDELIM;
248 frame->mii_opcode = STE_MII_READOP;
249 frame->mii_turnaround = 0;
250 frame->mii_data = 0;
256
257 /*
258 * Set up frame for RX.
259 */
260 frame->mii_stdelim = STE_MII_STARTDELIM;
261 frame->mii_opcode = STE_MII_READOP;
262 frame->mii_turnaround = 0;
263 frame->mii_data = 0;
251
264
252 CSR_WRITE_2(sc, STE_PHYCTL, 0);
253 /*
254 * Turn on data xmit.
255 */
256 MII_SET(STE_PHYCTL_MDIR);
257
258 ste_mii_sync(sc);
259

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281 MII_SET(STE_PHYCTL_MCLK);
282 DELAY(1);
283
284 /*
285 * Now try reading data bits. If the ack failed, we still
286 * need to clock through 16 cycles to keep the PHY(s) in sync.
287 */
288 if (ack) {
265 CSR_WRITE_2(sc, STE_PHYCTL, 0);
266 /*
267 * Turn on data xmit.
268 */
269 MII_SET(STE_PHYCTL_MDIR);
270
271 ste_mii_sync(sc);
272

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294 MII_SET(STE_PHYCTL_MCLK);
295 DELAY(1);
296
297 /*
298 * Now try reading data bits. If the ack failed, we still
299 * need to clock through 16 cycles to keep the PHY(s) in sync.
300 */
301 if (ack) {
289 for (i = 0; i < 16; i++) {
302 for(i = 0; i < 16; i++) {
290 MII_CLR(STE_PHYCTL_MCLK);
291 DELAY(1);
292 MII_SET(STE_PHYCTL_MCLK);
293 DELAY(1);
294 }
295 goto fail;
296 }
297

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310fail:
311
312 MII_CLR(STE_PHYCTL_MCLK);
313 DELAY(1);
314 MII_SET(STE_PHYCTL_MCLK);
315 DELAY(1);
316
317 if (ack)
303 MII_CLR(STE_PHYCTL_MCLK);
304 DELAY(1);
305 MII_SET(STE_PHYCTL_MCLK);
306 DELAY(1);
307 }
308 goto fail;
309 }
310

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323fail:
324
325 MII_CLR(STE_PHYCTL_MCLK);
326 DELAY(1);
327 MII_SET(STE_PHYCTL_MCLK);
328 DELAY(1);
329
330 if (ack)
318 return (1);
319 return (0);
331 return(1);
332 return(0);
320}
321
322/*
323 * Write to a PHY register through the MII.
324 */
325static int
333}
334
335/*
336 * Write to a PHY register through the MII.
337 */
338static int
326ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame)
339ste_mii_writereg(sc, frame)
340 struct ste_softc *sc;
341 struct ste_mii_frame *frame;
342
327{
328
329 /*
330 * Set up frame for TX.
331 */
332
333 frame->mii_stdelim = STE_MII_STARTDELIM;
334 frame->mii_opcode = STE_MII_WRITEOP;
335 frame->mii_turnaround = STE_MII_TURNAROUND;
343{
344
345 /*
346 * Set up frame for TX.
347 */
348
349 frame->mii_stdelim = STE_MII_STARTDELIM;
350 frame->mii_opcode = STE_MII_WRITEOP;
351 frame->mii_turnaround = STE_MII_TURNAROUND;
336
352
337 /*
338 * Turn on data output.
339 */
340 MII_SET(STE_PHYCTL_MDIR);
341
342 ste_mii_sync(sc);
343
344 ste_mii_send(sc, frame->mii_stdelim, 2);

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354 MII_CLR(STE_PHYCTL_MCLK);
355 DELAY(1);
356
357 /*
358 * Turn off xmit.
359 */
360 MII_CLR(STE_PHYCTL_MDIR);
361
353 /*
354 * Turn on data output.
355 */
356 MII_SET(STE_PHYCTL_MDIR);
357
358 ste_mii_sync(sc);
359
360 ste_mii_send(sc, frame->mii_stdelim, 2);

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370 MII_CLR(STE_PHYCTL_MCLK);
371 DELAY(1);
372
373 /*
374 * Turn off xmit.
375 */
376 MII_CLR(STE_PHYCTL_MDIR);
377
362 return (0);
378 return(0);
363}
364
365static int
379}
380
381static int
366ste_miibus_readreg(device_t dev, int phy, int reg)
382ste_miibus_readreg(dev, phy, reg)
383 device_t dev;
384 int phy, reg;
367{
385{
368 struct ste_softc *sc;
369 struct ste_mii_frame frame;
386 struct ste_softc *sc;
387 struct ste_mii_frame frame;
370
371 sc = device_get_softc(dev);
372
388
389 sc = device_get_softc(dev);
390
373 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0)
391 if ( sc->ste_one_phy && phy != 0 )
374 return (0);
375
376 bzero((char *)&frame, sizeof(frame));
377
378 frame.mii_phyaddr = phy;
379 frame.mii_regaddr = reg;
380 ste_mii_readreg(sc, &frame);
381
392 return (0);
393
394 bzero((char *)&frame, sizeof(frame));
395
396 frame.mii_phyaddr = phy;
397 frame.mii_regaddr = reg;
398 ste_mii_readreg(sc, &frame);
399
382 return (frame.mii_data);
400 return(frame.mii_data);
383}
384
385static int
401}
402
403static int
386ste_miibus_writereg(device_t dev, int phy, int reg, int data)
404ste_miibus_writereg(dev, phy, reg, data)
405 device_t dev;
406 int phy, reg, data;
387{
407{
388 struct ste_softc *sc;
389 struct ste_mii_frame frame;
408 struct ste_softc *sc;
409 struct ste_mii_frame frame;
390
391 sc = device_get_softc(dev);
392 bzero((char *)&frame, sizeof(frame));
393
394 frame.mii_phyaddr = phy;
395 frame.mii_regaddr = reg;
396 frame.mii_data = data;
397
398 ste_mii_writereg(sc, &frame);
399
410
411 sc = device_get_softc(dev);
412 bzero((char *)&frame, sizeof(frame));
413
414 frame.mii_phyaddr = phy;
415 frame.mii_regaddr = reg;
416 frame.mii_data = data;
417
418 ste_mii_writereg(sc, &frame);
419
400 return (0);
420 return(0);
401}
402
403static void
421}
422
423static void
404ste_miibus_statchg(device_t dev)
424ste_miibus_statchg(dev)
425 device_t dev;
405{
426{
406 struct ste_softc *sc;
407 struct mii_data *mii;
408 struct ifnet *ifp;
409 uint16_t cfg;
427 struct ste_softc *sc;
428 struct mii_data *mii;
410
411 sc = device_get_softc(dev);
412
413 mii = device_get_softc(sc->ste_miibus);
429
430 sc = device_get_softc(dev);
431
432 mii = device_get_softc(sc->ste_miibus);
414 ifp = sc->ste_ifp;
415 if (mii == NULL || ifp == NULL ||
416 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
417 return;
418
433
419 sc->ste_flags &= ~STE_FLAG_LINK;
420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
421 (IFM_ACTIVE | IFM_AVALID)) {
422 switch (IFM_SUBTYPE(mii->mii_media_active)) {
423 case IFM_10_T:
424 case IFM_100_TX:
425 case IFM_100_FX:
426 case IFM_100_T4:
427 sc->ste_flags |= STE_FLAG_LINK;
428 default:
429 break;
430 }
434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
436 } else {
437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
431 }
432
438 }
439
433 /* Program MACs with resolved speed/duplex/flow-control. */
434 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
435 cfg = CSR_READ_2(sc, STE_MACCTL0);
436 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
437 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
438 /*
439 * ST201 data sheet says driver should enable receiving
440 * MAC control frames bit of receive mode register to
441 * receive flow-control frames but the register has no
442 * such bits. In addition the controller has no ability
443 * to send pause frames so it should be handled in
444 * driver. Implementing pause timer handling in driver
445 * layer is not trivial, so don't enable flow-control
446 * here.
447 */
448 cfg |= STE_MACCTL0_FULLDUPLEX;
449 }
450 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
451 }
440 return;
452}
441}
453
442
454static int
443static int
455ste_ifmedia_upd(struct ifnet *ifp)
444ste_ifmedia_upd(ifp)
445 struct ifnet *ifp;
456{
446{
457 struct ste_softc *sc;
458 struct mii_data *mii;
459 struct mii_softc *miisc;
460 int error;
447 struct ste_softc *sc;
461
462 sc = ifp->if_softc;
463 STE_LOCK(sc);
448
449 sc = ifp->if_softc;
450 STE_LOCK(sc);
451 ste_ifmedia_upd_locked(ifp);
452 STE_UNLOCK(sc);
453
454 return(0);
455}
456
457static void
458ste_ifmedia_upd_locked(ifp)
459 struct ifnet *ifp;
460{
461 struct ste_softc *sc;
462 struct mii_data *mii;
463
464 sc = ifp->if_softc;
465 STE_LOCK_ASSERT(sc);
464 mii = device_get_softc(sc->ste_miibus);
466 mii = device_get_softc(sc->ste_miibus);
467 sc->ste_link = 0;
465 if (mii->mii_instance) {
468 if (mii->mii_instance) {
469 struct mii_softc *miisc;
466 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
467 mii_phy_reset(miisc);
468 }
470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
471 mii_phy_reset(miisc);
472 }
469 error = mii_mediachg(mii);
470 STE_UNLOCK(sc);
471
472 return (error);
473 mii_mediachg(mii);
473}
474
475static void
474}
475
476static void
476ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
477ste_ifmedia_sts(ifp, ifmr)
478 struct ifnet *ifp;
479 struct ifmediareq *ifmr;
477{
480{
478 struct ste_softc *sc;
479 struct mii_data *mii;
481 struct ste_softc *sc;
482 struct mii_data *mii;
480
481 sc = ifp->if_softc;
482 mii = device_get_softc(sc->ste_miibus);
483
484 STE_LOCK(sc);
483
484 sc = ifp->if_softc;
485 mii = device_get_softc(sc->ste_miibus);
486
487 STE_LOCK(sc);
485 if ((ifp->if_flags & IFF_UP) == 0) {
486 STE_UNLOCK(sc);
487 return;
488 }
489 mii_pollstat(mii);
490 ifmr->ifm_active = mii->mii_media_active;
491 ifmr->ifm_status = mii->mii_media_status;
492 STE_UNLOCK(sc);
488 mii_pollstat(mii);
489 ifmr->ifm_active = mii->mii_media_active;
490 ifmr->ifm_status = mii->mii_media_status;
491 STE_UNLOCK(sc);
492
493 return;
493}
494
495static void
494}
495
496static void
496ste_wait(struct ste_softc *sc)
497ste_wait(sc)
498 struct ste_softc *sc;
497{
499{
498 int i;
500 register int i;
499
500 for (i = 0; i < STE_TIMEOUT; i++) {
501 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
502 break;
501
502 for (i = 0; i < STE_TIMEOUT; i++) {
503 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
504 break;
503 DELAY(1);
504 }
505
506 if (i == STE_TIMEOUT)
507 device_printf(sc->ste_dev, "command never completed!\n");
505 }
506
507 if (i == STE_TIMEOUT)
508 device_printf(sc->ste_dev, "command never completed!\n");
509
510 return;
508}
509
510/*
511 * The EEPROM is slow: give it time to come ready after issuing
512 * it a command.
513 */
514static int
511}
512
513/*
514 * The EEPROM is slow: give it time to come ready after issuing
515 * it a command.
516 */
517static int
515ste_eeprom_wait(struct ste_softc *sc)
518ste_eeprom_wait(sc)
519 struct ste_softc *sc;
516{
520{
517 int i;
521 int i;
518
519 DELAY(1000);
520
521 for (i = 0; i < 100; i++) {
522 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
523 DELAY(1000);
524 else
525 break;
526 }
527
528 if (i == 100) {
529 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
522
523 DELAY(1000);
524
525 for (i = 0; i < 100; i++) {
526 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
527 DELAY(1000);
528 else
529 break;
530 }
531
532 if (i == 100) {
533 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
530 return (1);
534 return(1);
531 }
532
535 }
536
533 return (0);
537 return(0);
534}
535
536/*
537 * Read a sequence of words from the EEPROM. Note that ethernet address
538 * data is stored in the EEPROM in network byte order.
539 */
540static int
538}
539
540/*
541 * Read a sequence of words from the EEPROM. Note that ethernet address
542 * data is stored in the EEPROM in network byte order.
543 */
544static int
541ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
545ste_read_eeprom(sc, dest, off, cnt, swap)
546 struct ste_softc *sc;
547 caddr_t dest;
548 int off;
549 int cnt;
550 int swap;
542{
551{
543 int err = 0, i;
552 int err = 0, i;
553 u_int16_t word = 0, *ptr;
544
545 if (ste_eeprom_wait(sc))
554
555 if (ste_eeprom_wait(sc))
546 return (1);
556 return(1);
547
548 for (i = 0; i < cnt; i++) {
549 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
550 err = ste_eeprom_wait(sc);
551 if (err)
552 break;
557
558 for (i = 0; i < cnt; i++) {
559 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
560 err = ste_eeprom_wait(sc);
561 if (err)
562 break;
553 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
554 dest++;
563 word = CSR_READ_2(sc, STE_EEPROM_DATA);
564 ptr = (u_int16_t *)(dest + (i * 2));
565 if (swap)
566 *ptr = ntohs(word);
567 else
568 *ptr = word;
555 }
556
569 }
570
557 return (err ? 1 : 0);
571 return(err ? 1 : 0);
558}
559
560static void
572}
573
574static void
561ste_rxfilter(struct ste_softc *sc)
575ste_setmulti(sc)
576 struct ste_softc *sc;
562{
577{
563 struct ifnet *ifp;
564 struct ifmultiaddr *ifma;
565 uint32_t hashes[2] = { 0, 0 };
566 uint8_t rxcfg;
567 int h;
578 struct ifnet *ifp;
579 int h = 0;
580 u_int32_t hashes[2] = { 0, 0 };
581 struct ifmultiaddr *ifma;
568
582
569 STE_LOCK_ASSERT(sc);
570
571 ifp = sc->ste_ifp;
583 ifp = sc->ste_ifp;
572 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
573 rxcfg |= STE_RXMODE_UNICAST;
574 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
575 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
576 if (ifp->if_flags & IFF_BROADCAST)
577 rxcfg |= STE_RXMODE_BROADCAST;
578 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
579 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
580 rxcfg |= STE_RXMODE_ALLMULTI;
581 if ((ifp->if_flags & IFF_PROMISC) != 0)
582 rxcfg |= STE_RXMODE_PROMISC;
583 goto chipit;
584 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
585 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
586 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
587 return;
584 }
585
588 }
589
586 rxcfg |= STE_RXMODE_MULTIHASH;
587 /* Now program new ones. */
588 if_maddr_rlock(ifp);
590 /* first, zot all the existing hash bits */
591 CSR_WRITE_2(sc, STE_MAR0, 0);
592 CSR_WRITE_2(sc, STE_MAR1, 0);
593 CSR_WRITE_2(sc, STE_MAR2, 0);
594 CSR_WRITE_2(sc, STE_MAR3, 0);
595
596 /* now program new ones */
597 IF_ADDR_LOCK(ifp);
589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
590 if (ifma->ifma_addr->sa_family != AF_LINK)
591 continue;
592 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
593 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
594 if (h < 32)
595 hashes[0] |= (1 << h);
596 else
597 hashes[1] |= (1 << (h - 32));
598 }
598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
599 if (ifma->ifma_addr->sa_family != AF_LINK)
600 continue;
601 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
602 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
603 if (h < 32)
604 hashes[0] |= (1 << h);
605 else
606 hashes[1] |= (1 << (h - 32));
607 }
599 if_maddr_runlock(ifp);
608 IF_ADDR_UNLOCK(ifp);
600
609
601chipit:
602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
610 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
611 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
612 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
613 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
606 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
607 CSR_READ_1(sc, STE_RX_MODE);
614 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
615 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
616
617 return;
608}
609
610#ifdef DEVICE_POLLING
611static poll_handler_t ste_poll, ste_poll_locked;
612
618}
619
620#ifdef DEVICE_POLLING
621static poll_handler_t ste_poll, ste_poll_locked;
622
613static int
623static void
614ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
615{
616 struct ste_softc *sc = ifp->if_softc;
624ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
625{
626 struct ste_softc *sc = ifp->if_softc;
617 int rx_npkts = 0;
618
619 STE_LOCK(sc);
620 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
627
628 STE_LOCK(sc);
629 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
621 rx_npkts = ste_poll_locked(ifp, cmd, count);
630 ste_poll_locked(ifp, cmd, count);
622 STE_UNLOCK(sc);
631 STE_UNLOCK(sc);
623 return (rx_npkts);
624}
625
632}
633
626static int
634static void
627ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
628{
629 struct ste_softc *sc = ifp->if_softc;
635ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
636{
637 struct ste_softc *sc = ifp->if_softc;
630 int rx_npkts;
631
632 STE_LOCK_ASSERT(sc);
633
638
639 STE_LOCK_ASSERT(sc);
640
634 rx_npkts = ste_rxeof(sc, count);
641 sc->rxcycles = count;
642 if (cmd == POLL_AND_CHECK_STATUS)
643 ste_rxeoc(sc);
644 ste_rxeof(sc);
635 ste_txeof(sc);
645 ste_txeof(sc);
636 ste_txeoc(sc);
637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
638 ste_start_locked(ifp);
639
640 if (cmd == POLL_AND_CHECK_STATUS) {
646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
647 ste_start_locked(ifp);
648
649 if (cmd == POLL_AND_CHECK_STATUS) {
641 uint16_t status;
650 u_int16_t status;
642
643 status = CSR_READ_2(sc, STE_ISR_ACK);
644
651
652 status = CSR_READ_2(sc, STE_ISR_ACK);
653
645 if (status & STE_ISR_STATS_OFLOW)
654 if (status & STE_ISR_TX_DONE)
655 ste_txeoc(sc);
656
657 if (status & STE_ISR_STATS_OFLOW) {
658 callout_stop(&sc->ste_stat_callout);
646 ste_stats_update(sc);
659 ste_stats_update(sc);
660 }
647
661
662 if (status & STE_ISR_LINKEVENT)
663 mii_pollstat(device_get_softc(sc->ste_miibus));
664
648 if (status & STE_ISR_HOSTERR) {
665 if (status & STE_ISR_HOSTERR) {
649 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
666 ste_reset(sc);
650 ste_init_locked(sc);
651 }
652 }
667 ste_init_locked(sc);
668 }
669 }
653 return (rx_npkts);
654}
655#endif /* DEVICE_POLLING */
656
657static void
670}
671#endif /* DEVICE_POLLING */
672
673static void
658ste_intr(void *xsc)
674ste_intr(xsc)
675 void *xsc;
659{
676{
660 struct ste_softc *sc;
661 struct ifnet *ifp;
662 uint16_t intrs, status;
677 struct ste_softc *sc;
678 struct ifnet *ifp;
679 u_int16_t status;
663
664 sc = xsc;
665 STE_LOCK(sc);
666 ifp = sc->ste_ifp;
667
668#ifdef DEVICE_POLLING
669 if (ifp->if_capenable & IFCAP_POLLING) {
670 STE_UNLOCK(sc);
671 return;
672 }
673#endif
680
681 sc = xsc;
682 STE_LOCK(sc);
683 ifp = sc->ste_ifp;
684
685#ifdef DEVICE_POLLING
686 if (ifp->if_capenable & IFCAP_POLLING) {
687 STE_UNLOCK(sc);
688 return;
689 }
690#endif
674 /* Reading STE_ISR_ACK clears STE_IMR register. */
675 status = CSR_READ_2(sc, STE_ISR_ACK);
676 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
691
692 /* See if this is really our interrupt. */
693 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
677 STE_UNLOCK(sc);
678 return;
679 }
680
694 STE_UNLOCK(sc);
695 return;
696 }
697
681 intrs = STE_INTRS;
682 if (status == 0xFFFF || (status & intrs) == 0)
683 goto done;
698 for (;;) {
699 status = CSR_READ_2(sc, STE_ISR_ACK);
684
700
685 if (sc->ste_int_rx_act > 0) {
686 status &= ~STE_ISR_RX_DMADONE;
687 intrs &= ~STE_IMR_RX_DMADONE;
688 }
701 if (!(status & STE_INTRS))
702 break;
689
703
690 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
691 ste_rxeof(sc, -1);
692 /*
693 * The controller has no ability to Rx interrupt
694 * moderation feature. Receiving 64 bytes frames
695 * from wire generates too many interrupts which in
696 * turn make system useless to process other useful
697 * things. Fortunately ST201 supports single shot
698 * timer so use the timer to implement Rx interrupt
699 * moderation in driver. This adds more register
700 * access but it greatly reduces number of Rx
701 * interrupts under high network load.
702 */
703 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
704 (sc->ste_int_rx_mod != 0)) {
705 if ((status & STE_ISR_RX_DMADONE) != 0) {
706 CSR_WRITE_2(sc, STE_COUNTDOWN,
707 STE_TIMER_USECS(sc->ste_int_rx_mod));
708 intrs &= ~STE_IMR_RX_DMADONE;
709 sc->ste_int_rx_act = 1;
710 } else {
711 intrs |= STE_IMR_RX_DMADONE;
712 sc->ste_int_rx_act = 0;
713 }
704 if (status & STE_ISR_RX_DMADONE) {
705 ste_rxeoc(sc);
706 ste_rxeof(sc);
714 }
707 }
715 }
716 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
717 if ((status & STE_ISR_TX_DMADONE) != 0)
708
709 if (status & STE_ISR_TX_DMADONE)
718 ste_txeof(sc);
710 ste_txeof(sc);
719 if ((status & STE_ISR_TX_DONE) != 0)
711
712 if (status & STE_ISR_TX_DONE)
720 ste_txeoc(sc);
713 ste_txeoc(sc);
721 if ((status & STE_ISR_STATS_OFLOW) != 0)
714
715 if (status & STE_ISR_STATS_OFLOW) {
716 callout_stop(&sc->ste_stat_callout);
722 ste_stats_update(sc);
717 ste_stats_update(sc);
723 if ((status & STE_ISR_HOSTERR) != 0) {
724 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
718 }
719
720 if (status & STE_ISR_LINKEVENT)
721 mii_pollstat(device_get_softc(sc->ste_miibus));
722
723
724 if (status & STE_ISR_HOSTERR) {
725 ste_reset(sc);
725 ste_init_locked(sc);
726 ste_init_locked(sc);
726 STE_UNLOCK(sc);
727 return;
728 }
727 }
729 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
730 ste_start_locked(ifp);
731done:
732 /* Re-enable interrupts */
733 CSR_WRITE_2(sc, STE_IMR, intrs);
734 }
728 }
729
730 /* Re-enable interrupts */
731 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
732
733 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
734 ste_start_locked(ifp);
735
735 STE_UNLOCK(sc);
736 STE_UNLOCK(sc);
737
738 return;
736}
737
739}
740
741static void
742ste_rxeoc(struct ste_softc *sc)
743{
744 struct ste_chain_onefrag *cur_rx;
745
746 STE_LOCK_ASSERT(sc);
747
748 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
749 cur_rx = sc->ste_cdata.ste_rx_head;
750 do {
751 cur_rx = cur_rx->ste_next;
752 /* If the ring is empty, just return. */
753 if (cur_rx == sc->ste_cdata.ste_rx_head)
754 return;
755 } while (cur_rx->ste_ptr->ste_status == 0);
756 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
757 /* We've fallen behind the chip: catch it. */
758 sc->ste_cdata.ste_rx_head = cur_rx;
759 ++ste_rxsyncs;
760 }
761 }
762}
763
738/*
739 * A frame has been uploaded: pass the resulting mbuf chain up to
740 * the higher level protocols.
741 */
764/*
765 * A frame has been uploaded: pass the resulting mbuf chain up to
766 * the higher level protocols.
767 */
742static int
743ste_rxeof(struct ste_softc *sc, int count)
768static void
769ste_rxeof(sc)
770 struct ste_softc *sc;
744{
771{
745 struct mbuf *m;
746 struct ifnet *ifp;
747 struct ste_chain_onefrag *cur_rx;
748 uint32_t rxstat;
749 int total_len, rx_npkts;
772 struct mbuf *m;
773 struct ifnet *ifp;
774 struct ste_chain_onefrag *cur_rx;
775 int total_len = 0, count=0;
776 u_int32_t rxstat;
750
777
778 STE_LOCK_ASSERT(sc);
779
751 ifp = sc->ste_ifp;
752
780 ifp = sc->ste_ifp;
781
753 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
754 sc->ste_cdata.ste_rx_list_map,
755 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
756
757 cur_rx = sc->ste_cdata.ste_rx_head;
758 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
759 cur_rx = cur_rx->ste_next) {
760 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
761 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
762 break;
782 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
783 & STE_RXSTAT_DMADONE) {
763#ifdef DEVICE_POLLING
764 if (ifp->if_capenable & IFCAP_POLLING) {
784#ifdef DEVICE_POLLING
785 if (ifp->if_capenable & IFCAP_POLLING) {
765 if (count == 0)
786 if (sc->rxcycles <= 0)
766 break;
787 break;
767 count--;
788 sc->rxcycles--;
768 }
769#endif
789 }
790#endif
770 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
791 if ((STE_RX_LIST_CNT - count) < 3) {
771 break;
792 break;
793 }
794
795 cur_rx = sc->ste_cdata.ste_rx_head;
796 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
797
772 /*
773 * If an error occurs, update stats, clear the
774 * status word and leave the mbuf cluster in place:
775 * it should simply get re-used next time this descriptor
776 * comes up in the ring.
777 */
778 if (rxstat & STE_RXSTAT_FRAME_ERR) {
779 ifp->if_ierrors++;
780 cur_rx->ste_ptr->ste_status = 0;
781 continue;
782 }
783
798 /*
799 * If an error occurs, update stats, clear the
800 * status word and leave the mbuf cluster in place:
801 * it should simply get re-used next time this descriptor
802 * comes up in the ring.
803 */
804 if (rxstat & STE_RXSTAT_FRAME_ERR) {
805 ifp->if_ierrors++;
806 cur_rx->ste_ptr->ste_status = 0;
807 continue;
808 }
809
784 /* No errors; receive the packet. */
810 /*
811 * If there error bit was not set, the upload complete
812 * bit should be set which means we have a valid packet.
813 * If not, something truly strange has happened.
814 */
815 if (!(rxstat & STE_RXSTAT_DMADONE)) {
816 device_printf(sc->ste_dev,
817 "bad receive status -- packet dropped\n");
818 ifp->if_ierrors++;
819 cur_rx->ste_ptr->ste_status = 0;
820 continue;
821 }
822
823 /* No errors; receive the packet. */
785 m = cur_rx->ste_mbuf;
824 m = cur_rx->ste_mbuf;
786 total_len = STE_RX_BYTES(rxstat);
825 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
787
788 /*
789 * Try to conjure up a new mbuf cluster. If that
790 * fails, it means we have an out of memory condition and
791 * should leave the buffer in place and continue. This will
792 * result in a lost packet, but there's little else we
793 * can do in this situation.
794 */
826
827 /*
828 * Try to conjure up a new mbuf cluster. If that
829 * fails, it means we have an out of memory condition and
830 * should leave the buffer in place and continue. This will
831 * result in a lost packet, but there's little else we
832 * can do in this situation.
833 */
795 if (ste_newbuf(sc, cur_rx) != 0) {
796 ifp->if_iqdrops++;
834 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
835 ifp->if_ierrors++;
797 cur_rx->ste_ptr->ste_status = 0;
798 continue;
799 }
800
801 m->m_pkthdr.rcvif = ifp;
802 m->m_pkthdr.len = m->m_len = total_len;
803
804 ifp->if_ipackets++;
805 STE_UNLOCK(sc);
806 (*ifp->if_input)(ifp, m);
807 STE_LOCK(sc);
836 cur_rx->ste_ptr->ste_status = 0;
837 continue;
838 }
839
840 m->m_pkthdr.rcvif = ifp;
841 m->m_pkthdr.len = m->m_len = total_len;
842
843 ifp->if_ipackets++;
844 STE_UNLOCK(sc);
845 (*ifp->if_input)(ifp, m);
846 STE_LOCK(sc);
808 }
809
847
810 if (rx_npkts > 0) {
811 sc->ste_cdata.ste_rx_head = cur_rx;
812 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
813 sc->ste_cdata.ste_rx_list_map,
814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
848 cur_rx->ste_ptr->ste_status = 0;
849 count++;
815 }
816
850 }
851
817 return (rx_npkts);
852 return;
818}
819
820static void
853}
854
855static void
821ste_txeoc(struct ste_softc *sc)
856ste_txeoc(sc)
857 struct ste_softc *sc;
822{
858{
823 uint16_t txstat;
824 struct ifnet *ifp;
859 u_int8_t txstat;
860 struct ifnet *ifp;
825
861
826 STE_LOCK_ASSERT(sc);
827
828 ifp = sc->ste_ifp;
829
862 ifp = sc->ste_ifp;
863
830 /*
831 * STE_TX_STATUS register implements a queue of up to 31
832 * transmit status byte. Writing an arbitrary value to the
833 * register will advance the queue to the next transmit
834 * status byte. This means if driver does not read
835 * STE_TX_STATUS register after completing sending more
836 * than 31 frames the controller would be stalled so driver
837 * should re-wake the Tx MAC. This is the most severe
838 * limitation of ST201 based controller.
839 */
840 for (;;) {
841 txstat = CSR_READ_2(sc, STE_TX_STATUS);
842 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
843 break;
844 if ((txstat & (STE_TXSTATUS_UNDERRUN |
845 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
846 STE_TXSTATUS_STATSOFLOW)) != 0) {
864 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
865 STE_TXSTATUS_TXDONE) {
866 if (txstat & STE_TXSTATUS_UNDERRUN ||
867 txstat & STE_TXSTATUS_EXCESSCOLLS ||
868 txstat & STE_TXSTATUS_RECLAIMERR) {
847 ifp->if_oerrors++;
869 ifp->if_oerrors++;
848#ifdef STE_SHOW_TXERRORS
849 device_printf(sc->ste_dev, "TX error : 0x%b\n",
850 txstat & 0xFF, STE_ERR_BITS);
851#endif
852 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
870 device_printf(sc->ste_dev,
871 "transmission error: %x\n", txstat);
872
873 ste_reset(sc);
874 ste_init_locked(sc);
875
876 if (txstat & STE_TXSTATUS_UNDERRUN &&
853 sc->ste_tx_thresh < STE_PACKET_SIZE) {
854 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
877 sc->ste_tx_thresh < STE_PACKET_SIZE) {
878 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
855 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
856 sc->ste_tx_thresh = STE_PACKET_SIZE;
857 device_printf(sc->ste_dev,
879 device_printf(sc->ste_dev,
858 "TX underrun, increasing TX"
880 "tx underrun, increasing tx"
859 " start threshold to %d bytes\n",
860 sc->ste_tx_thresh);
881 " start threshold to %d bytes\n",
882 sc->ste_tx_thresh);
861 /* Make sure to disable active DMA cycles. */
862 STE_SETBIT4(sc, STE_DMACTL,
863 STE_DMACTL_TXDMA_STALL);
864 ste_wait(sc);
865 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
866 ste_init_locked(sc);
867 break;
868 }
883 }
869 /* Restart Tx. */
870 ste_restart_tx(sc);
884 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
885 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
886 (STE_PACKET_SIZE >> 4));
871 }
887 }
872 /*
873 * Advance to next status and ACK TxComplete
874 * interrupt. ST201 data sheet was wrong here, to
875 * get next Tx status, we have to write both
876 * STE_TX_STATUS and STE_TX_FRAMEID register.
877 * Otherwise controller returns the same status
878 * as well as not acknowledge Tx completion
879 * interrupt.
880 */
888 ste_init_locked(sc);
881 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
882 }
889 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
890 }
883}
884
891
885static void
886ste_tick(void *arg)
887{
888 struct ste_softc *sc;
889 struct mii_data *mii;
890
891 sc = (struct ste_softc *)arg;
892
893 STE_LOCK_ASSERT(sc);
894
895 mii = device_get_softc(sc->ste_miibus);
896 mii_tick(mii);
897 /*
898 * ukphy(4) does not seem to generate CB that reports
899 * resolved link state so if we know we lost a link,
900 * explicitly check the link state.
901 */
902 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
903 ste_miibus_statchg(sc->ste_dev);
904 /*
905 * Because we are not generating Tx completion
906 * interrupt for every frame, reclaim transmitted
907 * buffers here.
908 */
909 ste_txeof(sc);
910 ste_txeoc(sc);
911 ste_stats_update(sc);
912 ste_watchdog(sc);
913 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
892 return;
914}
915
916static void
893}
894
895static void
917ste_txeof(struct ste_softc *sc)
896ste_txeof(sc)
897 struct ste_softc *sc;
918{
898{
919 struct ifnet *ifp;
920 struct ste_chain *cur_tx;
921 uint32_t txstat;
922 int idx;
899 struct ste_chain *cur_tx;
900 struct ifnet *ifp;
901 int idx;
923
902
924 STE_LOCK_ASSERT(sc);
925
926 ifp = sc->ste_ifp;
903 ifp = sc->ste_ifp;
927 idx = sc->ste_cdata.ste_tx_cons;
928 if (idx == sc->ste_cdata.ste_tx_prod)
929 return;
930
904
931 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
932 sc->ste_cdata.ste_tx_list_map,
933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
934
935 while (idx != sc->ste_cdata.ste_tx_prod) {
905 idx = sc->ste_cdata.ste_tx_cons;
906 while(idx != sc->ste_cdata.ste_tx_prod) {
936 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
907 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
937 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
938 if ((txstat & STE_TXCTL_DMADONE) == 0)
908
909 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
939 break;
910 break;
940 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
941 BUS_DMASYNC_POSTWRITE);
942 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
943 KASSERT(cur_tx->ste_mbuf != NULL,
944 ("%s: freeing NULL mbuf!\n", __func__));
911
945 m_freem(cur_tx->ste_mbuf);
946 cur_tx->ste_mbuf = NULL;
947 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
948 ifp->if_opackets++;
912 m_freem(cur_tx->ste_mbuf);
913 cur_tx->ste_mbuf = NULL;
914 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
915 ifp->if_opackets++;
949 sc->ste_cdata.ste_tx_cnt--;
916
950 STE_INC(idx, STE_TX_LIST_CNT);
951 }
952
953 sc->ste_cdata.ste_tx_cons = idx;
917 STE_INC(idx, STE_TX_LIST_CNT);
918 }
919
920 sc->ste_cdata.ste_tx_cons = idx;
954 if (sc->ste_cdata.ste_tx_cnt == 0)
955 sc->ste_timer = 0;
921 if (idx == sc->ste_cdata.ste_tx_prod)
922 ifp->if_timer = 0;
956}
957
958static void
923}
924
925static void
959ste_stats_clear(struct ste_softc *sc)
926ste_stats_update(xsc)
927 void *xsc;
960{
928{
929 struct ste_softc *sc;
930 struct ifnet *ifp;
931 struct mii_data *mii;
961
932
933 sc = xsc;
962 STE_LOCK_ASSERT(sc);
963
934 STE_LOCK_ASSERT(sc);
935
964 /* Rx stats. */
965 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
966 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
967 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
968 CSR_READ_1(sc, STE_STAT_RX_BCAST);
969 CSR_READ_1(sc, STE_STAT_RX_MCAST);
970 CSR_READ_1(sc, STE_STAT_RX_LOST);
971 /* Tx stats. */
972 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
973 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
974 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
975 CSR_READ_1(sc, STE_STAT_TX_BCAST);
976 CSR_READ_1(sc, STE_STAT_TX_MCAST);
977 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
978 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
979 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
980 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
981 CSR_READ_1(sc, STE_STAT_TX_DEFER);
982 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
983 CSR_READ_1(sc, STE_STAT_TX_ABORT);
984}
936 ifp = sc->ste_ifp;
937 mii = device_get_softc(sc->ste_miibus);
985
938
986static void
987ste_stats_update(struct ste_softc *sc)
988{
989 struct ifnet *ifp;
990 struct ste_hw_stats *stats;
991 uint32_t val;
939 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
940 + CSR_READ_1(sc, STE_MULTI_COLLS)
941 + CSR_READ_1(sc, STE_SINGLE_COLLS);
992
942
993 STE_LOCK_ASSERT(sc);
943 if (!sc->ste_link) {
944 mii_pollstat(mii);
945 if (mii->mii_media_status & IFM_ACTIVE &&
946 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
947 sc->ste_link++;
948 /*
949 * we don't get a call-back on re-init so do it
950 * otherwise we get stuck in the wrong link state
951 */
952 ste_miibus_statchg(sc->ste_dev);
953 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
954 ste_start_locked(ifp);
955 }
956 }
994
957
995 ifp = sc->ste_ifp;
996 stats = &sc->ste_stats;
997 /* Rx stats. */
998 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
999 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
1000 val &= 0x000FFFFF;
1001 stats->rx_bytes += val;
1002 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
1003 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
1004 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
1005 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
1006 /* Tx stats. */
1007 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
1008 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
1009 val &= 0x000FFFFF;
1010 stats->tx_bytes += val;
1011 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
1012 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
1013 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
1014 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
1015 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
1016 stats->tx_single_colls += val;
1017 ifp->if_collisions += val;
1018 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
1019 stats->tx_multi_colls += val;
1020 ifp->if_collisions += val;
1021 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
1022 stats->tx_late_colls += val;
1023 ifp->if_collisions += val;
1024 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
1025 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
1026 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
958 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
959
960 return;
1027}
1028
961}
962
963
1029/*
1030 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
1031 * IDs against our list and return a device name if we find a match.
1032 */
1033static int
964/*
965 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
966 * IDs against our list and return a device name if we find a match.
967 */
968static int
1034ste_probe(device_t dev)
969ste_probe(dev)
970 device_t dev;
1035{
971{
1036 struct ste_type *t;
972 struct ste_type *t;
1037
1038 t = ste_devs;
1039
973
974 t = ste_devs;
975
1040 while (t->ste_name != NULL) {
976 while(t->ste_name != NULL) {
1041 if ((pci_get_vendor(dev) == t->ste_vid) &&
1042 (pci_get_device(dev) == t->ste_did)) {
1043 device_set_desc(dev, t->ste_name);
1044 return (BUS_PROBE_DEFAULT);
1045 }
1046 t++;
1047 }
1048
977 if ((pci_get_vendor(dev) == t->ste_vid) &&
978 (pci_get_device(dev) == t->ste_did)) {
979 device_set_desc(dev, t->ste_name);
980 return (BUS_PROBE_DEFAULT);
981 }
982 t++;
983 }
984
1049 return (ENXIO);
985 return(ENXIO);
1050}
1051
1052/*
1053 * Attach the interface. Allocate softc structures, do ifmedia
1054 * setup and ethernet/BPF attach.
1055 */
1056static int
986}
987
988/*
989 * Attach the interface. Allocate softc structures, do ifmedia
990 * setup and ethernet/BPF attach.
991 */
992static int
1057ste_attach(device_t dev)
993ste_attach(dev)
994 device_t dev;
1058{
995{
1059 struct ste_softc *sc;
1060 struct ifnet *ifp;
1061 uint16_t eaddr[ETHER_ADDR_LEN / 2];
1062 int error = 0, pmc, rid;
996 struct ste_softc *sc;
997 struct ifnet *ifp;
998 int error = 0, rid;
999 u_char eaddr[6];
1063
1064 sc = device_get_softc(dev);
1065 sc->ste_dev = dev;
1066
1067 /*
1068 * Only use one PHY since this chip reports multiple
1069 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1070 * it is at 0 & 1. It is rev 0x12.
1071 */
1072 if (pci_get_vendor(dev) == DL_VENDORID &&
1073 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1074 pci_get_revid(dev) == 0x12 )
1000
1001 sc = device_get_softc(dev);
1002 sc->ste_dev = dev;
1003
1004 /*
1005 * Only use one PHY since this chip reports multiple
1006 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1007 * it is at 0 & 1. It is rev 0x12.
1008 */
1009 if (pci_get_vendor(dev) == DL_VENDORID &&
1010 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1011 pci_get_revid(dev) == 0x12 )
1075 sc->ste_flags |= STE_FLAG_ONE_PHY;
1012 sc->ste_one_phy = 1;
1076
1077 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1078 MTX_DEF);
1079 /*
1080 * Map control/status registers.
1081 */
1082 pci_enable_busmaster(dev);
1083
1013
1014 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1015 MTX_DEF);
1016 /*
1017 * Map control/status registers.
1018 */
1019 pci_enable_busmaster(dev);
1020
1084 /* Prefer memory space register mapping over IO space. */
1085 sc->ste_res_id = PCIR_BAR(1);
1086 sc->ste_res_type = SYS_RES_MEMORY;
1087 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1088 &sc->ste_res_id, RF_ACTIVE);
1021 rid = STE_RID;
1022 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
1023
1089 if (sc->ste_res == NULL) {
1024 if (sc->ste_res == NULL) {
1090 sc->ste_res_id = PCIR_BAR(0);
1091 sc->ste_res_type = SYS_RES_IOPORT;
1092 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
1093 &sc->ste_res_id, RF_ACTIVE);
1094 }
1095 if (sc->ste_res == NULL) {
1096 device_printf(dev, "couldn't map ports/memory\n");
1097 error = ENXIO;
1098 goto fail;
1099 }
1100
1025 device_printf(dev, "couldn't map ports/memory\n");
1026 error = ENXIO;
1027 goto fail;
1028 }
1029
1030 sc->ste_btag = rman_get_bustag(sc->ste_res);
1031 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
1032
1101 /* Allocate interrupt */
1102 rid = 0;
1103 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1104 RF_SHAREABLE | RF_ACTIVE);
1105
1106 if (sc->ste_irq == NULL) {
1107 device_printf(dev, "couldn't map interrupt\n");
1108 error = ENXIO;
1109 goto fail;
1110 }
1111
1033 /* Allocate interrupt */
1034 rid = 0;
1035 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1036 RF_SHAREABLE | RF_ACTIVE);
1037
1038 if (sc->ste_irq == NULL) {
1039 device_printf(dev, "couldn't map interrupt\n");
1040 error = ENXIO;
1041 goto fail;
1042 }
1043
1112 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
1044 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0);
1113
1114 /* Reset the adapter. */
1115 ste_reset(sc);
1116
1117 /*
1118 * Get station address from the EEPROM.
1119 */
1045
1046 /* Reset the adapter. */
1047 ste_reset(sc);
1048
1049 /*
1050 * Get station address from the EEPROM.
1051 */
1120 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
1052 if (ste_read_eeprom(sc, eaddr,
1053 STE_EEADDR_NODE0, 3, 0)) {
1121 device_printf(dev, "failed to read station address\n");
1054 device_printf(dev, "failed to read station address\n");
1122 error = ENXIO;
1055 error = ENXIO;;
1123 goto fail;
1124 }
1056 goto fail;
1057 }
1125 ste_sysctl_node(sc);
1126
1058
1127 if ((error = ste_dma_alloc(sc)) != 0)
1059 /* Allocate the descriptor queues. */
1060 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1061 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1062
1063 if (sc->ste_ldata == NULL) {
1064 device_printf(dev, "no memory for list buffers!\n");
1065 error = ENXIO;
1128 goto fail;
1066 goto fail;
1067 }
1129
1068
1069 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1070
1130 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1131 if (ifp == NULL) {
1132 device_printf(dev, "can not if_alloc()\n");
1133 error = ENOSPC;
1134 goto fail;
1135 }
1136
1137 /* Do MII setup. */
1138 if (mii_phy_probe(dev, &sc->ste_miibus,
1139 ste_ifmedia_upd, ste_ifmedia_sts)) {
1140 device_printf(dev, "MII without any phy!\n");
1141 error = ENXIO;
1142 goto fail;
1143 }
1144
1145 ifp->if_softc = sc;
1146 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1071 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1072 if (ifp == NULL) {
1073 device_printf(dev, "can not if_alloc()\n");
1074 error = ENOSPC;
1075 goto fail;
1076 }
1077
1078 /* Do MII setup. */
1079 if (mii_phy_probe(dev, &sc->ste_miibus,
1080 ste_ifmedia_upd, ste_ifmedia_sts)) {
1081 device_printf(dev, "MII without any phy!\n");
1082 error = ENXIO;
1083 goto fail;
1084 }
1085
1086 ifp->if_softc = sc;
1087 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1088 ifp->if_mtu = ETHERMTU;
1147 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1148 ifp->if_ioctl = ste_ioctl;
1149 ifp->if_start = ste_start;
1089 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1090 ifp->if_ioctl = ste_ioctl;
1091 ifp->if_start = ste_start;
1092 ifp->if_watchdog = ste_watchdog;
1150 ifp->if_init = ste_init;
1151 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1152 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1153 IFQ_SET_READY(&ifp->if_snd);
1154
1155 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1156
1157 /*
1158 * Call MI attach routine.
1159 */
1093 ifp->if_init = ste_init;
1094 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1095 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1096 IFQ_SET_READY(&ifp->if_snd);
1097
1098 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1099
1100 /*
1101 * Call MI attach routine.
1102 */
1160 ether_ifattach(ifp, (uint8_t *)eaddr);
1103 ether_ifattach(ifp, eaddr);
1161
1162 /*
1163 * Tell the upper layer(s) we support long frames.
1164 */
1165 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1166 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1104
1105 /*
1106 * Tell the upper layer(s) we support long frames.
1107 */
1108 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1109 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1167 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
1168 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1169 ifp->if_capenable = ifp->if_capabilities;
1170#ifdef DEVICE_POLLING
1171 ifp->if_capabilities |= IFCAP_POLLING;
1172#endif
1173
1174 /* Hook interrupt last to avoid having to lock softc */
1175 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1176 NULL, ste_intr, sc, &sc->ste_intrhand);
1177
1178 if (error) {
1179 device_printf(dev, "couldn't set up irq\n");
1180 ether_ifdetach(ifp);
1181 goto fail;
1182 }
1183
1184fail:
1185 if (error)
1186 ste_detach(dev);
1187
1110 ifp->if_capenable = ifp->if_capabilities;
1111#ifdef DEVICE_POLLING
1112 ifp->if_capabilities |= IFCAP_POLLING;
1113#endif
1114
1115 /* Hook interrupt last to avoid having to lock softc */
1116 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1117 NULL, ste_intr, sc, &sc->ste_intrhand);
1118
1119 if (error) {
1120 device_printf(dev, "couldn't set up irq\n");
1121 ether_ifdetach(ifp);
1122 goto fail;
1123 }
1124
1125fail:
1126 if (error)
1127 ste_detach(dev);
1128
1188 return (error);
1129 return(error);
1189}
1190
1191/*
1192 * Shutdown hardware and free up resources. This can be called any
1193 * time after the mutex has been initialized. It is called in both
1194 * the error case in attach and the normal detach case so it needs
1195 * to be careful about only freeing resources that have actually been
1196 * allocated.
1197 */
1198static int
1130}
1131
1132/*
1133 * Shutdown hardware and free up resources. This can be called any
1134 * time after the mutex has been initialized. It is called in both
1135 * the error case in attach and the normal detach case so it needs
1136 * to be careful about only freeing resources that have actually been
1137 * allocated.
1138 */
1139static int
1199ste_detach(device_t dev)
1140ste_detach(dev)
1141 device_t dev;
1200{
1142{
1201 struct ste_softc *sc;
1202 struct ifnet *ifp;
1143 struct ste_softc *sc;
1144 struct ifnet *ifp;
1203
1204 sc = device_get_softc(dev);
1205 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1206 ifp = sc->ste_ifp;
1207
1208#ifdef DEVICE_POLLING
1209 if (ifp->if_capenable & IFCAP_POLLING)
1210 ether_poll_deregister(ifp);
1211#endif
1212
1213 /* These should only be active if attach succeeded */
1214 if (device_is_attached(dev)) {
1145
1146 sc = device_get_softc(dev);
1147 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1148 ifp = sc->ste_ifp;
1149
1150#ifdef DEVICE_POLLING
1151 if (ifp->if_capenable & IFCAP_POLLING)
1152 ether_poll_deregister(ifp);
1153#endif
1154
1155 /* These should only be active if attach succeeded */
1156 if (device_is_attached(dev)) {
1215 ether_ifdetach(ifp);
1216 STE_LOCK(sc);
1217 ste_stop(sc);
1218 STE_UNLOCK(sc);
1157 STE_LOCK(sc);
1158 ste_stop(sc);
1159 STE_UNLOCK(sc);
1219 callout_drain(&sc->ste_callout);
1160 callout_drain(&sc->ste_stat_callout);
1161 ether_ifdetach(ifp);
1220 }
1221 if (sc->ste_miibus)
1222 device_delete_child(dev, sc->ste_miibus);
1223 bus_generic_detach(dev);
1224
1225 if (sc->ste_intrhand)
1226 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1227 if (sc->ste_irq)
1228 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1229 if (sc->ste_res)
1162 }
1163 if (sc->ste_miibus)
1164 device_delete_child(dev, sc->ste_miibus);
1165 bus_generic_detach(dev);
1166
1167 if (sc->ste_intrhand)
1168 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1169 if (sc->ste_irq)
1170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1171 if (sc->ste_res)
1230 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1231 sc->ste_res);
1172 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1232
1233 if (ifp)
1234 if_free(ifp);
1235
1173
1174 if (ifp)
1175 if_free(ifp);
1176
1236 ste_dma_free(sc);
1177 if (sc->ste_ldata) {
1178 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1179 M_DEVBUF);
1180 }
1181
1237 mtx_destroy(&sc->ste_mtx);
1238
1182 mtx_destroy(&sc->ste_mtx);
1183
1239 return (0);
1184 return(0);
1240}
1241
1185}
1186
1242struct ste_dmamap_arg {
1243 bus_addr_t ste_busaddr;
1244};
1245
1246static void
1247ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1248{
1249 struct ste_dmamap_arg *ctx;
1250
1251 if (error != 0)
1252 return;
1253
1254 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1255
1256 ctx = (struct ste_dmamap_arg *)arg;
1257 ctx->ste_busaddr = segs[0].ds_addr;
1258}
1259
1260static int
1187static int
1261ste_dma_alloc(struct ste_softc *sc)
1188ste_newbuf(sc, c, m)
1189 struct ste_softc *sc;
1190 struct ste_chain_onefrag *c;
1191 struct mbuf *m;
1262{
1192{
1263 struct ste_chain *txc;
1264 struct ste_chain_onefrag *rxc;
1265 struct ste_dmamap_arg ctx;
1266 int error, i;
1193 struct mbuf *m_new = NULL;
1267
1194
1268 /* Create parent DMA tag. */
1269 error = bus_dma_tag_create(
1270 bus_get_dma_tag(sc->ste_dev), /* parent */
1271 1, 0, /* alignment, boundary */
1272 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1273 BUS_SPACE_MAXADDR, /* highaddr */
1274 NULL, NULL, /* filter, filterarg */
1275 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1276 0, /* nsegments */
1277 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1278 0, /* flags */
1279 NULL, NULL, /* lockfunc, lockarg */
1280 &sc->ste_cdata.ste_parent_tag);
1281 if (error != 0) {
1282 device_printf(sc->ste_dev,
1283 "could not create parent DMA tag.\n");
1284 goto fail;
1285 }
1286
1287 /* Create DMA tag for Tx descriptor list. */
1288 error = bus_dma_tag_create(
1289 sc->ste_cdata.ste_parent_tag, /* parent */
1290 STE_DESC_ALIGN, 0, /* alignment, boundary */
1291 BUS_SPACE_MAXADDR, /* lowaddr */
1292 BUS_SPACE_MAXADDR, /* highaddr */
1293 NULL, NULL, /* filter, filterarg */
1294 STE_TX_LIST_SZ, /* maxsize */
1295 1, /* nsegments */
1296 STE_TX_LIST_SZ, /* maxsegsize */
1297 0, /* flags */
1298 NULL, NULL, /* lockfunc, lockarg */
1299 &sc->ste_cdata.ste_tx_list_tag);
1300 if (error != 0) {
1301 device_printf(sc->ste_dev,
1302 "could not create Tx list DMA tag.\n");
1303 goto fail;
1304 }
1305
1306 /* Create DMA tag for Rx descriptor list. */
1307 error = bus_dma_tag_create(
1308 sc->ste_cdata.ste_parent_tag, /* parent */
1309 STE_DESC_ALIGN, 0, /* alignment, boundary */
1310 BUS_SPACE_MAXADDR, /* lowaddr */
1311 BUS_SPACE_MAXADDR, /* highaddr */
1312 NULL, NULL, /* filter, filterarg */
1313 STE_RX_LIST_SZ, /* maxsize */
1314 1, /* nsegments */
1315 STE_RX_LIST_SZ, /* maxsegsize */
1316 0, /* flags */
1317 NULL, NULL, /* lockfunc, lockarg */
1318 &sc->ste_cdata.ste_rx_list_tag);
1319 if (error != 0) {
1320 device_printf(sc->ste_dev,
1321 "could not create Rx list DMA tag.\n");
1322 goto fail;
1323 }
1324
1325 /* Create DMA tag for Tx buffers. */
1326 error = bus_dma_tag_create(
1327 sc->ste_cdata.ste_parent_tag, /* parent */
1328 1, 0, /* alignment, boundary */
1329 BUS_SPACE_MAXADDR, /* lowaddr */
1330 BUS_SPACE_MAXADDR, /* highaddr */
1331 NULL, NULL, /* filter, filterarg */
1332 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1333 STE_MAXFRAGS, /* nsegments */
1334 MCLBYTES, /* maxsegsize */
1335 0, /* flags */
1336 NULL, NULL, /* lockfunc, lockarg */
1337 &sc->ste_cdata.ste_tx_tag);
1338 if (error != 0) {
1339 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1340 goto fail;
1341 }
1342
1343 /* Create DMA tag for Rx buffers. */
1344 error = bus_dma_tag_create(
1345 sc->ste_cdata.ste_parent_tag, /* parent */
1346 1, 0, /* alignment, boundary */
1347 BUS_SPACE_MAXADDR, /* lowaddr */
1348 BUS_SPACE_MAXADDR, /* highaddr */
1349 NULL, NULL, /* filter, filterarg */
1350 MCLBYTES, /* maxsize */
1351 1, /* nsegments */
1352 MCLBYTES, /* maxsegsize */
1353 0, /* flags */
1354 NULL, NULL, /* lockfunc, lockarg */
1355 &sc->ste_cdata.ste_rx_tag);
1356 if (error != 0) {
1357 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1358 goto fail;
1359 }
1360
1361 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1362 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1363 (void **)&sc->ste_ldata.ste_tx_list,
1364 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1365 &sc->ste_cdata.ste_tx_list_map);
1366 if (error != 0) {
1367 device_printf(sc->ste_dev,
1368 "could not allocate DMA'able memory for Tx list.\n");
1369 goto fail;
1370 }
1371 ctx.ste_busaddr = 0;
1372 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1373 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1374 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1375 if (error != 0 || ctx.ste_busaddr == 0) {
1376 device_printf(sc->ste_dev,
1377 "could not load DMA'able memory for Tx list.\n");
1378 goto fail;
1379 }
1380 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1381
1382 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1383 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1384 (void **)&sc->ste_ldata.ste_rx_list,
1385 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1386 &sc->ste_cdata.ste_rx_list_map);
1387 if (error != 0) {
1388 device_printf(sc->ste_dev,
1389 "could not allocate DMA'able memory for Rx list.\n");
1390 goto fail;
1391 }
1392 ctx.ste_busaddr = 0;
1393 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1394 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1395 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1396 if (error != 0 || ctx.ste_busaddr == 0) {
1397 device_printf(sc->ste_dev,
1398 "could not load DMA'able memory for Rx list.\n");
1399 goto fail;
1400 }
1401 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1402
1403 /* Create DMA maps for Tx buffers. */
1404 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1405 txc = &sc->ste_cdata.ste_tx_chain[i];
1406 txc->ste_ptr = NULL;
1407 txc->ste_mbuf = NULL;
1408 txc->ste_next = NULL;
1409 txc->ste_phys = 0;
1410 txc->ste_map = NULL;
1411 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1412 &txc->ste_map);
1413 if (error != 0) {
1414 device_printf(sc->ste_dev,
1415 "could not create Tx dmamap.\n");
1416 goto fail;
1195 if (m == NULL) {
1196 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1197 if (m_new == NULL)
1198 return(ENOBUFS);
1199 MCLGET(m_new, M_DONTWAIT);
1200 if (!(m_new->m_flags & M_EXT)) {
1201 m_freem(m_new);
1202 return(ENOBUFS);
1417 }
1203 }
1204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1205 } else {
1206 m_new = m;
1207 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1208 m_new->m_data = m_new->m_ext.ext_buf;
1418 }
1209 }
1419 /* Create DMA maps for Rx buffers. */
1420 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1421 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1422 device_printf(sc->ste_dev,
1423 "could not create spare Rx dmamap.\n");
1424 goto fail;
1425 }
1426 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1427 rxc = &sc->ste_cdata.ste_rx_chain[i];
1428 rxc->ste_ptr = NULL;
1429 rxc->ste_mbuf = NULL;
1430 rxc->ste_next = NULL;
1431 rxc->ste_map = NULL;
1432 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1433 &rxc->ste_map);
1434 if (error != 0) {
1435 device_printf(sc->ste_dev,
1436 "could not create Rx dmamap.\n");
1437 goto fail;
1438 }
1439 }
1440
1210
1441fail:
1442 return (error);
1443}
1211 m_adj(m_new, ETHER_ALIGN);
1444
1212
1445static void
1446ste_dma_free(struct ste_softc *sc)
1447{
1448 struct ste_chain *txc;
1449 struct ste_chain_onefrag *rxc;
1450 int i;
1213 c->ste_mbuf = m_new;
1214 c->ste_ptr->ste_status = 0;
1215 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1216 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST;
1451
1217
1452 /* Tx buffers. */
1453 if (sc->ste_cdata.ste_tx_tag != NULL) {
1454 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1455 txc = &sc->ste_cdata.ste_tx_chain[i];
1456 if (txc->ste_map != NULL) {
1457 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1458 txc->ste_map);
1459 txc->ste_map = NULL;
1460 }
1461 }
1462 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1463 sc->ste_cdata.ste_tx_tag = NULL;
1464 }
1465 /* Rx buffers. */
1466 if (sc->ste_cdata.ste_rx_tag != NULL) {
1467 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1468 rxc = &sc->ste_cdata.ste_rx_chain[i];
1469 if (rxc->ste_map != NULL) {
1470 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1471 rxc->ste_map);
1472 rxc->ste_map = NULL;
1473 }
1474 }
1475 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1476 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1477 sc->ste_cdata.ste_rx_sparemap);
1478 sc->ste_cdata.ste_rx_sparemap = NULL;
1479 }
1480 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1481 sc->ste_cdata.ste_rx_tag = NULL;
1482 }
1483 /* Tx descriptor list. */
1484 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1485 if (sc->ste_cdata.ste_tx_list_map != NULL)
1486 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1487 sc->ste_cdata.ste_tx_list_map);
1488 if (sc->ste_cdata.ste_tx_list_map != NULL &&
1489 sc->ste_ldata.ste_tx_list != NULL)
1490 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1491 sc->ste_ldata.ste_tx_list,
1492 sc->ste_cdata.ste_tx_list_map);
1493 sc->ste_ldata.ste_tx_list = NULL;
1494 sc->ste_cdata.ste_tx_list_map = NULL;
1495 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1496 sc->ste_cdata.ste_tx_list_tag = NULL;
1497 }
1498 /* Rx descriptor list. */
1499 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1500 if (sc->ste_cdata.ste_rx_list_map != NULL)
1501 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1502 sc->ste_cdata.ste_rx_list_map);
1503 if (sc->ste_cdata.ste_rx_list_map != NULL &&
1504 sc->ste_ldata.ste_rx_list != NULL)
1505 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1506 sc->ste_ldata.ste_rx_list,
1507 sc->ste_cdata.ste_rx_list_map);
1508 sc->ste_ldata.ste_rx_list = NULL;
1509 sc->ste_cdata.ste_rx_list_map = NULL;
1510 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1511 sc->ste_cdata.ste_rx_list_tag = NULL;
1512 }
1513 if (sc->ste_cdata.ste_parent_tag != NULL) {
1514 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1515 sc->ste_cdata.ste_parent_tag = NULL;
1516 }
1218 return(0);
1517}
1518
1519static int
1219}
1220
1221static int
1520ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1222ste_init_rx_list(sc)
1223 struct ste_softc *sc;
1521{
1224{
1522 struct mbuf *m;
1523 bus_dma_segment_t segs[1];
1524 bus_dmamap_t map;
1525 int error, nsegs;
1225 struct ste_chain_data *cd;
1226 struct ste_list_data *ld;
1227 int i;
1526
1228
1527 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1528 if (m == NULL)
1529 return (ENOBUFS);
1530 m->m_len = m->m_pkthdr.len = MCLBYTES;
1531 m_adj(m, ETHER_ALIGN);
1532
1533 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1534 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1535 m_freem(m);
1536 return (error);
1537 }
1538 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1539
1540 if (rxc->ste_mbuf != NULL) {
1541 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1542 BUS_DMASYNC_POSTREAD);
1543 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1544 }
1545 map = rxc->ste_map;
1546 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1547 sc->ste_cdata.ste_rx_sparemap = map;
1548 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1549 BUS_DMASYNC_PREREAD);
1550 rxc->ste_mbuf = m;
1551 rxc->ste_ptr->ste_status = 0;
1552 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1553 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1554 STE_FRAG_LAST);
1555 return (0);
1556}
1557
1558static int
1559ste_init_rx_list(struct ste_softc *sc)
1560{
1561 struct ste_chain_data *cd;
1562 struct ste_list_data *ld;
1563 int error, i;
1564
1565 sc->ste_int_rx_act = 0;
1566 cd = &sc->ste_cdata;
1229 cd = &sc->ste_cdata;
1567 ld = &sc->ste_ldata;
1568 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1230 ld = sc->ste_ldata;
1231
1569 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1570 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1232 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1233 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1571 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1572 if (error != 0)
1573 return (error);
1234 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1235 return(ENOBUFS);
1574 if (i == (STE_RX_LIST_CNT - 1)) {
1236 if (i == (STE_RX_LIST_CNT - 1)) {
1575 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1237 cd->ste_rx_chain[i].ste_next =
1238 &cd->ste_rx_chain[0];
1576 ld->ste_rx_list[i].ste_next =
1239 ld->ste_rx_list[i].ste_next =
1577 htole32(ld->ste_rx_list_paddr +
1578 (sizeof(struct ste_desc_onefrag) * 0));
1240 vtophys(&ld->ste_rx_list[0]);
1579 } else {
1241 } else {
1580 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1242 cd->ste_rx_chain[i].ste_next =
1243 &cd->ste_rx_chain[i + 1];
1581 ld->ste_rx_list[i].ste_next =
1244 ld->ste_rx_list[i].ste_next =
1582 htole32(ld->ste_rx_list_paddr +
1583 (sizeof(struct ste_desc_onefrag) * (i + 1)));
1245 vtophys(&ld->ste_rx_list[i + 1]);
1584 }
1246 }
1247 ld->ste_rx_list[i].ste_status = 0;
1585 }
1586
1587 cd->ste_rx_head = &cd->ste_rx_chain[0];
1248 }
1249
1250 cd->ste_rx_head = &cd->ste_rx_chain[0];
1588 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1589 sc->ste_cdata.ste_rx_list_map,
1590 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1591
1251
1592 return (0);
1252 return(0);
1593}
1594
1595static void
1253}
1254
1255static void
1596ste_init_tx_list(struct ste_softc *sc)
1256ste_init_tx_list(sc)
1257 struct ste_softc *sc;
1597{
1258{
1598 struct ste_chain_data *cd;
1599 struct ste_list_data *ld;
1600 int i;
1259 struct ste_chain_data *cd;
1260 struct ste_list_data *ld;
1261 int i;
1601
1602 cd = &sc->ste_cdata;
1262
1263 cd = &sc->ste_cdata;
1603 ld = &sc->ste_ldata;
1604 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1264 ld = sc->ste_ldata;
1605 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1606 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1265 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1266 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1607 cd->ste_tx_chain[i].ste_mbuf = NULL;
1608 if (i == (STE_TX_LIST_CNT - 1)) {
1609 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1610 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1611 ld->ste_tx_list_paddr +
1612 (sizeof(struct ste_desc) * 0)));
1613 } else {
1614 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1615 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1616 ld->ste_tx_list_paddr +
1617 (sizeof(struct ste_desc) * (i + 1))));
1618 }
1267 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1268 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1269 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1270 if (i == (STE_TX_LIST_CNT - 1))
1271 cd->ste_tx_chain[i].ste_next =
1272 &cd->ste_tx_chain[0];
1273 else
1274 cd->ste_tx_chain[i].ste_next =
1275 &cd->ste_tx_chain[i + 1];
1619 }
1620
1276 }
1277
1621 cd->ste_last_tx = NULL;
1622 cd->ste_tx_prod = 0;
1623 cd->ste_tx_cons = 0;
1278 cd->ste_tx_prod = 0;
1279 cd->ste_tx_cons = 0;
1624 cd->ste_tx_cnt = 0;
1625
1280
1626 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1627 sc->ste_cdata.ste_tx_list_map,
1628 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1281 return;
1629}
1630
1631static void
1282}
1283
1284static void
1632ste_init(void *xsc)
1285ste_init(xsc)
1286 void *xsc;
1633{
1287{
1634 struct ste_softc *sc;
1288 struct ste_softc *sc;
1635
1636 sc = xsc;
1637 STE_LOCK(sc);
1638 ste_init_locked(sc);
1639 STE_UNLOCK(sc);
1640}
1641
1642static void
1289
1290 sc = xsc;
1291 STE_LOCK(sc);
1292 ste_init_locked(sc);
1293 STE_UNLOCK(sc);
1294}
1295
1296static void
1643ste_init_locked(struct ste_softc *sc)
1297ste_init_locked(sc)
1298 struct ste_softc *sc;
1644{
1299{
1645 struct ifnet *ifp;
1646 struct mii_data *mii;
1647 uint8_t val;
1648 int i;
1300 int i;
1301 struct ifnet *ifp;
1649
1650 STE_LOCK_ASSERT(sc);
1651 ifp = sc->ste_ifp;
1302
1303 STE_LOCK_ASSERT(sc);
1304 ifp = sc->ste_ifp;
1652 mii = device_get_softc(sc->ste_miibus);
1653
1305
1654 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1655 return;
1656
1657 ste_stop(sc);
1306 ste_stop(sc);
1658 /* Reset the chip to a known state. */
1659 ste_reset(sc);
1660
1661 /* Init our MAC address */
1662 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1663 CSR_WRITE_2(sc, STE_PAR0 + i,
1664 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1665 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1666 }
1667
1668 /* Init RX list */
1307
1308 /* Init our MAC address */
1309 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1310 CSR_WRITE_2(sc, STE_PAR0 + i,
1311 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1312 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1313 }
1314
1315 /* Init RX list */
1669 if (ste_init_rx_list(sc) != 0) {
1316 if (ste_init_rx_list(sc) == ENOBUFS) {
1670 device_printf(sc->ste_dev,
1671 "initialization failed: no memory for RX buffers\n");
1672 ste_stop(sc);
1673 return;
1674 }
1675
1676 /* Set RX polling interval */
1677 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1678
1679 /* Init TX descriptors */
1680 ste_init_tx_list(sc);
1681
1317 device_printf(sc->ste_dev,
1318 "initialization failed: no memory for RX buffers\n");
1319 ste_stop(sc);
1320 return;
1321 }
1322
1323 /* Set RX polling interval */
1324 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1325
1326 /* Init TX descriptors */
1327 ste_init_tx_list(sc);
1328
1682 /* Clear and disable WOL. */
1683 val = CSR_READ_1(sc, STE_WAKE_EVENT);
1684 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
1685 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
1686 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1687
1688 /* Set the TX freethresh value */
1689 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1690
1691 /* Set the TX start threshold for best performance. */
1692 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1693
1694 /* Set the TX reclaim threshold. */
1695 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1696
1329 /* Set the TX freethresh value */
1330 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1331
1332 /* Set the TX start threshold for best performance. */
1333 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1334
1335 /* Set the TX reclaim threshold. */
1336 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1337
1697 /* Accept VLAN length packets */
1698 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1699
1700 /* Set up the RX filter. */
1338 /* Set up the RX filter. */
1701 ste_rxfilter(sc);
1339 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1702
1340
1341 /* If we want promiscuous mode, set the allframes bit. */
1342 if (ifp->if_flags & IFF_PROMISC) {
1343 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1344 } else {
1345 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1346 }
1347
1348 /* Set capture broadcast bit to accept broadcast frames. */
1349 if (ifp->if_flags & IFF_BROADCAST) {
1350 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1351 } else {
1352 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1353 }
1354
1355 ste_setmulti(sc);
1356
1703 /* Load the address of the RX list. */
1704 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1705 ste_wait(sc);
1706 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1357 /* Load the address of the RX list. */
1358 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1359 ste_wait(sc);
1360 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1707 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1361 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1708 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1709 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1710
1362 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1363 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1364
1711 /* Set TX polling interval(defer until we TX first packet). */
1365 /* Set TX polling interval (defer until we TX first packet */
1712 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1713
1714 /* Load address of the TX list */
1715 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1716 ste_wait(sc);
1717 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1718 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1719 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1720 ste_wait(sc);
1366 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1367
1368 /* Load address of the TX list */
1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1370 ste_wait(sc);
1371 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1372 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1373 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1374 ste_wait(sc);
1721 /* Select 3.2us timer. */
1722 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
1723 STE_DMACTL_COUNTDOWN_MODE);
1375 sc->ste_tx_prev = NULL;
1724
1725 /* Enable receiver and transmitter */
1726 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1727 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1728 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1729 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1730
1731 /* Enable stats counters. */
1732 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1376
1377 /* Enable receiver and transmitter */
1378 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1379 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1380 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1381 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1382
1383 /* Enable stats counters. */
1384 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1733 /* Clear stats counters. */
1734 ste_stats_clear(sc);
1735
1385
1736 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1737 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1738#ifdef DEVICE_POLLING
1739 /* Disable interrupts if we are polling. */
1740 if (ifp->if_capenable & IFCAP_POLLING)
1741 CSR_WRITE_2(sc, STE_IMR, 0);
1386 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1387#ifdef DEVICE_POLLING
1388 /* Disable interrupts if we are polling. */
1389 if (ifp->if_capenable & IFCAP_POLLING)
1390 CSR_WRITE_2(sc, STE_IMR, 0);
1742 else
1391 else
1743#endif
1744 /* Enable interrupts. */
1745 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1746
1392#endif
1393 /* Enable interrupts. */
1394 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1395
1747 sc->ste_flags &= ~STE_FLAG_LINK;
1748 /* Switch to the current media. */
1749 mii_mediachg(mii);
1396 /* Accept VLAN length packets */
1397 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1750
1398
1399 ste_ifmedia_upd_locked(ifp);
1400
1751 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1752 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1753
1401 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1402 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1403
1754 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1404 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
1405
1406 return;
1755}
1756
1757static void
1407}
1408
1409static void
1758ste_stop(struct ste_softc *sc)
1410ste_stop(sc)
1411 struct ste_softc *sc;
1759{
1412{
1760 struct ifnet *ifp;
1761 struct ste_chain_onefrag *cur_rx;
1762 struct ste_chain *cur_tx;
1763 uint32_t val;
1764 int i;
1413 int i;
1414 struct ifnet *ifp;
1765
1766 STE_LOCK_ASSERT(sc);
1767 ifp = sc->ste_ifp;
1768
1415
1416 STE_LOCK_ASSERT(sc);
1417 ifp = sc->ste_ifp;
1418
1769 callout_stop(&sc->ste_callout);
1770 sc->ste_timer = 0;
1419 callout_stop(&sc->ste_stat_callout);
1771 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1772
1773 CSR_WRITE_2(sc, STE_IMR, 0);
1420 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1421
1422 CSR_WRITE_2(sc, STE_IMR, 0);
1774 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1775 /* Stop pending DMA. */
1776 val = CSR_READ_4(sc, STE_DMACTL);
1777 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1778 CSR_WRITE_4(sc, STE_DMACTL, val);
1423 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1424 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1425 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1426 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1427 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1779 ste_wait(sc);
1428 ste_wait(sc);
1780 /* Disable auto-polling. */
1781 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1782 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1783 /* Nullify DMA address to stop any further DMA. */
1784 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1785 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1786 /* Stop TX/RX MAC. */
1787 val = CSR_READ_2(sc, STE_MACCTL1);
1788 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1789 STE_MACCTL1_STATS_DISABLE;
1790 CSR_WRITE_2(sc, STE_MACCTL1, val);
1791 for (i = 0; i < STE_TIMEOUT; i++) {
1792 DELAY(10);
1793 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1794 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1795 break;
1796 }
1797 if (i == STE_TIMEOUT)
1798 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1799 /* Acknowledge any pending interrupts. */
1800 CSR_READ_2(sc, STE_ISR_ACK);
1801 ste_stats_update(sc);
1429 /*
1430 * Try really hard to stop the RX engine or under heavy RX
1431 * data chip will write into de-allocated memory.
1432 */
1433 ste_reset(sc);
1802
1434
1435 sc->ste_link = 0;
1436
1803 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1437 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1804 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1805 if (cur_rx->ste_mbuf != NULL) {
1806 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1807 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1808 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1809 cur_rx->ste_map);
1810 m_freem(cur_rx->ste_mbuf);
1811 cur_rx->ste_mbuf = NULL;
1438 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1439 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1440 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1812 }
1813 }
1814
1815 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1441 }
1442 }
1443
1444 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1816 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1817 if (cur_tx->ste_mbuf != NULL) {
1818 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1819 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1820 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1821 cur_tx->ste_map);
1822 m_freem(cur_tx->ste_mbuf);
1823 cur_tx->ste_mbuf = NULL;
1445 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1446 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1447 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1824 }
1825 }
1448 }
1449 }
1450
1451 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1452
1453 return;
1826}
1827
1828static void
1454}
1455
1456static void
1829ste_reset(struct ste_softc *sc)
1457ste_reset(sc)
1458 struct ste_softc *sc;
1830{
1459{
1831 uint32_t ctl;
1832 int i;
1460 int i;
1833
1461
1834 ctl = CSR_READ_4(sc, STE_ASICCTL);
1835 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1836 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1837 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1838 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1839 STE_ASICCTL_EXTRESET_RESET;
1840 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1841 CSR_READ_4(sc, STE_ASICCTL);
1842 /*
1843 * Due to the need of accessing EEPROM controller can take
1844 * up to 1ms to complete the global reset.
1845 */
1846 DELAY(1000);
1462 STE_SETBIT4(sc, STE_ASICCTL,
1463 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1464 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1465 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1466 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1467 STE_ASICCTL_EXTRESET_RESET);
1847
1468
1469 DELAY(100000);
1470
1848 for (i = 0; i < STE_TIMEOUT; i++) {
1849 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1850 break;
1471 for (i = 0; i < STE_TIMEOUT; i++) {
1472 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1473 break;
1851 DELAY(10);
1852 }
1853
1854 if (i == STE_TIMEOUT)
1855 device_printf(sc->ste_dev, "global reset never completed\n");
1474 }
1475
1476 if (i == STE_TIMEOUT)
1477 device_printf(sc->ste_dev, "global reset never completed\n");
1856}
1857
1478
1858static void
1859ste_restart_tx(struct ste_softc *sc)
1860{
1861 uint16_t mac;
1862 int i;
1863
1864 for (i = 0; i < STE_TIMEOUT; i++) {
1865 mac = CSR_READ_2(sc, STE_MACCTL1);
1866 mac |= STE_MACCTL1_TX_ENABLE;
1867 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1868 mac = CSR_READ_2(sc, STE_MACCTL1);
1869 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1870 break;
1871 DELAY(10);
1872 }
1873
1874 if (i == STE_TIMEOUT)
1875 device_printf(sc->ste_dev, "starting Tx failed");
1479 return;
1876}
1877
1878static int
1480}
1481
1482static int
1879ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1483ste_ioctl(ifp, command, data)
1484 struct ifnet *ifp;
1485 u_long command;
1486 caddr_t data;
1880{
1487{
1881 struct ste_softc *sc;
1882 struct ifreq *ifr;
1883 struct mii_data *mii;
1884 int error = 0, mask;
1488 struct ste_softc *sc;
1489 struct ifreq *ifr;
1490 struct mii_data *mii;
1491 int error = 0;
1885
1886 sc = ifp->if_softc;
1887 ifr = (struct ifreq *)data;
1888
1492
1493 sc = ifp->if_softc;
1494 ifr = (struct ifreq *)data;
1495
1889 switch (command) {
1496 switch(command) {
1890 case SIOCSIFFLAGS:
1891 STE_LOCK(sc);
1497 case SIOCSIFFLAGS:
1498 STE_LOCK(sc);
1892 if ((ifp->if_flags & IFF_UP) != 0) {
1893 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1894 ((ifp->if_flags ^ sc->ste_if_flags) &
1895 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1896 ste_rxfilter(sc);
1897 else
1499 if (ifp->if_flags & IFF_UP) {
1500 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1501 ifp->if_flags & IFF_PROMISC &&
1502 !(sc->ste_if_flags & IFF_PROMISC)) {
1503 STE_SETBIT1(sc, STE_RX_MODE,
1504 STE_RXMODE_PROMISC);
1505 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1506 !(ifp->if_flags & IFF_PROMISC) &&
1507 sc->ste_if_flags & IFF_PROMISC) {
1508 STE_CLRBIT1(sc, STE_RX_MODE,
1509 STE_RXMODE_PROMISC);
1510 }
1511 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1512 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
1513 ste_setmulti(sc);
1514 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1515 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1898 ste_init_locked(sc);
1516 ste_init_locked(sc);
1899 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1900 ste_stop(sc);
1517 }
1518 } else {
1519 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1520 ste_stop(sc);
1521 }
1901 sc->ste_if_flags = ifp->if_flags;
1902 STE_UNLOCK(sc);
1522 sc->ste_if_flags = ifp->if_flags;
1523 STE_UNLOCK(sc);
1524 error = 0;
1903 break;
1904 case SIOCADDMULTI:
1905 case SIOCDELMULTI:
1906 STE_LOCK(sc);
1525 break;
1526 case SIOCADDMULTI:
1527 case SIOCDELMULTI:
1528 STE_LOCK(sc);
1907 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1908 ste_rxfilter(sc);
1529 ste_setmulti(sc);
1909 STE_UNLOCK(sc);
1530 STE_UNLOCK(sc);
1531 error = 0;
1910 break;
1911 case SIOCGIFMEDIA:
1912 case SIOCSIFMEDIA:
1913 mii = device_get_softc(sc->ste_miibus);
1914 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1915 break;
1916 case SIOCSIFCAP:
1532 break;
1533 case SIOCGIFMEDIA:
1534 case SIOCSIFMEDIA:
1535 mii = device_get_softc(sc->ste_miibus);
1536 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1537 break;
1538 case SIOCSIFCAP:
1917 STE_LOCK(sc);
1918 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1919#ifdef DEVICE_POLLING
1539#ifdef DEVICE_POLLING
1920 if ((mask & IFCAP_POLLING) != 0 &&
1921 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
1922 ifp->if_capenable ^= IFCAP_POLLING;
1923 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
1924 error = ether_poll_register(ste_poll, ifp);
1925 if (error != 0) {
1926 STE_UNLOCK(sc);
1927 break;
1928 }
1929 /* Disable interrupts. */
1930 CSR_WRITE_2(sc, STE_IMR, 0);
1931 } else {
1932 error = ether_poll_deregister(ifp);
1933 /* Enable interrupts. */
1934 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1935 }
1540 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1541 !(ifp->if_capenable & IFCAP_POLLING)) {
1542 error = ether_poll_register(ste_poll, ifp);
1543 if (error)
1544 return(error);
1545 STE_LOCK(sc);
1546 /* Disable interrupts */
1547 CSR_WRITE_2(sc, STE_IMR, 0);
1548 ifp->if_capenable |= IFCAP_POLLING;
1549 STE_UNLOCK(sc);
1550 return (error);
1551
1936 }
1552 }
1553 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1554 ifp->if_capenable & IFCAP_POLLING) {
1555 error = ether_poll_deregister(ifp);
1556 /* Enable interrupts. */
1557 STE_LOCK(sc);
1558 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1559 ifp->if_capenable &= ~IFCAP_POLLING;
1560 STE_UNLOCK(sc);
1561 return (error);
1562 }
1937#endif /* DEVICE_POLLING */
1563#endif /* DEVICE_POLLING */
1938 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1939 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1940 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1941 STE_UNLOCK(sc);
1942 break;
1943 default:
1944 error = ether_ioctl(ifp, command, data);
1945 break;
1946 }
1947
1564 break;
1565 default:
1566 error = ether_ioctl(ifp, command, data);
1567 break;
1568 }
1569
1948 return (error);
1570 return(error);
1949}
1950
1951static int
1571}
1572
1573static int
1952ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1574ste_encap(sc, c, m_head)
1575 struct ste_softc *sc;
1576 struct ste_chain *c;
1577 struct mbuf *m_head;
1953{
1578{
1954 struct ste_frag *frag;
1955 struct mbuf *m;
1956 struct ste_desc *desc;
1957 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1958 int error, i, nsegs;
1579 int frag = 0;
1580 struct ste_frag *f = NULL;
1581 struct mbuf *m;
1582 struct ste_desc *d;
1959
1583
1960 STE_LOCK_ASSERT(sc);
1961 M_ASSERTPKTHDR((*m_head));
1584 d = c->ste_ptr;
1585 d->ste_ctl = 0;
1962
1586
1963 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1964 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1965 if (error == EFBIG) {
1966 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
1967 if (m == NULL) {
1968 m_freem(*m_head);
1969 *m_head = NULL;
1970 return (ENOMEM);
1587encap_retry:
1588 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1589 if (m->m_len != 0) {
1590 if (frag == STE_MAXFRAGS)
1591 break;
1592 f = &d->ste_frags[frag];
1593 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1594 f->ste_len = m->m_len;
1595 frag++;
1971 }
1596 }
1972 *m_head = m;
1973 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1974 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1975 if (error != 0) {
1976 m_freem(*m_head);
1977 *m_head = NULL;
1978 return (error);
1979 }
1980 } else if (error != 0)
1981 return (error);
1982 if (nsegs == 0) {
1983 m_freem(*m_head);
1984 *m_head = NULL;
1985 return (EIO);
1986 }
1597 }
1987 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1988 BUS_DMASYNC_PREWRITE);
1989
1598
1990 desc = txc->ste_ptr;
1991 for (i = 0; i < nsegs; i++) {
1992 frag = &desc->ste_frags[i];
1993 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1994 frag->ste_len = htole32(txsegs[i].ds_len);
1599 if (m != NULL) {
1600 struct mbuf *mn;
1601
1602 /*
1603 * We ran out of segments. We have to recopy this
1604 * mbuf chain first. Bail out if we can't get the
1605 * new buffers.
1606 */
1607 mn = m_defrag(m_head, M_DONTWAIT);
1608 if (mn == NULL) {
1609 m_freem(m_head);
1610 return ENOMEM;
1611 }
1612 m_head = mn;
1613 goto encap_retry;
1995 }
1614 }
1996 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1997 /*
1998 * Because we use Tx polling we can't chain multiple
1999 * Tx descriptors here. Otherwise we race with controller.
2000 */
2001 desc->ste_next = 0;
2002 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
2003 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
2004 STE_TXCTL_DMAINTR);
2005 else
2006 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
2007 txc->ste_mbuf = *m_head;
2008 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
2009 sc->ste_cdata.ste_tx_cnt++;
2010
1615
2011 return (0);
1616 c->ste_mbuf = m_head;
1617 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1618 d->ste_ctl = 1;
1619
1620 return(0);
2012}
2013
2014static void
1621}
1622
1623static void
2015ste_start(struct ifnet *ifp)
1624ste_start(ifp)
1625 struct ifnet *ifp;
2016{
1626{
2017 struct ste_softc *sc;
1627 struct ste_softc *sc;
2018
2019 sc = ifp->if_softc;
2020 STE_LOCK(sc);
2021 ste_start_locked(ifp);
2022 STE_UNLOCK(sc);
2023}
2024
2025static void
1628
1629 sc = ifp->if_softc;
1630 STE_LOCK(sc);
1631 ste_start_locked(ifp);
1632 STE_UNLOCK(sc);
1633}
1634
1635static void
2026ste_start_locked(struct ifnet *ifp)
1636ste_start_locked(ifp)
1637 struct ifnet *ifp;
2027{
1638{
2028 struct ste_softc *sc;
2029 struct ste_chain *cur_tx;
2030 struct mbuf *m_head = NULL;
2031 int enq;
1639 struct ste_softc *sc;
1640 struct mbuf *m_head = NULL;
1641 struct ste_chain *cur_tx;
1642 int idx;
2032
2033 sc = ifp->if_softc;
2034 STE_LOCK_ASSERT(sc);
2035
1643
1644 sc = ifp->if_softc;
1645 STE_LOCK_ASSERT(sc);
1646
2036 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2037 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1647 if (!sc->ste_link)
2038 return;
2039
1648 return;
1649
2040 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
2041 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
2042 /*
2043 * Controller may have cached copy of the last used
2044 * next ptr so we have to reserve one TFD to avoid
2045 * TFD overruns.
2046 */
1650 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1651 return;
1652
1653 idx = sc->ste_cdata.ste_tx_prod;
1654
1655 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1656 /*
1657 * We cannot re-use the last (free) descriptor;
1658 * the chip may not have read its ste_next yet.
1659 */
1660 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
1661 sc->ste_cdata.ste_tx_cons) {
2047 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2048 break;
2049 }
1662 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1663 break;
1664 }
1665
2050 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2051 if (m_head == NULL)
2052 break;
1666 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1667 if (m_head == NULL)
1668 break;
2053 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
2054 if (ste_encap(sc, &m_head, cur_tx) != 0) {
2055 if (m_head == NULL)
2056 break;
2057 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1669
1670 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1671
1672 if (ste_encap(sc, cur_tx, m_head) != 0)
2058 break;
1673 break;
2059 }
2060 if (sc->ste_cdata.ste_last_tx == NULL) {
2061 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2062 sc->ste_cdata.ste_tx_list_map,
2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1674
1675 cur_tx->ste_ptr->ste_next = 0;
1676
1677 if (sc->ste_tx_prev == NULL) {
1678 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1679 /* Load address of the TX list */
2064 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
2065 ste_wait(sc);
1680 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1681 ste_wait(sc);
1682
2066 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1683 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
2067 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
1684 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1685
1686 /* Set TX polling interval to start TX engine */
2068 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1687 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1688
2069 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
2070 ste_wait(sc);
1689 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1690 ste_wait(sc);
2071 } else {
2072 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
2073 sc->ste_cdata.ste_last_tx->ste_phys;
2074 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
2075 sc->ste_cdata.ste_tx_list_map,
2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1691 }else{
1692 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1693 sc->ste_tx_prev->ste_ptr->ste_next
1694 = cur_tx->ste_phys;
2077 }
1695 }
2078 sc->ste_cdata.ste_last_tx = cur_tx;
2079
1696
2080 enq++;
1697 sc->ste_tx_prev = cur_tx;
1698
2081 /*
2082 * If there's a BPF listener, bounce a copy of this frame
2083 * to him.
2084 */
1699 /*
1700 * If there's a BPF listener, bounce a copy of this frame
1701 * to him.
1702 */
2085 BPF_MTAP(ifp, m_head);
1703 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1704
1705 STE_INC(idx, STE_TX_LIST_CNT);
1706 ifp->if_timer = 5;
2086 }
1707 }
1708 sc->ste_cdata.ste_tx_prod = idx;
2087
1709
2088 if (enq > 0)
2089 sc->ste_timer = STE_TX_TIMEOUT;
1710 return;
2090}
2091
2092static void
1711}
1712
1713static void
2093ste_watchdog(struct ste_softc *sc)
1714ste_watchdog(ifp)
1715 struct ifnet *ifp;
2094{
1716{
2095 struct ifnet *ifp;
1717 struct ste_softc *sc;
2096
1718
2097 ifp = sc->ste_ifp;
2098 STE_LOCK_ASSERT(sc);
1719 sc = ifp->if_softc;
1720 STE_LOCK(sc);
2099
1721
2100 if (sc->ste_timer == 0 || --sc->ste_timer)
2101 return;
2102
2103 ifp->if_oerrors++;
2104 if_printf(ifp, "watchdog timeout\n");
2105
1722 ifp->if_oerrors++;
1723 if_printf(ifp, "watchdog timeout\n");
1724
2106 ste_txeof(sc);
2107 ste_txeoc(sc);
1725 ste_txeoc(sc);
2108 ste_rxeof(sc, -1);
2109 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1726 ste_txeof(sc);
1727 ste_rxeoc(sc);
1728 ste_rxeof(sc);
1729 ste_reset(sc);
2110 ste_init_locked(sc);
2111
2112 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2113 ste_start_locked(ifp);
1730 ste_init_locked(sc);
1731
1732 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1733 ste_start_locked(ifp);
2114}
1734 STE_UNLOCK(sc);
2115
1735
2116static int
2117ste_shutdown(device_t dev)
2118{
2119
2120 return (ste_suspend(dev));
1736 return;
2121}
2122
2123static int
1737}
1738
1739static int
2124ste_suspend(device_t dev)
1740ste_shutdown(dev)
1741 device_t dev;
2125{
1742{
2126 struct ste_softc *sc;
1743 struct ste_softc *sc;
2127
2128 sc = device_get_softc(dev);
2129
2130 STE_LOCK(sc);
2131 ste_stop(sc);
1744
1745 sc = device_get_softc(dev);
1746
1747 STE_LOCK(sc);
1748 ste_stop(sc);
2132 ste_setwol(sc);
2133 STE_UNLOCK(sc);
2134
2135 return (0);
2136}
1749 STE_UNLOCK(sc);
1750
1751 return (0);
1752}
2137
2138static int
2139ste_resume(device_t dev)
2140{
2141 struct ste_softc *sc;
2142 struct ifnet *ifp;
2143 int pmc;
2144 uint16_t pmstat;
2145
2146 sc = device_get_softc(dev);
2147 STE_LOCK(sc);
2148 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
2149 /* Disable PME and clear PME status. */
2150 pmstat = pci_read_config(sc->ste_dev,
2151 pmc + PCIR_POWER_STATUS, 2);
2152 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2153 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2154 pci_write_config(sc->ste_dev,
2155 pmc + PCIR_POWER_STATUS, pmstat, 2);
2156 }
2157 }
2158 ifp = sc->ste_ifp;
2159 if ((ifp->if_flags & IFF_UP) != 0) {
2160 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2161 ste_init_locked(sc);
2162 }
2163 STE_UNLOCK(sc);
2164
2165 return (0);
2166}
2167
2168#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2169 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2170#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2171 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2172
2173static void
2174ste_sysctl_node(struct ste_softc *sc)
2175{
2176 struct sysctl_ctx_list *ctx;
2177 struct sysctl_oid_list *child, *parent;
2178 struct sysctl_oid *tree;
2179 struct ste_hw_stats *stats;
2180
2181 stats = &sc->ste_stats;
2182 ctx = device_get_sysctl_ctx(sc->ste_dev);
2183 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2184
2185 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
2186 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
2187 /* Pull in device tunables. */
2188 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
2189 resource_int_value(device_get_name(sc->ste_dev),
2190 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
2191
2192 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2193 NULL, "STE statistics");
2194 parent = SYSCTL_CHILDREN(tree);
2195
2196 /* Rx statistics. */
2197 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2198 NULL, "Rx MAC statistics");
2199 child = SYSCTL_CHILDREN(tree);
2200 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2201 &stats->rx_bytes, "Good octets");
2202 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2203 &stats->rx_frames, "Good frames");
2204 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2205 &stats->rx_bcast_frames, "Good broadcast frames");
2206 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2207 &stats->rx_mcast_frames, "Good multicast frames");
2208 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2209 &stats->rx_lost_frames, "Lost frames");
2210
2211 /* Tx statistics. */
2212 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2213 NULL, "Tx MAC statistics");
2214 child = SYSCTL_CHILDREN(tree);
2215 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2216 &stats->tx_bytes, "Good octets");
2217 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2218 &stats->tx_frames, "Good frames");
2219 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2220 &stats->tx_bcast_frames, "Good broadcast frames");
2221 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2222 &stats->tx_mcast_frames, "Good multicast frames");
2223 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2224 &stats->tx_carrsense_errs, "Carrier sense errors");
2225 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2226 &stats->tx_single_colls, "Single collisions");
2227 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2228 &stats->tx_multi_colls, "Multiple collisions");
2229 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2230 &stats->tx_late_colls, "Late collisions");
2231 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2232 &stats->tx_frames_defered, "Frames with deferrals");
2233 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2234 &stats->tx_excess_defers, "Frames with excessive derferrals");
2235 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2236 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2237}
2238
2239#undef STE_SYSCTL_STAT_ADD32
2240#undef STE_SYSCTL_STAT_ADD64
2241
2242static void
2243ste_setwol(struct ste_softc *sc)
2244{
2245 struct ifnet *ifp;
2246 uint16_t pmstat;
2247 uint8_t val;
2248 int pmc;
2249
2250 STE_LOCK_ASSERT(sc);
2251
2252 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
2253 /* Disable WOL. */
2254 CSR_READ_1(sc, STE_WAKE_EVENT);
2255 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
2256 return;
2257 }
2258
2259 ifp = sc->ste_ifp;
2260 val = CSR_READ_1(sc, STE_WAKE_EVENT);
2261 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
2262 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
2263 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2264 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
2265 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
2266 /* Request PME. */
2267 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
2268 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2269 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2270 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2271 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2272}