| sdhci_xenon.h (3611ec604864a7d4dcc9a3ea898c80eb35eef8a0) | sdhci_xenon.h (4fa977f854e27c93c22acfa6a3ba38f5c4959e15) |
|---|---|
| 1/*- 2 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41 42#define XENON_SYS_EXT_OP_CTRL 0x010C 43#define XENON_MASK_CMD_CONFLICT_ERR (1 << 8) 44 45#define XENON_SLOT_EMMC_CTRL 0x0130 46#define XENON_ENABLE_DATA_STROBE (1 << 24) 47#define XENON_ENABLE_RESP_STROBE (1 << 25) 48 | 1/*- 2 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41 42#define XENON_SYS_EXT_OP_CTRL 0x010C 43#define XENON_MASK_CMD_CONFLICT_ERR (1 << 8) 44 45#define XENON_SLOT_EMMC_CTRL 0x0130 46#define XENON_ENABLE_DATA_STROBE (1 << 24) 47#define XENON_ENABLE_RESP_STROBE (1 << 25) 48 |
| 49/* Custom HS200 / HS400 Mode Select values in SDHCI_HOST_CONTROL2 register. */ 50#define XENON_CTRL2_MMC_HS200 0x5 51#define XENON_CTRL2_MMC_HS400 0x6 52 |
|
| 49/* eMMC PHY */ 50#define XENON_EMMC_PHY_REG_BASE 0x170 51 52#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE 53#define XENON_SAMPL_INV_QSP_PHASE_SELECT (1 << 18) 54#define XENON_TIMING_ADJUST_SDIO_MODE (1 << 28) 55#define XENON_TIMING_ADJUST_SLOW_MODE (1 << 29) 56#define XENON_PHY_INITIALIZATION (1U << 31) --- 44 unchanged lines hidden --- | 53/* eMMC PHY */ 54#define XENON_EMMC_PHY_REG_BASE 0x170 55 56#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE 57#define XENON_SAMPL_INV_QSP_PHASE_SELECT (1 << 18) 58#define XENON_TIMING_ADJUST_SDIO_MODE (1 << 28) 59#define XENON_TIMING_ADJUST_SLOW_MODE (1 << 29) 60#define XENON_PHY_INITIALIZATION (1U << 31) --- 44 unchanged lines hidden --- |