rt2860reg.h (3b8f08459569bf0faa21473e5cec2491e95c9349) rt2860reg.h (6fc44dab1979102b0fca53bb5a723fc77c62934d)
1/*-
2 * Copyright (c) 2007 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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694/* possible flags for MCU command RT2860_MCU_CMD_LEDS */
695#define RT2860_LED_RADIO (1 << 13)
696#define RT2860_LED_LINK_2GHZ (1 << 14)
697#define RT2860_LED_LINK_5GHZ (1 << 15)
698
699
700/* possible flags for RT3020 RF register 1 */
701#define RT3070_RF_BLOCK (1 << 0)
1/*-
2 * Copyright (c) 2007 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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694/* possible flags for MCU command RT2860_MCU_CMD_LEDS */
695#define RT2860_LED_RADIO (1 << 13)
696#define RT2860_LED_LINK_2GHZ (1 << 14)
697#define RT2860_LED_LINK_5GHZ (1 << 15)
698
699
700/* possible flags for RT3020 RF register 1 */
701#define RT3070_RF_BLOCK (1 << 0)
702#define RT3070_PLL_PD (1 << 1)
702#define RT3070_RX0_PD (1 << 2)
703#define RT3070_TX0_PD (1 << 3)
704#define RT3070_RX1_PD (1 << 4)
705#define RT3070_TX1_PD (1 << 5)
706#define RT3070_RX2_PD (1 << 6)
707#define RT3070_TX2_PD (1 << 7)
708
709/* possible flags for RT3020 RF register 7 */

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745#define RT3593_CP_IC_MASK 0xe0
746#define RT3593_CP_IC_SHIFT 5
747
748/* possible flags for RT3053 RF register 46 */
749#define RT3593_RX_CTB (1 << 5)
750
751#define RT3090_DEF_LNA 10
752
703#define RT3070_RX0_PD (1 << 2)
704#define RT3070_TX0_PD (1 << 3)
705#define RT3070_RX1_PD (1 << 4)
706#define RT3070_TX1_PD (1 << 5)
707#define RT3070_RX2_PD (1 << 6)
708#define RT3070_TX2_PD (1 << 7)
709
710/* possible flags for RT3020 RF register 7 */

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746#define RT3593_CP_IC_MASK 0xe0
747#define RT3593_CP_IC_SHIFT 5
748
749/* possible flags for RT3053 RF register 46 */
750#define RT3593_RX_CTB (1 << 5)
751
752#define RT3090_DEF_LNA 10
753
754/* possible flags for RT5390 RF register 38 */
755#define RT5390_RX_LO1 (1 << 5)
756
757/* possible flags for RT5390 RF register 39 */
758#define RT5390_RX_LO2 (1 << 7)
759
760/* possible flags for RT5390 RF register 42 */
761#define RT5390_RX_CTB (1 << 6)
762
763/* possible flags for RT5390 BBP register 4 */
764#define RT5390_MAC_IF_CTRL (1 << 6)
765
766/* possible flags for RT5390 BBP register 105 */
767#define RT5390_MLD (1 << 2)
768#define RT5390_SIG_MODULATION (1 << 3)
769
753/* RT2860 TX descriptor */
754struct rt2860_txd {
755 uint32_t sdp0; /* Segment Data Pointer 0 */
756 uint16_t sdl1; /* Segment Data Length 1 */
757#define RT2860_TX_BURST (1 << 15)
758#define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */
759
760 uint16_t sdl0; /* Segment Data Length 0 */

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889#define RT2860_RF_2750 4 /* dual-band 1T2R */
890#define RT3070_RF_3020 5 /* 1T1R */
891#define RT3070_RF_2020 6 /* b/g */
892#define RT3070_RF_3021 7 /* 1T2R */
893#define RT3070_RF_3022 8 /* 2T2R */
894#define RT3070_RF_3052 9 /* dual-band 2T2R */
895#define RT3070_RF_3320 11 /* 1T1R */
896#define RT3070_RF_3053 13 /* dual-band 3T3R */
770/* RT2860 TX descriptor */
771struct rt2860_txd {
772 uint32_t sdp0; /* Segment Data Pointer 0 */
773 uint16_t sdl1; /* Segment Data Length 1 */
774#define RT2860_TX_BURST (1 << 15)
775#define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */
776
777 uint16_t sdl0; /* Segment Data Length 0 */

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906#define RT2860_RF_2750 4 /* dual-band 1T2R */
907#define RT3070_RF_3020 5 /* 1T1R */
908#define RT3070_RF_2020 6 /* b/g */
909#define RT3070_RF_3021 7 /* 1T2R */
910#define RT3070_RF_3022 8 /* 2T2R */
911#define RT3070_RF_3052 9 /* dual-band 2T2R */
912#define RT3070_RF_3320 11 /* 1T1R */
913#define RT3070_RF_3053 13 /* dual-band 3T3R */
914#define RT5390_RF_5390 15 /* b/g/n */
897
898/* USB commands for RT2870 only */
899#define RT2870_RESET 1
900#define RT2870_WRITE_2 2
901#define RT2870_WRITE_REGION_1 6
902#define RT2870_READ_REGION_1 7
903#define RT2870_EEPROM_READ 9
904

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1001 DELAY(RT2860_EEPROM_DELAY); \
1002} while (/* CONSTCOND */0)
1003
1004/*
1005 * Default values for MAC registers; values taken from the reference driver.
1006 */
1007#define RT2860_DEF_MAC \
1008 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
915
916/* USB commands for RT2870 only */
917#define RT2870_RESET 1
918#define RT2870_WRITE_2 2
919#define RT2870_WRITE_REGION_1 6
920#define RT2870_READ_REGION_1 7
921#define RT2870_EEPROM_READ 9
922

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1019 DELAY(RT2860_EEPROM_DELAY); \
1020} while (/* CONSTCOND */0)
1021
1022/*
1023 * Default values for MAC registers; values taken from the reference driver.
1024 */
1025#define RT2860_DEF_MAC \
1026 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
1027 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \
1009 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
1010 { RT2860_HT_BASIC_RATE, 0x00008003 }, \
1011 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
1028 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
1029 { RT2860_HT_BASIC_RATE, 0x00008003 }, \
1030 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
1031 { RT2860_RX_FILTR_CFG, 0x00017f97 }, \
1012 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
1013 { RT2860_TX_SW_CFG0, 0x00000000 }, \
1014 { RT2860_TX_SW_CFG1, 0x00080606 }, \
1015 { RT2860_TX_LINK_CFG, 0x00001020 }, \
1016 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
1032 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
1033 { RT2860_TX_SW_CFG0, 0x00000000 }, \
1034 { RT2860_TX_SW_CFG1, 0x00080606 }, \
1035 { RT2860_TX_LINK_CFG, 0x00001020 }, \
1036 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
1037 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \
1017 { RT2860_LED_CFG, 0x7f031e46 }, \
1018 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
1019 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
1020 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
1021 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
1022 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
1023 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
1024 { RT2860_CCK_PROT_CFG, 0x05740003 }, \
1025 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
1026 { RT2860_GF20_PROT_CFG, 0x01744004 }, \
1027 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
1028 { RT2860_MM20_PROT_CFG, 0x01744004 }, \
1029 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \
1030 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
1038 { RT2860_LED_CFG, 0x7f031e46 }, \
1039 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
1040 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
1041 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
1042 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
1043 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
1044 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
1045 { RT2860_CCK_PROT_CFG, 0x05740003 }, \
1046 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
1047 { RT2860_GF20_PROT_CFG, 0x01744004 }, \
1048 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
1049 { RT2860_MM20_PROT_CFG, 0x01744004 }, \
1050 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \
1051 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
1031 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
1032 { RT2860_TX_RTS_CFG, 0x00092b20 }, \
1033 { RT2860_EXP_ACK_TIME, 0x002400ca }, \
1052 { RT2860_TX_RTS_CFG, 0x00092b20 }, \
1053 { RT2860_EXP_ACK_TIME, 0x002400ca }, \
1034 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
1035 { RT2860_PWR_PIN_CFG, 0x00000003 }
1036
1037/* XXX only a few registers differ from above, try to merge? */
1038#define RT2870_DEF_MAC \
1039 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
1040 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
1041 { RT2860_HT_BASIC_RATE, 0x00008003 }, \
1042 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
1043 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
1044 { RT2860_TX_SW_CFG0, 0x00000000 }, \
1045 { RT2860_TX_SW_CFG1, 0x00080606 }, \
1046 { RT2860_TX_LINK_CFG, 0x00001020 }, \
1047 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
1048 { RT2860_LED_CFG, 0x7f031e46 }, \
1049 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
1050 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
1051 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
1052 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
1053 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
1054 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
1055 { RT2860_CCK_PROT_CFG, 0x05740003 }, \
1056 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
1057 { RT2860_PBF_CFG, 0x00f40006 }, \
1058 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \
1059 { RT2860_GF20_PROT_CFG, 0x01744004 }, \
1060 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
1061 { RT2860_MM20_PROT_CFG, 0x01744004 }, \
1062 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \
1063 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
1064 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
1054 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
1065 { RT2860_TX_RTS_CFG, 0x00092b20 }, \
1066 { RT2860_EXP_ACK_TIME, 0x002400ca }, \
1067 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
1068 { RT2860_PWR_PIN_CFG, 0x00000003 }
1069
1070/*
1071 * Default values for BBP registers; values taken from the reference driver.
1072 */
1073#define RT2860_DEF_BBP \
1074 { 65, 0x2c }, \
1075 { 66, 0x38 }, \
1055 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
1056 { RT2860_PWR_PIN_CFG, 0x00000003 }
1057
1058/*
1059 * Default values for BBP registers; values taken from the reference driver.
1060 */
1061#define RT2860_DEF_BBP \
1062 { 65, 0x2c }, \
1063 { 66, 0x38 }, \
1064 { 68, 0x0b }, \
1076 { 69, 0x12 }, \
1077 { 70, 0x0a }, \
1078 { 73, 0x10 }, \
1079 { 81, 0x37 }, \
1080 { 82, 0x62 }, \
1081 { 83, 0x6a }, \
1082 { 84, 0x99 }, \
1083 { 86, 0x00 }, \
1084 { 91, 0x04 }, \
1085 { 92, 0x00 }, \
1086 { 103, 0x00 }, \
1087 { 105, 0x05 }, \
1088 { 106, 0x35 }
1089
1065 { 69, 0x12 }, \
1066 { 70, 0x0a }, \
1067 { 73, 0x10 }, \
1068 { 81, 0x37 }, \
1069 { 82, 0x62 }, \
1070 { 83, 0x6a }, \
1071 { 84, 0x99 }, \
1072 { 86, 0x00 }, \
1073 { 91, 0x04 }, \
1074 { 92, 0x00 }, \
1075 { 103, 0x00 }, \
1076 { 105, 0x05 }, \
1077 { 106, 0x35 }
1078
1079#define RT5390_DEF_BBP \
1080 { 31, 0x08 }, \
1081 { 65, 0x2c }, \
1082 { 66, 0x38 }, \
1083 { 68, 0x0b }, \
1084 { 69, 0x12 }, \
1085 { 70, 0x0a }, \
1086 { 73, 0x13 }, \
1087 { 75, 0x46 }, \
1088 { 76, 0x28 }, \
1089 { 77, 0x59 }, \
1090 { 81, 0x37 }, \
1091 { 82, 0x62 }, \
1092 { 83, 0x7a }, \
1093 { 84, 0x19 }, \
1094 { 86, 0x38 }, \
1095 { 91, 0x04 }, \
1096 { 92, 0x02 }, \
1097 { 103, 0xc0 }, \
1098 { 104, 0x92 }, \
1099 { 105, 0x3c }, \
1100 { 106, 0x03 }, \
1101 { 128, 0x12 }, \
1102
1090/*
1091 * Default settings for RF registers; values derived from the reference driver.
1092 */
1093#define RT2860_RF2850 \
1094 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \
1095 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \
1096 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \
1097 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \

--- 101 unchanged lines hidden (view full) ---

1199 { 0x61, 0, 5 }, \
1200 { 0x61, 0, 7 }, \
1201 { 0x61, 0, 9 }
1202
1203#define RT3070_DEF_RF \
1204 { 4, 0x40 }, \
1205 { 5, 0x03 }, \
1206 { 6, 0x02 }, \
1103/*
1104 * Default settings for RF registers; values derived from the reference driver.
1105 */
1106#define RT2860_RF2850 \
1107 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \
1108 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \
1109 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \
1110 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \

--- 101 unchanged lines hidden (view full) ---

1212 { 0x61, 0, 5 }, \
1213 { 0x61, 0, 7 }, \
1214 { 0x61, 0, 9 }
1215
1216#define RT3070_DEF_RF \
1217 { 4, 0x40 }, \
1218 { 5, 0x03 }, \
1219 { 6, 0x02 }, \
1207 { 7, 0x70 }, \
1220 { 7, 0x60 }, \
1208 { 9, 0x0f }, \
1209 { 10, 0x41 }, \
1210 { 11, 0x21 }, \
1211 { 12, 0x7b }, \
1212 { 14, 0x90 }, \
1213 { 15, 0x58 }, \
1214 { 16, 0xb3 }, \
1215 { 17, 0x92 }, \
1216 { 18, 0x2c }, \
1217 { 19, 0x02 }, \
1218 { 20, 0xba }, \
1219 { 21, 0xdb }, \
1220 { 24, 0x16 }, \
1221 { 25, 0x01 }, \
1222 { 29, 0x1f }
1223
1221 { 9, 0x0f }, \
1222 { 10, 0x41 }, \
1223 { 11, 0x21 }, \
1224 { 12, 0x7b }, \
1225 { 14, 0x90 }, \
1226 { 15, 0x58 }, \
1227 { 16, 0xb3 }, \
1228 { 17, 0x92 }, \
1229 { 18, 0x2c }, \
1230 { 19, 0x02 }, \
1231 { 20, 0xba }, \
1232 { 21, 0xdb }, \
1233 { 24, 0x16 }, \
1234 { 25, 0x01 }, \
1235 { 29, 0x1f }
1236
1224#define RT3572_DEF_RF \
1225 { 0, 0x70 }, \
1226 { 1, 0x81 }, \
1227 { 2, 0xf1 }, \
1228 { 3, 0x02 }, \
1229 { 4, 0x4c }, \
1230 { 5, 0x05 }, \
1231 { 6, 0x4a }, \
1232 { 7, 0xd8 }, \
1233 { 9, 0xc3 }, \
1234 { 10, 0xf1 }, \
1235 { 11, 0xb9 }, \
1236 { 12, 0x70 }, \
1237 { 13, 0x65 }, \
1238 { 14, 0xa0 }, \
1239 { 15, 0x53 }, \
1240 { 16, 0x4c }, \
1241 { 17, 0x23 }, \
1242 { 18, 0xac }, \
1243 { 19, 0x93 }, \
1244 { 20, 0xb3 }, \
1245 { 21, 0xd0 }, \
1246 { 22, 0x00 }, \
1247 { 23, 0x3c }, \
1248 { 24, 0x16 }, \
1249 { 25, 0x15 }, \
1250 { 26, 0x85 }, \
1251 { 27, 0x00 }, \
1237#define RT5390_DEF_RF \
1238 { 1, 0x0f }, \
1239 { 2, 0x80 }, \
1240 { 3, 0x88 }, \
1241 { 5, 0x10 }, \
1242 { 6, 0xe0 }, \
1243 { 7, 0x00 }, \
1244 { 10, 0x53 }, \
1245 { 11, 0x4a }, \
1246 { 12, 0x46 }, \
1247 { 13, 0x9f }, \
1248 { 14, 0x00 }, \
1249 { 15, 0x00 }, \
1250 { 16, 0x00 }, \
1251 { 18, 0x03 }, \
1252 { 19, 0x00 }, \
1253 { 20, 0x00 }, \
1254 { 21, 0x00 }, \
1255 { 22, 0x20 }, \
1256 { 23, 0x00 }, \
1257 { 24, 0x00 }, \
1258 { 25, 0x80 }, \
1259 { 26, 0x00 }, \
1260 { 27, 0x09 }, \
1252 { 28, 0x00 }, \
1261 { 28, 0x00 }, \
1253 { 29, 0x9b }, \
1254 { 30, 0x09 }, \
1255 { 31, 0x10 }
1262 { 29, 0x10 }, \
1263 { 30, 0x10 }, \
1264 { 31, 0x80 }, \
1265 { 32, 0x80 }, \
1266 { 33, 0x00 }, \
1267 { 34, 0x07 }, \
1268 { 35, 0x12 }, \
1269 { 36, 0x00 }, \
1270 { 37, 0x08 }, \
1271 { 38, 0x85 }, \
1272 { 39, 0x1b }, \
1273 { 40, 0x0b }, \
1274 { 41, 0xbb }, \
1275 { 42, 0xd2 }, \
1276 { 43, 0x9a }, \
1277 { 44, 0x0e }, \
1278 { 45, 0xa2 }, \
1279 { 46, 0x73 }, \
1280 { 47, 0x00 }, \
1281 { 48, 0x10 }, \
1282 { 49, 0x94 }, \
1283 { 52, 0x38 }, \
1284 { 53, 0x00 }, \
1285 { 54, 0x78 }, \
1286 { 55, 0x23 }, \
1287 { 56, 0x22 }, \
1288 { 57, 0x80 }, \
1289 { 58, 0x7f }, \
1290 { 59, 0x07 }, \
1291 { 60, 0x45 }, \
1292 { 61, 0xd1 }, \
1293 { 62, 0x00 }, \
1294 { 63, 0x00 }
1295
1296#define RT5392_DEF_RF \
1297 { 1, 0x17 }, \
1298 { 2, 0x80 }, \
1299 { 3, 0x88 }, \
1300 { 5, 0x10 }, \
1301 { 6, 0xe0 }, \
1302 { 7, 0x00 }, \
1303 { 10, 0x53 }, \
1304 { 11, 0x4a }, \
1305 { 12, 0x46 }, \
1306 { 13, 0x9f }, \
1307 { 14, 0x00 }, \
1308 { 15, 0x00 }, \
1309 { 16, 0x00 }, \
1310 { 18, 0x03 }, \
1311 { 19, 0x4d }, \
1312 { 20, 0x00 }, \
1313 { 21, 0x8d }, \
1314 { 22, 0x20 }, \
1315 { 23, 0x0b }, \
1316 { 24, 0x44 }, \
1317 { 25, 0x80 }, \
1318 { 26, 0x82 }, \
1319 { 27, 0x09 }, \
1320 { 28, 0x00 }, \
1321 { 29, 0x10 }, \
1322 { 30, 0x10 }, \
1323 { 31, 0x80 }, \
1324 { 32, 0x80 }, \
1325 { 33, 0xc0 }, \
1326 { 34, 0x07 }, \
1327 { 35, 0x12 }, \
1328 { 36, 0x00 }, \
1329 { 37, 0x08 }, \
1330 { 38, 0x89 }, \
1331 { 39, 0x1b }, \
1332 { 40, 0x0f }, \
1333 { 41, 0xbb }, \
1334 { 42, 0xd5 }, \
1335 { 43, 0x9b }, \
1336 { 44, 0x0e }, \
1337 { 45, 0xa2 }, \
1338 { 46, 0x73 }, \
1339 { 47, 0x0c }, \
1340 { 48, 0x10 }, \
1341 { 49, 0x94 }, \
1342 { 50, 0x94 }, \
1343 { 51, 0x3a }, \
1344 { 52, 0x48 }, \
1345 { 53, 0x44 }, \
1346 { 54, 0x38 }, \
1347 { 55, 0x43 }, \
1348 { 56, 0xa1 }, \
1349 { 57, 0x00 }, \
1350 { 58, 0x39 }, \
1351 { 59, 0x07 }, \
1352 { 60, 0x45 }, \
1353 { 61, 0x91 }, \
1354 { 62, 0x39 }, \
1355 { 63, 0x00 }