ppb_base.c (24ef1eb1432b587d5c88706e50485f012ca9dfda) ppb_base.c (bc35c17446fab005a7e11b67b9004736f1c8498b)
1/*-
2 * Copyright (c) 1997, 1998 Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 1997, 1998 Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $Id: ppb_base.c,v 1.4 1998/08/03 19:14:31 msmith Exp $
26 * $Id: ppb_base.c,v 1.5 1998/09/13 18:26:26 nsouch Exp $
27 *
28 */
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
27 *
28 */
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/kernel.h>
32#include <machine/clock.h>
32
33#include <dev/ppbus/ppbconf.h>
34
35/*
36 * ppb_intr()
37 *
38 * Function called by ppcintr() when an intr occurs.
39 */

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65 * Polls the device
66 *
67 * max is a delay in 10-milliseconds
68 */
69int
70ppb_poll_device(struct ppb_device *dev, int max,
71 char mask, char status, int how)
72{
33
34#include <dev/ppbus/ppbconf.h>
35
36/*
37 * ppb_intr()
38 *
39 * Function called by ppcintr() when an intr occurs.
40 */

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66 * Polls the device
67 *
68 * max is a delay in 10-milliseconds
69 */
70int
71ppb_poll_device(struct ppb_device *dev, int max,
72 char mask, char status, int how)
73{
73 int i, error;
74 int i, j, error;
75 char r;
74
76
75 for (i = 0; i < max; i++) {
77 /* try at least up to 10ms */
78 for (j = 0; j < ((how & PPB_POLL) ? max : 1); j++) {
79 for (i = 0; i < 10000; i++) {
80 r = ppb_rstr(dev);
81 DELAY(1);
82 if ((r & mask) == status)
83 return (0);
84 }
85 }
86
87 if (!(how & PPB_POLL)) {
88 for (i = 0; max == PPB_FOREVER || i < max-1; i++) {
76 if ((ppb_rstr(dev) & mask) == status)
77 return (0);
78
79 switch (how) {
80 case PPB_NOINTR:
81 /* wait 10 ms */
89 if ((ppb_rstr(dev) & mask) == status)
90 return (0);
91
92 switch (how) {
93 case PPB_NOINTR:
94 /* wait 10 ms */
82 if ((error = tsleep((caddr_t)dev, PPBPRI,
83 "ppbpoll", hz/100)))
84 return (error);
95 tsleep((caddr_t)dev, PPBPRI, "ppbpoll", hz/100);
85 break;
86
87 case PPB_INTR:
88 default:
89 /* wait 10 ms */
90 if ((error = tsleep((caddr_t)dev, PPBPRI | PCATCH,
96 break;
97
98 case PPB_INTR:
99 default:
100 /* wait 10 ms */
101 if ((error = tsleep((caddr_t)dev, PPBPRI | PCATCH,
91 "ppbpoll", hz/100)))
102 "ppbpoll", hz/100)) != EWOULDBLOCK)
92 return (error);
93 break;
94 }
103 return (error);
104 break;
105 }
106 }
95 }
96
97 return (EWOULDBLOCK);
98}
99
100/*
101 * ppb_set_mode()
102 *
103 * Set the operating mode of the chipset
104 */
105int
106ppb_set_mode(struct ppb_device *dev, int mode)
107{
108 struct ppb_data *ppb = dev->ppb;
109 int old_mode = ppb_get_mode(dev);
110
107 }
108
109 return (EWOULDBLOCK);
110}
111
112/*
113 * ppb_set_mode()
114 *
115 * Set the operating mode of the chipset
116 */
117int
118ppb_set_mode(struct ppb_device *dev, int mode)
119{
120 struct ppb_data *ppb = dev->ppb;
121 int old_mode = ppb_get_mode(dev);
122
111 if ((*ppb->ppb_link->adapter->setmode)(dev->id_unit, mode))
123 if ((*ppb->ppb_link->adapter->setmode)(
124 ppb->ppb_link->adapter_unit, mode))
112 return (-1);
113
114 /* XXX yet device mode = ppbus mode = chipset mode */
125 return (-1);
126
127 /* XXX yet device mode = ppbus mode = chipset mode */
115 dev->mode = ppb->mode = mode;
128 dev->mode = ppb->mode = (mode & PPB_MASK);
116
117 return (old_mode);
118}
119
120/*
129
130 return (old_mode);
131}
132
133/*
134 * ppb_write()
135 *
136 * Write charaters to the port
137 */
138int
139ppb_write(struct ppb_device *dev, char *buf, int len, int how)
140{
141 struct ppb_data *ppb = dev->ppb;
142
143 return (ppb->ppb_link->adapter->write(ppb->ppb_link->adapter_unit,
144 buf, len, how));
145}
146
147/*
121 * ppb_reset_epp_timeout()
122 *
123 * Reset the EPP timeout bit in the status register
124 */
125int
126ppb_reset_epp_timeout(struct ppb_device *dev)
127{
128 struct ppb_data *ppb = dev->ppb;
129
130 if (ppb->ppb_owner != dev)
131 return (EACCES);
132
148 * ppb_reset_epp_timeout()
149 *
150 * Reset the EPP timeout bit in the status register
151 */
152int
153ppb_reset_epp_timeout(struct ppb_device *dev)
154{
155 struct ppb_data *ppb = dev->ppb;
156
157 if (ppb->ppb_owner != dev)
158 return (EACCES);
159
133 (*ppb->ppb_link->adapter->reset_epp_timeout)(dev->id_unit);
160 (*ppb->ppb_link->adapter->reset_epp_timeout)(ppb->ppb_link->adapter_unit);
134
135 return (0);
136}
137
138/*
139 * ppb_ecp_sync()
140 *
141 * Wait for the ECP FIFO to be empty
142 */
143int
144ppb_ecp_sync(struct ppb_device *dev)
145{
146 struct ppb_data *ppb = dev->ppb;
147
148 if (ppb->ppb_owner != dev)
149 return (EACCES);
150
161
162 return (0);
163}
164
165/*
166 * ppb_ecp_sync()
167 *
168 * Wait for the ECP FIFO to be empty
169 */
170int
171ppb_ecp_sync(struct ppb_device *dev)
172{
173 struct ppb_data *ppb = dev->ppb;
174
175 if (ppb->ppb_owner != dev)
176 return (EACCES);
177
151 (*ppb->ppb_link->adapter->ecp_sync)(dev->id_unit);
178 (*ppb->ppb_link->adapter->ecp_sync)(ppb->ppb_link->adapter_unit);
152
153 return (0);
154}
155
156/*
157 * ppb_get_status()
158 *
159 * Read the status register and update the status info

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180 return (0);
181}
182
183/*
184 * ppb_get_status()
185 *
186 * Read the status register and update the status info

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