ixl.h (6d011ad5f677a2d2c99eb1d848089000ea3f463c) ixl.h (4294f337b02257f24cc0177c5031abea7fdc3d75)
1/******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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31
32******************************************************************************/
33/*$FreeBSD$*/
34
35
36#ifndef _IXL_H_
37#define _IXL_H_
38
1/******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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31
32******************************************************************************/
33/*$FreeBSD$*/
34
35
36#ifndef _IXL_H_
37#define _IXL_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/buf_ring.h>
43#include <sys/mbuf.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>

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85#include <sys/proc.h>
86#include <sys/sysctl.h>
87#include <sys/endian.h>
88#include <sys/taskqueue.h>
89#include <sys/pcpu.h>
90#include <sys/smp.h>
91#include <sys/sbuf.h>
92#include <machine/smp.h>
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/buf_ring.h>
42#include <sys/mbuf.h>
43#include <sys/protosw.h>
44#include <sys/socket.h>
45#include <sys/malloc.h>
46#include <sys/kernel.h>

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84#include <sys/proc.h>
85#include <sys/sysctl.h>
86#include <sys/endian.h>
87#include <sys/taskqueue.h>
88#include <sys/pcpu.h>
89#include <sys/smp.h>
90#include <sys/sbuf.h>
91#include <machine/smp.h>
92#include <machine/stdarg.h>
93
93
94#ifdef PCI_IOV
95#include <sys/nv.h>
96#include <sys/iov_schema.h>
97#include <dev/pci/pci_iov.h>
94#ifdef RSS
95#include <net/rss_config.h>
98#endif
99
96#endif
97
98#include "opt_inet.h"
99#include "opt_inet6.h"
100#include "opt_rss.h"
101
100#include "i40e_type.h"
101#include "i40e_prototype.h"
102
102#include "i40e_type.h"
103#include "i40e_prototype.h"
104
103#if defined(IXL_DEBUG) || defined(IXL_DEBUG_SYSCTL)
104#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
105#define MAC_FORMAT_ARGS(mac_addr) \
106 (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
107 (mac_addr)[4], (mac_addr)[5]
108#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
105#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
106#define MAC_FORMAT_ARGS(mac_addr) \
107 (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
108 (mac_addr)[4], (mac_addr)[5]
109#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
109#endif /* IXL_DEBUG || IXL_DEBUG_SYSCTL */
110
111#ifdef IXL_DEBUG
110
111#ifdef IXL_DEBUG
112/* Enable debug sysctls */
113#ifndef IXL_DEBUG_SYSCTL
114#define IXL_DEBUG_SYSCTL 1
115#endif
116
117#define _DBG_PRINTF(S, ...) printf("%s: " S "\n", __func__, ##__VA_ARGS__)
118#define _DEV_DBG_PRINTF(dev, S, ...) device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__)
119#define _IF_DBG_PRINTF(ifp, S, ...) if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__)
120
121/* Defines for printing generic debug information */
122#define DPRINTF(...) _DBG_PRINTF(__VA_ARGS__)
123#define DDPRINTF(...) _DEV_DBG_PRINTF(__VA_ARGS__)

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152#define INIT_DBG_DEV(...)
153#define INIT_DBG_IF(...)
154#define IOCTL_DEBUGOUT(...)
155#define IOCTL_DBG_IF2(...)
156#define IOCTL_DBG_IF(...)
157#define HW_DEBUGOUT(...)
158#endif /* IXL_DEBUG */
159
112
113#define _DBG_PRINTF(S, ...) printf("%s: " S "\n", __func__, ##__VA_ARGS__)
114#define _DEV_DBG_PRINTF(dev, S, ...) device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__)
115#define _IF_DBG_PRINTF(ifp, S, ...) if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__)
116
117/* Defines for printing generic debug information */
118#define DPRINTF(...) _DBG_PRINTF(__VA_ARGS__)
119#define DDPRINTF(...) _DEV_DBG_PRINTF(__VA_ARGS__)

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148#define INIT_DBG_DEV(...)
149#define INIT_DBG_IF(...)
150#define IOCTL_DEBUGOUT(...)
151#define IOCTL_DBG_IF2(...)
152#define IOCTL_DBG_IF(...)
153#define HW_DEBUGOUT(...)
154#endif /* IXL_DEBUG */
155
156enum ixl_dbg_mask {
157 IXL_DBG_INFO = 0x00000001,
158 IXL_DBG_EN_DIS = 0x00000002,
159 IXL_DBG_AQ = 0x00000004,
160 IXL_DBG_NVMUPD = 0x00000008,
161
162 IXL_DBG_IOCTL_KNOWN = 0x00000010,
163 IXL_DBG_IOCTL_UNKNOWN = 0x00000020,
164 IXL_DBG_IOCTL_ALL = 0x00000030,
165
166 I40E_DEBUG_RSS = 0x00000100,
167
168 IXL_DBG_IOV = 0x00001000,
169 IXL_DBG_IOV_VC = 0x00002000,
170
171 IXL_DBG_SWITCH_INFO = 0x00010000,
172
173 IXL_DBG_ALL = 0xFFFFFFFF
174};
175
160/* Tunables */
161
162/*
163 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the
164 * number of tx/rx descriptors allocated by the driver. Increasing this
165 * value allows the driver to queue more operations.
166 *
167 * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes.
168 * The driver currently always uses 32 byte Rx descriptors.
169 */
176/* Tunables */
177
178/*
179 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the
180 * number of tx/rx descriptors allocated by the driver. Increasing this
181 * value allows the driver to queue more operations.
182 *
183 * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes.
184 * The driver currently always uses 32 byte Rx descriptors.
185 */
170#define DEFAULT_RING 1024
171#define PERFORM_RING 2048
172#define MAX_RING 4096
173#define MIN_RING 32
186#define DEFAULT_RING 1024
187#define IXL_MAX_RING 8160
188#define IXL_MIN_RING 32
189#define IXL_RING_INCREMENT 32
174
190
191#define IXL_AQ_LEN 256
192#define IXL_AQ_LEN_MAX 1024
193
175/*
176** Default number of entries in Tx queue buf_ring.
177*/
194/*
195** Default number of entries in Tx queue buf_ring.
196*/
178#define SMALL_TXBRSZ 4096
179/* This may require mbuf cluster tuning */
180#define DEFAULT_TXBRSZ (SMALL_TXBRSZ * SMALL_TXBRSZ)
197#define DEFAULT_TXBRSZ 4096
181
182/* Alignment for rings */
198
199/* Alignment for rings */
183#define DBA_ALIGN 128
200#define DBA_ALIGN 128
184
185/*
186 * This is the max watchdog interval, ie. the time that can
187 * pass between any two TX clean operations, such only happening
188 * when the TX hardware is functioning.
189 */
201
202/*
203 * This is the max watchdog interval, ie. the time that can
204 * pass between any two TX clean operations, such only happening
205 * when the TX hardware is functioning.
206 */
190#define IXL_WATCHDOG (10 * hz)
207#define IXL_WATCHDOG (10 * hz)
191
192/*
193 * This parameters control when the driver calls the routine to reclaim
194 * transmit descriptors.
195 */
196#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8)
197#define IXL_TX_OP_THRESHOLD (que->num_desc / 32)
198
208
209/*
210 * This parameters control when the driver calls the routine to reclaim
211 * transmit descriptors.
212 */
213#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8)
214#define IXL_TX_OP_THRESHOLD (que->num_desc / 32)
215
199/* Flow control constants */
200#define IXL_FC_PAUSE 0xFFFF
201#define IXL_FC_HI 0x20000
202#define IXL_FC_LO 0x10000
203
204#define MAX_MULTICAST_ADDR 128
205
206#define IXL_BAR 3
207#define IXL_ADM_LIMIT 2
208#define IXL_TSO_SIZE 65535
209#define IXL_AQ_BUF_SZ ((u32) 4096)
210#define IXL_RX_HDR 128
216#define MAX_MULTICAST_ADDR 128
217
218#define IXL_BAR 3
219#define IXL_ADM_LIMIT 2
220#define IXL_TSO_SIZE 65535
221#define IXL_AQ_BUF_SZ ((u32) 4096)
222#define IXL_RX_HDR 128
211/* Controls the length of the Admin Queue */
212#define IXL_AQ_LEN 256
213#define IXL_AQ_LEN_MAX 1024
214#define IXL_AQ_BUFSZ 4096
215#define IXL_RX_LIMIT 512
216#define IXL_RX_ITR 0
217#define IXL_TX_ITR 1
218#define IXL_ITR_NONE 3
219#define IXL_QUEUE_EOL 0x7FF
220#define IXL_MAX_FRAME 9728
221#define IXL_MAX_TX_SEGS 8
223#define IXL_RX_LIMIT 512
224#define IXL_RX_ITR 0
225#define IXL_TX_ITR 1
226#define IXL_ITR_NONE 3
227#define IXL_QUEUE_EOL 0x7FF
228#define IXL_MAX_FRAME 9728
229#define IXL_MAX_TX_SEGS 8
222#define IXL_MAX_TSO_SEGS 66
230#define IXL_MAX_TSO_SEGS 128
223#define IXL_SPARSE_CHAIN 6
224#define IXL_QUEUE_HUNG 0x80000000
231#define IXL_SPARSE_CHAIN 6
232#define IXL_QUEUE_HUNG 0x80000000
225#define IXL_KEYSZ 10
226
233
234#define IXL_RSS_KEY_SIZE_REG 13
235#define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4)
236#define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */
237#define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F
238#define IXL_RSS_VF_LUT_ENTRY_MASK 0xF
239
227#define IXL_VF_MAX_BUFFER 0x3F80
228#define IXL_VF_MAX_HDR_BUFFER 0x840
229#define IXL_VF_MAX_FRAME 0x3FFF
230
240#define IXL_VF_MAX_BUFFER 0x3F80
241#define IXL_VF_MAX_HDR_BUFFER 0x840
242#define IXL_VF_MAX_FRAME 0x3FFF
243
231/* ERJ: hardware can support ~1.5k filters between all functions */
232#define IXL_MAX_FILTERS 256
233#define IXL_MAX_TX_BUSY 10
244/* ERJ: hardware can support ~2k (SW5+) filters between all functions */
245#define IXL_MAX_FILTERS 256
246#define IXL_MAX_TX_BUSY 10
234
235#define IXL_NVM_VERSION_LO_SHIFT 0
236#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT)
237#define IXL_NVM_VERSION_HI_SHIFT 12
238#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT)
239
247
248#define IXL_NVM_VERSION_LO_SHIFT 0
249#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT)
250#define IXL_NVM_VERSION_HI_SHIFT 12
251#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT)
252
240
241/*
242 * Interrupt Moderation parameters
243 */
244#define IXL_MAX_ITR 0x07FF
245#define IXL_ITR_100K 0x0005
246#define IXL_ITR_20K 0x0019
247#define IXL_ITR_8K 0x003E
248#define IXL_ITR_4K 0x007A

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293
294#define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf) ((glb_vf) / 32)
295#define IXL_GLGEN_VFLRSTAT_MASK(glb_vf) (1 << ((glb_vf) % 32))
296
297#define IXL_MAX_ITR_IDX 3
298
299#define IXL_END_OF_INTR_LNKLST 0x7FF
300
253/*
254 * Interrupt Moderation parameters
255 */
256#define IXL_MAX_ITR 0x07FF
257#define IXL_ITR_100K 0x0005
258#define IXL_ITR_20K 0x0019
259#define IXL_ITR_8K 0x003E
260#define IXL_ITR_4K 0x007A

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305
306#define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf) ((glb_vf) / 32)
307#define IXL_GLGEN_VFLRSTAT_MASK(glb_vf) (1 << ((glb_vf) % 32))
308
309#define IXL_MAX_ITR_IDX 3
310
311#define IXL_END_OF_INTR_LNKLST 0x7FF
312
313#define IXL_DEFAULT_RSS_HENA (\
314 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
315 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
316 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
317 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
318 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
319 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
320 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
321 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
322 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
323 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
324 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
325
301#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
302#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
303#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
304#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx)
305#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
306
307#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
308#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)

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332#define IXL_SET_OBYTES(vsi, count) (vsi)->ifp->if_obytes = (count)
333#define IXL_SET_IMCASTS(vsi, count) (vsi)->ifp->if_imcasts = (count)
334#define IXL_SET_OMCASTS(vsi, count) (vsi)->ifp->if_omcasts = (count)
335#define IXL_SET_IQDROPS(vsi, count) (vsi)->ifp->if_iqdrops = (count)
336#define IXL_SET_OQDROPS(vsi, odrops) (vsi)->ifp->if_snd.ifq_drops = (odrops)
337#define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count)
338#endif
339
326#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
327#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
328#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
329#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx)
330#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
331
332#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
333#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)

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357#define IXL_SET_OBYTES(vsi, count) (vsi)->ifp->if_obytes = (count)
358#define IXL_SET_IMCASTS(vsi, count) (vsi)->ifp->if_imcasts = (count)
359#define IXL_SET_OMCASTS(vsi, count) (vsi)->ifp->if_omcasts = (count)
360#define IXL_SET_IQDROPS(vsi, count) (vsi)->ifp->if_iqdrops = (count)
361#define IXL_SET_OQDROPS(vsi, odrops) (vsi)->ifp->if_snd.ifq_drops = (odrops)
362#define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count)
363#endif
364
340/* Pre-10.2 media type compatibility */
341#if __FreeBSD_version < 1002000
342#define IFM_OTHER IFM_UNKNOWN
343#endif
344
345/*
346 *****************************************************************************
347 * vendor_info_array
348 *
349 * This array contains the list of Subvendor/Subdevice IDs on which the driver
350 * should load.
351 *
352 *****************************************************************************

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475 struct taskqueue *tq;
476
477 /* Queue stats */
478 u64 irqs;
479 u64 tso;
480 u64 mbuf_defrag_failed;
481 u64 mbuf_hdr_failed;
482 u64 mbuf_pkt_failed;
365/*
366 *****************************************************************************
367 * vendor_info_array
368 *
369 * This array contains the list of Subvendor/Subdevice IDs on which the driver
370 * should load.
371 *
372 *****************************************************************************

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495 struct taskqueue *tq;
496
497 /* Queue stats */
498 u64 irqs;
499 u64 tso;
500 u64 mbuf_defrag_failed;
501 u64 mbuf_hdr_failed;
502 u64 mbuf_pkt_failed;
483 u64 tx_map_avail;
484 u64 tx_dma_setup;
503 u64 tx_dmamap_failed;
485 u64 dropped_pkts;
486};
487
488/*
504 u64 dropped_pkts;
505};
506
507/*
489** Virtual Station interface:
490** there would be one of these per traffic class/type
491** for now just one, and its embedded in the pf
508** Virtual Station Interface
492*/
493SLIST_HEAD(ixl_ftl_head, ixl_mac_filter);
494struct ixl_vsi {
495 void *back;
496 struct ifnet *ifp;
497 struct device *dev;
498 struct i40e_hw *hw;
499 struct ifmedia media;
500 enum i40e_vsi_type type;
509*/
510SLIST_HEAD(ixl_ftl_head, ixl_mac_filter);
511struct ixl_vsi {
512 void *back;
513 struct ifnet *ifp;
514 struct device *dev;
515 struct i40e_hw *hw;
516 struct ifmedia media;
517 enum i40e_vsi_type type;
501 u64 que_mask;
502 int id;
518 int id;
503 u16 vsi_num;
504 u16 msix_base; /* station base MSIX vector */
505 u16 first_queue;
506 u16 num_queues;
507 u32 rx_itr_setting;
508 u32 tx_itr_setting;
519 u16 num_queues;
520 u32 rx_itr_setting;
521 u32 tx_itr_setting;
522 u16 max_frame_size;
523
509 struct ixl_queue *queues; /* head of queues */
524 struct ixl_queue *queues; /* head of queues */
525
526 u16 vsi_num;
510 bool link_active;
511 u16 seid;
512 u16 uplink_seid;
513 u16 downlink_seid;
527 bool link_active;
528 u16 seid;
529 u16 uplink_seid;
530 u16 downlink_seid;
514 u16 max_frame_size;
515 u16 rss_table_size;
516 u16 rss_size;
517
518 /* MAC/VLAN Filter list */
519 struct ixl_ftl_head ftl;
520 u16 num_macs;
521
531
532 /* MAC/VLAN Filter list */
533 struct ixl_ftl_head ftl;
534 u16 num_macs;
535
536 /* Contains readylist & stat counter id */
522 struct i40e_aqc_vsi_properties_data info;
523
524 eventhandler_tag vlan_attach;
525 eventhandler_tag vlan_detach;
526 u16 num_vlans;
527
528 /* Per-VSI stats from hardware */
529 struct i40e_eth_stats eth_stats;

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560{
561 struct rx_ring *rxr = &que->rxr;
562
563 if (rxr->next_check > rxr->next_refresh)
564 return (rxr->next_check - rxr->next_refresh - 1);
565 else
566 return ((que->num_desc + rxr->next_check) -
567 rxr->next_refresh - 1);
537 struct i40e_aqc_vsi_properties_data info;
538
539 eventhandler_tag vlan_attach;
540 eventhandler_tag vlan_detach;
541 u16 num_vlans;
542
543 /* Per-VSI stats from hardware */
544 struct i40e_eth_stats eth_stats;

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575{
576 struct rx_ring *rxr = &que->rxr;
577
578 if (rxr->next_check > rxr->next_refresh)
579 return (rxr->next_check - rxr->next_refresh - 1);
580 else
581 return ((que->num_desc + rxr->next_check) -
582 rxr->next_refresh - 1);
568}
583}
569
570/*
571** Find the next available unused filter
572*/
573static inline struct ixl_mac_filter *
574ixl_get_filter(struct ixl_vsi *vsi)
575{
576 struct ixl_mac_filter *f;

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596 (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) &&
597 (ea1[4] == ea2[4]) && (ea1[5] == ea2[5]))
598 cmp = TRUE;
599
600 return (cmp);
601}
602
603/*
584
585/*
586** Find the next available unused filter
587*/
588static inline struct ixl_mac_filter *
589ixl_get_filter(struct ixl_vsi *vsi)
590{
591 struct ixl_mac_filter *f;

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611 (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) &&
612 (ea1[4] == ea2[4]) && (ea1[5] == ea2[5]))
613 cmp = TRUE;
614
615 return (cmp);
616}
617
618/*
619 * Return next largest power of 2, unsigned
620 *
621 * Public domain, from Bit Twiddling Hacks
622 */
623static inline u32
624next_power_of_two(u32 n)
625{
626 n--;
627 n |= n >> 1;
628 n |= n >> 2;
629 n |= n >> 4;
630 n |= n >> 8;
631 n |= n >> 16;
632 n++;
633
634 /* Next power of two > 0 is 1 */
635 n += (n == 0);
636
637 return (n);
638}
639
640/*
604 * Info for stats sysctls
605 */
606struct ixl_sysctl_info {
607 u64 *stat;
608 char *name;
609 char *description;
610};
611
641 * Info for stats sysctls
642 */
643struct ixl_sysctl_info {
644 u64 *stat;
645 char *name;
646 char *description;
647};
648
612extern int ixl_atr_rate;
649static uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] =
650 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
613
614/*********************************************************************
615 * TXRX Function prototypes
616 *********************************************************************/
617int ixl_allocate_tx_data(struct ixl_queue *);
618int ixl_allocate_rx_data(struct ixl_queue *);
619void ixl_init_tx_ring(struct ixl_queue *);
620int ixl_init_rx_ring(struct ixl_queue *);
621bool ixl_rxeof(struct ixl_queue *, int);
622bool ixl_txeof(struct ixl_queue *);
651
652/*********************************************************************
653 * TXRX Function prototypes
654 *********************************************************************/
655int ixl_allocate_tx_data(struct ixl_queue *);
656int ixl_allocate_rx_data(struct ixl_queue *);
657void ixl_init_tx_ring(struct ixl_queue *);
658int ixl_init_rx_ring(struct ixl_queue *);
659bool ixl_rxeof(struct ixl_queue *, int);
660bool ixl_txeof(struct ixl_queue *);
661void ixl_free_que_tx(struct ixl_queue *);
662void ixl_free_que_rx(struct ixl_queue *);
663
623int ixl_mq_start(struct ifnet *, struct mbuf *);
624int ixl_mq_start_locked(struct ifnet *, struct tx_ring *);
625void ixl_deferred_mq_start(void *, int);
664int ixl_mq_start(struct ifnet *, struct mbuf *);
665int ixl_mq_start_locked(struct ifnet *, struct tx_ring *);
666void ixl_deferred_mq_start(void *, int);
626void ixl_qflush(struct ifnet *);
627void ixl_free_vsi(struct ixl_vsi *);
667void ixl_free_vsi(struct ixl_vsi *);
628void ixl_free_que_tx(struct ixl_queue *);
629void ixl_free_que_rx(struct ixl_queue *);
630#ifdef IXL_FDIR
631void ixl_atr(struct ixl_queue *, struct tcphdr *, int);
632#endif
668void ixl_qflush(struct ifnet *);
669
670/* Common function prototypes between PF/VF driver */
633#if __FreeBSD_version >= 1100000
634uint64_t ixl_get_counter(if_t ifp, ift_counter cnt);
635#endif
671#if __FreeBSD_version >= 1100000
672uint64_t ixl_get_counter(if_t ifp, ift_counter cnt);
673#endif
636
674void ixl_get_default_rss_key(u32 *);
637#endif /* _IXL_H_ */
675#endif /* _IXL_H_ */