| i40e_register.h (f4cc2d1710068319774a27d5c5e7ff85856c9278) | i40e_register.h (b4a7ce0690aedd9763b3b47ee7fcdb421f0434c7) |
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| 1/****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 76 unchanged lines hidden (view full) --- 85#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 86#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 87#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 88#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 89#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 90#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 91#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 92#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 | 1/****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 76 unchanged lines hidden (view full) --- 85#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 86#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 87#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 88#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 89#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 90#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 91#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 92#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 |
| 93#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT) | 93#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) |
| 94#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 95#define I40E_PF_ARQT_ARQT_SHIFT 0 96#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 97#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 98#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 99#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 100#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 101#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 108#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 109#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 110#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 111#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 112#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 113#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 114#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 115#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 | 94#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 95#define I40E_PF_ARQT_ARQT_SHIFT 0 96#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 97#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 98#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 99#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 100#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 101#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 108#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 109#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 110#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 111#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 112#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 113#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 114#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 115#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 |
| 116#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT) | 116#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) |
| 117#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 118#define I40E_PF_ATQT_ATQT_SHIFT 0 119#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 120#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 121#define I40E_VF_ARQBAH_MAX_INDEX 127 122#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 123#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 124#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ --- 10 unchanged lines hidden (view full) --- 135#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 136#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 137#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 138#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 139#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 140#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 141#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 142#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 | 117#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 118#define I40E_PF_ATQT_ATQT_SHIFT 0 119#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 120#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 121#define I40E_VF_ARQBAH_MAX_INDEX 127 122#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 123#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 124#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ --- 10 unchanged lines hidden (view full) --- 135#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 136#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 137#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 138#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 139#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 140#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 141#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 142#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 |
| 143#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT) | 143#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT) |
| 144#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 145#define I40E_VF_ARQT_MAX_INDEX 127 146#define I40E_VF_ARQT_ARQT_SHIFT 0 147#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 148#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 149#define I40E_VF_ATQBAH_MAX_INDEX 127 150#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 151#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) --- 11 unchanged lines hidden (view full) --- 163#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 164#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 165#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 166#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 167#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 168#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 169#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 170#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 | 144#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 145#define I40E_VF_ARQT_MAX_INDEX 127 146#define I40E_VF_ARQT_ARQT_SHIFT 0 147#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 148#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 149#define I40E_VF_ATQBAH_MAX_INDEX 127 150#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 151#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) --- 11 unchanged lines hidden (view full) --- 163#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 164#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 165#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 166#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 167#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 168#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 169#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 170#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 |
| 171#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT) | 171#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT) |
| 172#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 173#define I40E_VF_ATQT_MAX_INDEX 127 174#define I40E_VF_ATQT_ATQT_SHIFT 0 175#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 176#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 177#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 178#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 179#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ --- 106 unchanged lines hidden (view full) --- 286#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 287#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 288#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 289#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 290#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 291#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 292#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 293#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 | 172#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 173#define I40E_VF_ATQT_MAX_INDEX 127 174#define I40E_VF_ATQT_ATQT_SHIFT 0 175#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 176#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 177#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 178#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 179#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ --- 106 unchanged lines hidden (view full) --- 286#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 287#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 288#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 289#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 290#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 291#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 292#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 293#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 |
| 294#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) | 294#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) |
| 295#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 296#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 297#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 298#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 299#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 300#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 301#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 302#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ --- 87 unchanged lines hidden (view full) --- 390#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 391#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 392#define I40E_GL_FWSTS_FWS0B_SHIFT 0 393#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 394#define I40E_GL_FWSTS_FWRI_SHIFT 9 395#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 396#define I40E_GL_FWSTS_FWS1B_SHIFT 16 397#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) | 295#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 296#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 297#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 298#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 299#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 300#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 301#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 302#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ --- 87 unchanged lines hidden (view full) --- 390#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 391#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 392#define I40E_GL_FWSTS_FWS0B_SHIFT 0 393#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 394#define I40E_GL_FWSTS_FWRI_SHIFT 9 395#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 396#define I40E_GL_FWSTS_FWS1B_SHIFT 16 397#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) |
| 398#define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 399#define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 400#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \ 401 I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 402#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \ 403 I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 404#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK \ 405 I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 406#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK \ 407 I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 408#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \ 409 I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 410#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \ 411 I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) |
|
| 398#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 399#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 400#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 401#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 402#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 403#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 404#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 405#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 --- 124 unchanged lines hidden (view full) --- 530#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 531#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 532#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 533#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 534#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 535#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 536#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 537#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 | 412#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 413#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 414#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 415#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 416#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 417#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 418#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 419#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 --- 124 unchanged lines hidden (view full) --- 544#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 545#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 546#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 547#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 548#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 549#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 550#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 551#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 |
| 538#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) | 552#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) |
| 539#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 540#define I40E_GLGEN_MSRWD_MAX_INDEX 3 541#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 542#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 543#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 544#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 545#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 546#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 --- 722 unchanged lines hidden (view full) --- 1269#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 1270#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1271#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1272#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 1273#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 1274#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1275#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1276#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 | 553#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 554#define I40E_GLGEN_MSRWD_MAX_INDEX 3 555#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 556#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 557#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 558#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 559#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 560#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 --- 722 unchanged lines hidden (view full) --- 1283#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 1284#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1285#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1286#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 1287#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 1288#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1289#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1290#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 |
| 1277#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) | 1291#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) |
| 1278#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1279#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1280#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1281#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1282#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1283#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 | 1292#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1293#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1294#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1295#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1296#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1297#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 |
| 1284#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT) | 1298#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) |
| 1285#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1286#define I40E_QRX_ENA_MAX_INDEX 1535 1287#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1288#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 1289#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1290#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 1291#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1292#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) --- 392 unchanged lines hidden (view full) --- 1685#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1686#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1687#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 1688#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1689#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 1690#define I40E_GLNVM_SRCTL_START_SHIFT 30 1691#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 1692#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 | 1299#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1300#define I40E_QRX_ENA_MAX_INDEX 1535 1301#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1302#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 1303#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1304#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 1305#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1306#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) --- 392 unchanged lines hidden (view full) --- 1699#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1700#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1701#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 1702#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1703#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 1704#define I40E_GLNVM_SRCTL_START_SHIFT 30 1705#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 1706#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 |
| 1693#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT) | 1707#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) |
| 1694#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1695#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1696#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1697#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1698#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1699#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1700#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1701#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) --- 1350 unchanged lines hidden (view full) --- 3052#define I40E_PF_MDET_TX_VALID_SHIFT 0 3053#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 3054#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3055#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3056#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3057#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3058#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3059#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 | 1708#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1709#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1710#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1711#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1712#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1713#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1714#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1715#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) --- 1350 unchanged lines hidden (view full) --- 3066#define I40E_PF_MDET_TX_VALID_SHIFT 0 3067#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 3068#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3069#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3070#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3071#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3072#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3073#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 |
| 3060#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT) | 3074#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) |
| 3061#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3062#define I40E_VP_MDET_RX_MAX_INDEX 127 3063#define I40E_VP_MDET_RX_VALID_SHIFT 0 3064#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 3065#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3066#define I40E_VP_MDET_TX_MAX_INDEX 127 3067#define I40E_VP_MDET_TX_VALID_SHIFT 0 3068#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) --- 119 unchanged lines hidden (view full) --- 3188#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3189#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3190#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3191#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3192#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3193#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3194#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3195#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 | 3075#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3076#define I40E_VP_MDET_RX_MAX_INDEX 127 3077#define I40E_VP_MDET_RX_VALID_SHIFT 0 3078#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 3079#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3080#define I40E_VP_MDET_TX_MAX_INDEX 127 3081#define I40E_VP_MDET_TX_VALID_SHIFT 0 3082#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) --- 119 unchanged lines hidden (view full) --- 3202#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3203#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3204#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3205#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3206#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3207#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3208#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3209#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 |
| 3196#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) | 3210#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) |
| 3197#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3198#define I40E_VF_ARQT1_ARQT_SHIFT 0 3199#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 3200#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3201#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3202#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3203#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3204#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 3211#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3212#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3213#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3214#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3215#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3216#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3217#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3218#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 | 3211#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3212#define I40E_VF_ARQT1_ARQT_SHIFT 0 3213#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 3214#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3215#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3216#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3217#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3218#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 3225#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3226#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3227#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3228#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3229#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3230#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3231#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3232#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 |
| 3219#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) | 3233#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) |
| 3220#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3221#define I40E_VF_ATQT1_ATQT_SHIFT 0 3222#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 3223#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3224#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3225#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3226#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3227#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 --- 2136 unchanged lines hidden --- | 3234#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3235#define I40E_VF_ATQT1_ATQT_SHIFT 0 3236#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 3237#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3238#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3239#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3240#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3241#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 --- 2136 unchanged lines hidden --- |