| i40e_register.h (27067774dce3388702a4cf744d7096c6fb71b688) | i40e_register.h (ceebc2f348c028b21bf9bcc99f7a3c4b0cb7d926) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2013-2015, Intel Corporation | 3 Copyright (c) 2013-2017, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 2786 unchanged lines hidden (view full) --- 2798#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2799#define I40E_GLV_RDPC_MAX_INDEX 383 2800#define I40E_GLV_RDPC_RDPC_SHIFT 0 2801#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 2802#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2803#define I40E_GLV_RUPP_MAX_INDEX 383 2804#define I40E_GLV_RUPP_RUPP_SHIFT 0 2805#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 2786 unchanged lines hidden (view full) --- 2798#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2799#define I40E_GLV_RDPC_MAX_INDEX 383 2800#define I40E_GLV_RDPC_RDPC_SHIFT 0 2801#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 2802#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2803#define I40E_GLV_RUPP_MAX_INDEX 383 2804#define I40E_GLV_RUPP_RUPP_SHIFT 0 2805#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) |
| 2806#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ | 2806#define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ |
| 2807#define I40E_GLV_TEPC_MAX_INDEX 383 2808#define I40E_GLV_TEPC_TEPC_SHIFT 0 2809#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 2810#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2811#define I40E_GLV_UPRCH_MAX_INDEX 383 2812#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2813#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 2814#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ --- 2549 unchanged lines hidden --- | 2807#define I40E_GLV_TEPC_MAX_INDEX 383 2808#define I40E_GLV_TEPC_TEPC_SHIFT 0 2809#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 2810#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2811#define I40E_GLV_UPRCH_MAX_INDEX 383 2812#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2813#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 2814#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ --- 2549 unchanged lines hidden --- |