i40e_nvm.c (f4cc2d1710068319774a27d5c5e7ff85856c9278) i40e_nvm.c (b4a7ce0690aedd9763b3b47ee7fcdb421f0434c7)
1/******************************************************************************
2
3 Copyright (c) 2013-2018, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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362 ret_code = __i40e_read_nvm_word(hw, offset, data);
363
364 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
365 i40e_release_nvm(hw);
366 return ret_code;
367}
368
369/**
1/******************************************************************************
2
3 Copyright (c) 2013-2018, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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362 ret_code = __i40e_read_nvm_word(hw, offset, data);
363
364 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
365 i40e_release_nvm(hw);
366 return ret_code;
367}
368
369/**
370 * i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location
371 * @hw: Pointer to the HW structure
372 * @module_ptr: Pointer to module in words with respect to NVM beginning
373 * @module_offset: Offset in words from module start
374 * @data_offset: Offset in words from reading data area start
375 * @words_data_size: Words to read from NVM
376 * @data_ptr: Pointer to memory location where resulting buffer will be stored
377 **/
378enum i40e_status_code
379i40e_read_nvm_module_data(struct i40e_hw *hw, u8 module_ptr, u16 module_offset,
380 u16 data_offset, u16 words_data_size, u16 *data_ptr)
381{
382 enum i40e_status_code status;
383 u16 specific_ptr = 0;
384 u16 ptr_value = 0;
385 u16 offset = 0;
386
387 if (module_ptr != 0) {
388 status = i40e_read_nvm_word(hw, module_ptr, &ptr_value);
389 if (status != I40E_SUCCESS) {
390 i40e_debug(hw, I40E_DEBUG_ALL,
391 "Reading nvm word failed.Error code: %d.\n",
392 status);
393 return I40E_ERR_NVM;
394 }
395 }
396#define I40E_NVM_INVALID_PTR_VAL 0x7FFF
397#define I40E_NVM_INVALID_VAL 0xFFFF
398
399 /* Pointer not initialized */
400 if (ptr_value == I40E_NVM_INVALID_PTR_VAL ||
401 ptr_value == I40E_NVM_INVALID_VAL) {
402 i40e_debug(hw, I40E_DEBUG_ALL, "Pointer not initialized.\n");
403 return I40E_ERR_BAD_PTR;
404 }
405
406 /* Check whether the module is in SR mapped area or outside */
407 if (ptr_value & I40E_PTR_TYPE) {
408 /* Pointer points outside of the Shared RAM mapped area */
409 i40e_debug(hw, I40E_DEBUG_ALL,
410 "Reading nvm data failed. Pointer points outside of the Shared RAM mapped area.\n");
411
412 return I40E_ERR_PARAM;
413 } else {
414 /* Read from the Shadow RAM */
415
416 status = i40e_read_nvm_word(hw, ptr_value + module_offset,
417 &specific_ptr);
418 if (status != I40E_SUCCESS) {
419 i40e_debug(hw, I40E_DEBUG_ALL,
420 "Reading nvm word failed.Error code: %d.\n",
421 status);
422 return I40E_ERR_NVM;
423 }
424
425 offset = ptr_value + module_offset + specific_ptr +
426 data_offset;
427
428 status = i40e_read_nvm_buffer(hw, offset, &words_data_size,
429 data_ptr);
430 if (status != I40E_SUCCESS) {
431 i40e_debug(hw, I40E_DEBUG_ALL,
432 "Reading nvm buffer failed.Error code: %d.\n",
433 status);
434 }
435 }
436
437 return status;
438}
439
440/**
370 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
371 * @hw: pointer to the HW structure
372 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
373 * @words: (in) number of words to read; (out) number of words actually read
374 * @data: words read from the Shadow RAM
375 *
376 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
377 * method. The buffer read is preceded by the NVM ownership take

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499 if (!ret_code) {
500 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
501 data);
502 i40e_release_nvm(hw);
503 }
504 } else {
505 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
506 }
441 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
442 * @hw: pointer to the HW structure
443 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
444 * @words: (in) number of words to read; (out) number of words actually read
445 * @data: words read from the Shadow RAM
446 *
447 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
448 * method. The buffer read is preceded by the NVM ownership take

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570 if (!ret_code) {
571 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
572 data);
573 i40e_release_nvm(hw);
574 }
575 } else {
576 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
577 }
578
507 return ret_code;
508}
509
579 return ret_code;
580}
581
510
511/**
512 * i40e_write_nvm_aq - Writes Shadow RAM.
513 * @hw: pointer to the HW structure.
514 * @module_pointer: module pointer location in words from the NVM beginning
515 * @offset: offset in words from module start
516 * @words: number of words to write
517 * @data: buffer with words to write to the Shadow RAM
518 * @last_command: tells the AdminQ that this is the last command

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821 "I40E_NVMUPD_WRITE_SA",
822 "I40E_NVMUPD_CSUM_CON",
823 "I40E_NVMUPD_CSUM_SA",
824 "I40E_NVMUPD_CSUM_LCB",
825 "I40E_NVMUPD_STATUS",
826 "I40E_NVMUPD_EXEC_AQ",
827 "I40E_NVMUPD_GET_AQ_RESULT",
828 "I40E_NVMUPD_GET_AQ_EVENT",
582/**
583 * i40e_write_nvm_aq - Writes Shadow RAM.
584 * @hw: pointer to the HW structure.
585 * @module_pointer: module pointer location in words from the NVM beginning
586 * @offset: offset in words from module start
587 * @words: number of words to write
588 * @data: buffer with words to write to the Shadow RAM
589 * @last_command: tells the AdminQ that this is the last command

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892 "I40E_NVMUPD_WRITE_SA",
893 "I40E_NVMUPD_CSUM_CON",
894 "I40E_NVMUPD_CSUM_SA",
895 "I40E_NVMUPD_CSUM_LCB",
896 "I40E_NVMUPD_STATUS",
897 "I40E_NVMUPD_EXEC_AQ",
898 "I40E_NVMUPD_GET_AQ_RESULT",
899 "I40E_NVMUPD_GET_AQ_EVENT",
900 "I40E_NVMUPD_GET_FEATURES",
829};
830
831/**
832 * i40e_nvmupd_command - Process an NVM update command
833 * @hw: pointer to hardware structure
834 * @cmd: pointer to nvm update command
835 * @bytes: pointer to the data buffer
836 * @perrno: pointer to return error code

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883
884 /* Clear error status on read */
885 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
886 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
887
888 return I40E_SUCCESS;
889 }
890
901};
902
903/**
904 * i40e_nvmupd_command - Process an NVM update command
905 * @hw: pointer to hardware structure
906 * @cmd: pointer to nvm update command
907 * @bytes: pointer to the data buffer
908 * @perrno: pointer to return error code

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955
956 /* Clear error status on read */
957 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
958 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
959
960 return I40E_SUCCESS;
961 }
962
963 /*
964 * A supported features request returns immediately
965 * rather than going into state machine
966 */
967 if (upd_cmd == I40E_NVMUPD_FEATURES) {
968 if (cmd->data_size < hw->nvmupd_features.size) {
969 *perrno = -EFAULT;
970 return I40E_ERR_BUF_TOO_SHORT;
971 }
972
973 /*
974 * If buffer is bigger than i40e_nvmupd_features structure,
975 * make sure the trailing bytes are set to 0x0.
976 */
977 if (cmd->data_size > hw->nvmupd_features.size)
978 i40e_memset(bytes + hw->nvmupd_features.size, 0x0,
979 cmd->data_size - hw->nvmupd_features.size,
980 I40E_NONDMA_MEM);
981
982 i40e_memcpy(bytes, &hw->nvmupd_features,
983 hw->nvmupd_features.size, I40E_NONDMA_MEM);
984
985 return I40E_SUCCESS;
986 }
987
891 /* Clear status even it is not read and log */
892 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
893 i40e_debug(hw, I40E_DEBUG_NVM,
894 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
895 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
896 }
897
898 /* Acquire lock to prevent race condition where adminq_task

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1349 break;
1350 case I40E_NVM_LCB:
1351 upd_cmd = I40E_NVMUPD_READ_LCB;
1352 break;
1353 case I40E_NVM_SA:
1354 upd_cmd = I40E_NVMUPD_READ_SA;
1355 break;
1356 case I40E_NVM_EXEC:
988 /* Clear status even it is not read and log */
989 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
990 i40e_debug(hw, I40E_DEBUG_NVM,
991 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
992 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
993 }
994
995 /* Acquire lock to prevent race condition where adminq_task

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1446 break;
1447 case I40E_NVM_LCB:
1448 upd_cmd = I40E_NVMUPD_READ_LCB;
1449 break;
1450 case I40E_NVM_SA:
1451 upd_cmd = I40E_NVMUPD_READ_SA;
1452 break;
1453 case I40E_NVM_EXEC:
1357 if (module == 0xf)
1358 upd_cmd = I40E_NVMUPD_STATUS;
1359 else if (module == 0)
1454 switch (module) {
1455 case I40E_NVM_EXEC_GET_AQ_RESULT:
1360 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1456 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1457 break;
1458 case I40E_NVM_EXEC_FEATURES:
1459 upd_cmd = I40E_NVMUPD_FEATURES;
1460 break;
1461 case I40E_NVM_EXEC_STATUS:
1462 upd_cmd = I40E_NVMUPD_STATUS;
1463 break;
1464 default:
1465 *perrno = -EFAULT;
1466 return I40E_NVMUPD_INVALID;
1467 }
1361 break;
1362 case I40E_NVM_AQE:
1363 upd_cmd = I40E_NVMUPD_GET_AQ_EVENT;
1364 break;
1365 }
1366 break;
1367
1368 case I40E_NVM_WRITE:

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1468 break;
1469 case I40E_NVM_AQE:
1470 upd_cmd = I40E_NVMUPD_GET_AQ_EVENT;
1471 break;
1472 }
1473 break;
1474
1475 case I40E_NVM_WRITE:

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