i40e_nvm.c (b4a7ce0690aedd9763b3b47ee7fcdb421f0434c7) i40e_nvm.c (abf774528d7e497460510b0026db85e30f054142)
1/******************************************************************************
2
3 Copyright (c) 2013-2018, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35#include "i40e_prototype.h"
36
37/**
1/******************************************************************************
2
3 Copyright (c) 2013-2018, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35#include "i40e_prototype.h"
36
37/**
38 * i40e_init_nvm_ops - Initialize NVM function pointers
38 * i40e_init_nvm - Initialize NVM function pointers
39 * @hw: pointer to the HW structure
40 *
41 * Setup the function pointers and the NVM info structure. Should be called
42 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
43 * Please notice that the NVM term is used here (& in all methods covered
44 * in this file) as an equivalent of the FLASH part mapped into the SR.
45 * We are accessing FLASH always through the Shadow RAM.
46 **/

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103 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
104
105 /* Store the timeout */
106 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
107
108 if (ret_code)
109 i40e_debug(hw, I40E_DEBUG_NVM,
110 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
39 * @hw: pointer to the HW structure
40 *
41 * Setup the function pointers and the NVM info structure. Should be called
42 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
43 * Please notice that the NVM term is used here (& in all methods covered
44 * in this file) as an equivalent of the FLASH part mapped into the SR.
45 * We are accessing FLASH always through the Shadow RAM.
46 **/

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103 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
104
105 /* Store the timeout */
106 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
107
108 if (ret_code)
109 i40e_debug(hw, I40E_DEBUG_NVM,
110 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
111 access, time_left, ret_code, hw->aq.asq_last_status);
111 access, (unsigned long long)time_left, ret_code,
112 hw->aq.asq_last_status);
112
113 if (ret_code && time_left) {
114 /* Poll until the current NVM owner timeouts */
115 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
116 while ((gtime < timeout) && time_left) {
117 i40e_msec_delay(10);
118 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
119 ret_code = i40e_aq_request_resource(hw,

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125 I40E_MS_TO_GTIME(time_left) + gtime;
126 break;
127 }
128 }
129 if (ret_code != I40E_SUCCESS) {
130 hw->nvm.hw_semaphore_timeout = 0;
131 i40e_debug(hw, I40E_DEBUG_NVM,
132 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
113
114 if (ret_code && time_left) {
115 /* Poll until the current NVM owner timeouts */
116 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
117 while ((gtime < timeout) && time_left) {
118 i40e_msec_delay(10);
119 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
120 ret_code = i40e_aq_request_resource(hw,

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126 I40E_MS_TO_GTIME(time_left) + gtime;
127 break;
128 }
129 }
130 if (ret_code != I40E_SUCCESS) {
131 hw->nvm.hw_semaphore_timeout = 0;
132 i40e_debug(hw, I40E_DEBUG_NVM,
133 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
133 time_left, ret_code, hw->aq.asq_last_status);
134 (unsigned long long)time_left, ret_code,
135 hw->aq.asq_last_status);
134 }
135 }
136
137i40e_i40e_acquire_nvm_exit:
138 return ret_code;
139}
140
141/**

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777{
778 enum i40e_status_code ret_code = I40E_SUCCESS;
779 u16 checksum;
780 __le16 le_sum;
781
782 DEBUGFUNC("i40e_update_nvm_checksum");
783
784 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
136 }
137 }
138
139i40e_i40e_acquire_nvm_exit:
140 return ret_code;
141}
142
143/**

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779{
780 enum i40e_status_code ret_code = I40E_SUCCESS;
781 u16 checksum;
782 __le16 le_sum;
783
784 DEBUGFUNC("i40e_update_nvm_checksum");
785
786 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
785 le_sum = CPU_TO_LE16(checksum);
786 if (ret_code == I40E_SUCCESS)
787 if (ret_code == I40E_SUCCESS) {
788 le_sum = CPU_TO_LE16(checksum);
787 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
788 1, &le_sum, TRUE);
789 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
790 1, &le_sum, TRUE);
791 }
789
790 return ret_code;
791}
792
793/**
794 * i40e_validate_nvm_checksum - Validate EEPROM checksum
795 * @hw: pointer to hardware structure
796 * @checksum: calculated checksum

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793 return ret_code;
794}
795
796/**
797 * i40e_validate_nvm_checksum - Validate EEPROM checksum
798 * @hw: pointer to hardware structure
799 * @checksum: calculated checksum

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