i40e_nvm.c (1a36faad54665288ed4eb839d2a4699ae2ead45e) i40e_nvm.c (ceebc2f348c028b21bf9bcc99f7a3c4b0cb7d926)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
3 Copyright (c) 2013-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35#include "i40e_prototype.h"
36
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35#include "i40e_prototype.h"
36
37enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
38 u16 *data);
39enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
40 u16 *data);
41enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
42 u16 *words, u16 *data);
43enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
44 u16 *words, u16 *data);
45enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
46 u32 offset, u16 words, void *data,
47 bool last_command);
48
49/**
50 * i40e_init_nvm_ops - Initialize NVM function pointers
51 * @hw: pointer to the HW structure
52 *
53 * Setup the function pointers and the NVM info structure. Should be called
54 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
55 * Please notice that the NVM term is used here (& in all methods covered
56 * in this file) as an equivalent of the FLASH part mapped into the SR.

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203 i40e_usec_delay(5);
204 }
205 if (ret_code == I40E_ERR_TIMEOUT)
206 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
207 return ret_code;
208}
209
210/**
37/**
38 * i40e_init_nvm_ops - Initialize NVM function pointers
39 * @hw: pointer to the HW structure
40 *
41 * Setup the function pointers and the NVM info structure. Should be called
42 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
43 * Please notice that the NVM term is used here (& in all methods covered
44 * in this file) as an equivalent of the FLASH part mapped into the SR.

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191 i40e_usec_delay(5);
192 }
193 if (ret_code == I40E_ERR_TIMEOUT)
194 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
195 return ret_code;
196}
197
198/**
211 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
212 * @hw: pointer to the HW structure
213 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
214 * @data: word read from the Shadow RAM
215 *
216 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
217 **/
218enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
219 u16 *data)
220{
221 enum i40e_status_code ret_code = I40E_SUCCESS;
222
223 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
224 if (!ret_code) {
225 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
226 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
227 } else {
228 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
229 }
230 i40e_release_nvm(hw);
231 }
232 return ret_code;
233}
234
235/**
236 * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking
237 * @hw: pointer to the HW structure
238 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
239 * @data: word read from the Shadow RAM
240 *
241 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
242 **/
243enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw,
244 u16 offset,
245 u16 *data)
246{
247 enum i40e_status_code ret_code = I40E_SUCCESS;
248
249 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
250 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
251 else
252 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
253 return ret_code;
254}
255
256/**
257 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
258 * @hw: pointer to the HW structure
259 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
260 * @data: word read from the Shadow RAM
261 *
262 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
263 **/
264enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,

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299 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
300 offset);
301
302read_nvm_exit:
303 return ret_code;
304}
305
306/**
199 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
200 * @hw: pointer to the HW structure
201 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
202 * @data: word read from the Shadow RAM
203 *
204 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
205 **/
206enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,

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241 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
242 offset);
243
244read_nvm_exit:
245 return ret_code;
246}
247
248/**
249 * i40e_read_nvm_aq - Read Shadow RAM.
250 * @hw: pointer to the HW structure.
251 * @module_pointer: module pointer location in words from the NVM beginning
252 * @offset: offset in words from module start
253 * @words: number of words to write
254 * @data: buffer with words to write to the Shadow RAM
255 * @last_command: tells the AdminQ that this is the last command
256 *
257 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
258 **/
259static enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw,
260 u8 module_pointer, u32 offset,
261 u16 words, void *data,
262 bool last_command)
263{
264 enum i40e_status_code ret_code = I40E_ERR_NVM;
265 struct i40e_asq_cmd_details cmd_details;
266
267 DEBUGFUNC("i40e_read_nvm_aq");
268
269 memset(&cmd_details, 0, sizeof(cmd_details));
270 cmd_details.wb_desc = &hw->nvm_wb_desc;
271
272 /* Here we are checking the SR limit only for the flat memory model.
273 * We cannot do it for the module-based model, as we did not acquire
274 * the NVM resource yet (we cannot get the module pointer value).
275 * Firmware will check the module-based model.
276 */
277 if ((offset + words) > hw->nvm.sr_size)
278 i40e_debug(hw, I40E_DEBUG_NVM,
279 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
280 (offset + words), hw->nvm.sr_size);
281 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
282 /* We can write only up to 4KB (one sector), in one AQ write */
283 i40e_debug(hw, I40E_DEBUG_NVM,
284 "NVM write fail error: tried to write %d words, limit is %d.\n",
285 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
286 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
287 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
288 /* A single write cannot spread over two sectors */
289 i40e_debug(hw, I40E_DEBUG_NVM,
290 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
291 offset, words);
292 else
293 ret_code = i40e_aq_read_nvm(hw, module_pointer,
294 2 * offset, /*bytes*/
295 2 * words, /*bytes*/
296 data, last_command, &cmd_details);
297
298 return ret_code;
299}
300
301/**
307 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
308 * @hw: pointer to the HW structure
309 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
310 * @data: word read from the Shadow RAM
311 *
302 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
303 * @hw: pointer to the HW structure
304 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
305 * @data: word read from the Shadow RAM
306 *
312 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
307 * Reads one 16 bit word from the Shadow RAM using the AdminQ
313 **/
308 **/
314enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
315 u16 *data)
309static enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
310 u16 *data)
316{
317 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
318
319 DEBUGFUNC("i40e_read_nvm_word_aq");
320
321 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE);
322 *data = LE16_TO_CPU(*(__le16 *)data);
323
324 return ret_code;
325}
326
327/**
311{
312 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
313
314 DEBUGFUNC("i40e_read_nvm_word_aq");
315
316 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE);
317 *data = LE16_TO_CPU(*(__le16 *)data);
318
319 return ret_code;
320}
321
322/**
328 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
323 * __i40e_read_nvm_word - Reads NVM word, assumes caller does the locking
329 * @hw: pointer to the HW structure
324 * @hw: pointer to the HW structure
330 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
331 * @words: (in) number of words to read; (out) number of words actually read
332 * @data: words read from the Shadow RAM
325 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
326 * @data: word read from the Shadow RAM
333 *
327 *
334 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
335 * method. The buffer read is preceded by the NVM ownership take
336 * and followed by the release.
328 * Reads one 16 bit word from the Shadow RAM.
329 *
330 * Do not use this function except in cases where the nvm lock is already
331 * taken via i40e_acquire_nvm().
337 **/
332 **/
338enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw,
339 u16 offset,
340 u16 *words, u16 *data)
333enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw,
334 u16 offset,
335 u16 *data)
341{
336{
342 enum i40e_status_code ret_code = I40E_SUCCESS;
343
344 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
337
338 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
345 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data);
346 else
347 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
348 return ret_code;
339 return i40e_read_nvm_word_aq(hw, offset, data);
340
341 return i40e_read_nvm_word_srctl(hw, offset, data);
349}
350
351/**
342}
343
344/**
352 * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acuire lock if necessary
345 * i40e_read_nvm_word - Reads NVM word, acquires lock if necessary
353 * @hw: pointer to the HW structure
346 * @hw: pointer to the HW structure
354 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
355 * @words: (in) number of words to read; (out) number of words actually read
356 * @data: words read from the Shadow RAM
347 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
348 * @data: word read from the Shadow RAM
357 *
349 *
358 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
359 * method. The buffer read is preceded by the NVM ownership take
360 * and followed by the release.
350 * Reads one 16 bit word from the Shadow RAM.
361 **/
351 **/
362enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
363 u16 *words, u16 *data)
352enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
353 u16 *data)
364{
365 enum i40e_status_code ret_code = I40E_SUCCESS;
366
354{
355 enum i40e_status_code ret_code = I40E_SUCCESS;
356
367 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
357 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
368 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
358 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
369 if (!ret_code) {
370 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
371 data);
372 i40e_release_nvm(hw);
373 }
374 } else {
375 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
376 }
359
360 if (ret_code)
361 return ret_code;
362 ret_code = __i40e_read_nvm_word(hw, offset, data);
363
364 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
365 i40e_release_nvm(hw);
377 return ret_code;
378}
379
380/**
381 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
382 * @hw: pointer to the HW structure
383 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
384 * @words: (in) number of words to read; (out) number of words actually read
385 * @data: words read from the Shadow RAM
386 *
387 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
388 * method. The buffer read is preceded by the NVM ownership take
389 * and followed by the release.
390 **/
366 return ret_code;
367}
368
369/**
370 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
371 * @hw: pointer to the HW structure
372 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
373 * @words: (in) number of words to read; (out) number of words actually read
374 * @data: words read from the Shadow RAM
375 *
376 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
377 * method. The buffer read is preceded by the NVM ownership take
378 * and followed by the release.
379 **/
391enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
392 u16 *words, u16 *data)
380static enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
381 u16 *words, u16 *data)
393{
394 enum i40e_status_code ret_code = I40E_SUCCESS;
395 u16 index, word;
396
397 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
398
399 /* Loop through the selected region */
400 for (word = 0; word < *words; word++) {

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416 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
417 * @words: (in) number of words to read; (out) number of words actually read
418 * @data: words read from the Shadow RAM
419 *
420 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
421 * method. The buffer read is preceded by the NVM ownership take
422 * and followed by the release.
423 **/
382{
383 enum i40e_status_code ret_code = I40E_SUCCESS;
384 u16 index, word;
385
386 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
387
388 /* Loop through the selected region */
389 for (word = 0; word < *words; word++) {

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405 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
406 * @words: (in) number of words to read; (out) number of words actually read
407 * @data: words read from the Shadow RAM
408 *
409 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
410 * method. The buffer read is preceded by the NVM ownership take
411 * and followed by the release.
412 **/
424enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
425 u16 *words, u16 *data)
413static enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
414 u16 *words, u16 *data)
426{
427 enum i40e_status_code ret_code;
428 u16 read_size = *words;
429 bool last_cmd = FALSE;
430 u16 words_read = 0;
431 u16 i = 0;
432
433 DEBUGFUNC("i40e_read_nvm_buffer_aq");

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465 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
466
467read_nvm_buffer_aq_exit:
468 *words = words_read;
469 return ret_code;
470}
471
472/**
415{
416 enum i40e_status_code ret_code;
417 u16 read_size = *words;
418 bool last_cmd = FALSE;
419 u16 words_read = 0;
420 u16 i = 0;
421
422 DEBUGFUNC("i40e_read_nvm_buffer_aq");

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454 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
455
456read_nvm_buffer_aq_exit:
457 *words = words_read;
458 return ret_code;
459}
460
461/**
473 * i40e_read_nvm_aq - Read Shadow RAM.
474 * @hw: pointer to the HW structure.
475 * @module_pointer: module pointer location in words from the NVM beginning
476 * @offset: offset in words from module start
477 * @words: number of words to write
478 * @data: buffer with words to write to the Shadow RAM
479 * @last_command: tells the AdminQ that this is the last command
462 * __i40e_read_nvm_buffer - Reads NVM buffer, caller must acquire lock
463 * @hw: pointer to the HW structure
464 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
465 * @words: (in) number of words to read; (out) number of words actually read
466 * @data: words read from the Shadow RAM
480 *
467 *
481 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
468 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
469 * method.
482 **/
470 **/
483enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
484 u32 offset, u16 words, void *data,
485 bool last_command)
471enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw,
472 u16 offset,
473 u16 *words, u16 *data)
486{
474{
487 enum i40e_status_code ret_code = I40E_ERR_NVM;
488 struct i40e_asq_cmd_details cmd_details;
475 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
476 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
489
477
490 DEBUGFUNC("i40e_read_nvm_aq");
478 return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
479}
491
480
492 memset(&cmd_details, 0, sizeof(cmd_details));
493 cmd_details.wb_desc = &hw->nvm_wb_desc;
481/**
482 * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
483 * @hw: pointer to the HW structure
484 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
485 * @words: (in) number of words to read; (out) number of words actually read
486 * @data: words read from the Shadow RAM
487 *
488 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
489 * method. The buffer read is preceded by the NVM ownership take
490 * and followed by the release.
491 **/
492enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
493 u16 *words, u16 *data)
494{
495 enum i40e_status_code ret_code = I40E_SUCCESS;
494
496
495 /* Here we are checking the SR limit only for the flat memory model.
496 * We cannot do it for the module-based model, as we did not acquire
497 * the NVM resource yet (we cannot get the module pointer value).
498 * Firmware will check the module-based model.
499 */
500 if ((offset + words) > hw->nvm.sr_size)
501 i40e_debug(hw, I40E_DEBUG_NVM,
502 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
503 (offset + words), hw->nvm.sr_size);
504 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
505 /* We can write only up to 4KB (one sector), in one AQ write */
506 i40e_debug(hw, I40E_DEBUG_NVM,
507 "NVM write fail error: tried to write %d words, limit is %d.\n",
508 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
509 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
510 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
511 /* A single write cannot spread over two sectors */
512 i40e_debug(hw, I40E_DEBUG_NVM,
513 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
514 offset, words);
515 else
516 ret_code = i40e_aq_read_nvm(hw, module_pointer,
517 2 * offset, /*bytes*/
518 2 * words, /*bytes*/
519 data, last_command, &cmd_details);
520
497 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
498 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
499 if (!ret_code) {
500 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
501 data);
502 i40e_release_nvm(hw);
503 }
504 } else {
505 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
506 }
521 return ret_code;
522}
523
507 return ret_code;
508}
509
510
524/**
525 * i40e_write_nvm_aq - Writes Shadow RAM.
526 * @hw: pointer to the HW structure.
527 * @module_pointer: module pointer location in words from the NVM beginning
528 * @offset: offset in words from module start
529 * @words: number of words to write
530 * @data: buffer with words to write to the Shadow RAM
531 * @last_command: tells the AdminQ that this is the last command

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557 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
558 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
559 /* A single write cannot spread over two sectors */
560 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
561 else
562 ret_code = i40e_aq_update_nvm(hw, module_pointer,
563 2 * offset, /*bytes*/
564 2 * words, /*bytes*/
511/**
512 * i40e_write_nvm_aq - Writes Shadow RAM.
513 * @hw: pointer to the HW structure.
514 * @module_pointer: module pointer location in words from the NVM beginning
515 * @offset: offset in words from module start
516 * @words: number of words to write
517 * @data: buffer with words to write to the Shadow RAM
518 * @last_command: tells the AdminQ that this is the last command

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544 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
545 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
546 /* A single write cannot spread over two sectors */
547 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
548 else
549 ret_code = i40e_aq_update_nvm(hw, module_pointer,
550 2 * offset, /*bytes*/
551 2 * words, /*bytes*/
565 data, last_command, &cmd_details);
552 data, last_command, 0,
553 &cmd_details);
566
567 return ret_code;
568}
569
570/**
571 * __i40e_write_nvm_word - Writes Shadow RAM word
572 * @hw: pointer to the HW structure
573 * @offset: offset of the Shadow RAM word to write

--- 72 unchanged lines hidden (view full) ---

646
647 ret_code = i40e_allocate_virt_mem(hw, &vmem,
648 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
649 if (ret_code)
650 goto i40e_calc_nvm_checksum_exit;
651 data = (u16 *)vmem.va;
652
653 /* read pointer to VPD area */
554
555 return ret_code;
556}
557
558/**
559 * __i40e_write_nvm_word - Writes Shadow RAM word
560 * @hw: pointer to the HW structure
561 * @offset: offset of the Shadow RAM word to write

--- 72 unchanged lines hidden (view full) ---

634
635 ret_code = i40e_allocate_virt_mem(hw, &vmem,
636 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
637 if (ret_code)
638 goto i40e_calc_nvm_checksum_exit;
639 data = (u16 *)vmem.va;
640
641 /* read pointer to VPD area */
654 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR,
655 &vpd_module);
642 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
656 if (ret_code != I40E_SUCCESS) {
657 ret_code = I40E_ERR_NVM_CHECKSUM;
658 goto i40e_calc_nvm_checksum_exit;
659 }
660
661 /* read pointer to PCIe Alt Auto-load module */
643 if (ret_code != I40E_SUCCESS) {
644 ret_code = I40E_ERR_NVM_CHECKSUM;
645 goto i40e_calc_nvm_checksum_exit;
646 }
647
648 /* read pointer to PCIe Alt Auto-load module */
662 ret_code = __i40e_read_nvm_word(hw,
663 I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
649 ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
664 &pcie_alt_module);
665 if (ret_code != I40E_SUCCESS) {
666 ret_code = I40E_ERR_NVM_CHECKSUM;
667 goto i40e_calc_nvm_checksum_exit;
668 }
669
670 /* Calculate SW checksum that covers the whole 64kB shadow RAM
671 * except the VPD and PCIe ALT Auto-load modules

--- 73 unchanged lines hidden (view full) ---

745 u16 *checksum)
746{
747 enum i40e_status_code ret_code = I40E_SUCCESS;
748 u16 checksum_sr = 0;
749 u16 checksum_local = 0;
750
751 DEBUGFUNC("i40e_validate_nvm_checksum");
752
650 &pcie_alt_module);
651 if (ret_code != I40E_SUCCESS) {
652 ret_code = I40E_ERR_NVM_CHECKSUM;
653 goto i40e_calc_nvm_checksum_exit;
654 }
655
656 /* Calculate SW checksum that covers the whole 64kB shadow RAM
657 * except the VPD and PCIe ALT Auto-load modules

--- 73 unchanged lines hidden (view full) ---

731 u16 *checksum)
732{
733 enum i40e_status_code ret_code = I40E_SUCCESS;
734 u16 checksum_sr = 0;
735 u16 checksum_local = 0;
736
737 DEBUGFUNC("i40e_validate_nvm_checksum");
738
753 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
754 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
755 if (!ret_code) {
756 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
757 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
758 i40e_release_nvm(hw);
759 if (ret_code != I40E_SUCCESS)
760 goto i40e_validate_nvm_checksum_exit;
761 } else {
762 goto i40e_validate_nvm_checksum_exit;
763 }
739 /* We must acquire the NVM lock in order to correctly synchronize the
740 * NVM accesses across multiple PFs. Without doing so it is possible
741 * for one of the PFs to read invalid data potentially indicating that
742 * the checksum is invalid.
743 */
744 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
745 if (ret_code)
746 return ret_code;
747 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
748 __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
749 i40e_release_nvm(hw);
750 if (ret_code)
751 return ret_code;
764
752
765 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
766
767 /* Verify read checksum from EEPROM is the same as
768 * calculated checksum
769 */
770 if (checksum_local != checksum_sr)
771 ret_code = I40E_ERR_NVM_CHECKSUM;
772
773 /* If the user cares, return the calculated checksum */
774 if (checksum)
775 *checksum = checksum_local;
776
753 /* Verify read checksum from EEPROM is the same as
754 * calculated checksum
755 */
756 if (checksum_local != checksum_sr)
757 ret_code = I40E_ERR_NVM_CHECKSUM;
758
759 /* If the user cares, return the calculated checksum */
760 if (checksum)
761 *checksum = checksum_local;
762
777i40e_validate_nvm_checksum_exit:
778 return ret_code;
779}
780
781static enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
782 struct i40e_nvm_access *cmd,
783 u8 *bytes, int *perrno);
784static enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
785 struct i40e_nvm_access *cmd,

--- 14 unchanged lines hidden (view full) ---

800 struct i40e_nvm_access *cmd,
801 u8 *bytes, int *perrno);
802static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
803 struct i40e_nvm_access *cmd,
804 u8 *bytes, int *perrno);
805static enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
806 struct i40e_nvm_access *cmd,
807 u8 *bytes, int *perrno);
763 return ret_code;
764}
765
766static enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
767 struct i40e_nvm_access *cmd,
768 u8 *bytes, int *perrno);
769static enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
770 struct i40e_nvm_access *cmd,

--- 14 unchanged lines hidden (view full) ---

785 struct i40e_nvm_access *cmd,
786 u8 *bytes, int *perrno);
787static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
788 struct i40e_nvm_access *cmd,
789 u8 *bytes, int *perrno);
790static enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
791 struct i40e_nvm_access *cmd,
792 u8 *bytes, int *perrno);
793static enum i40e_status_code i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
794 struct i40e_nvm_access *cmd,
795 u8 *bytes, int *perrno);
808static INLINE u8 i40e_nvmupd_get_module(u32 val)
809{
810 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
811}
812static INLINE u8 i40e_nvmupd_get_transaction(u32 val)
813{
814 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
815}
816
796static INLINE u8 i40e_nvmupd_get_module(u32 val)
797{
798 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
799}
800static INLINE u8 i40e_nvmupd_get_transaction(u32 val)
801{
802 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
803}
804
805static INLINE u8 i40e_nvmupd_get_preservation_flags(u32 val)
806{
807 return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >>
808 I40E_NVM_PRESERVATION_FLAGS_SHIFT);
809}
810
817static const char *i40e_nvm_update_state_str[] = {
818 "I40E_NVMUPD_INVALID",
819 "I40E_NVMUPD_READ_CON",
820 "I40E_NVMUPD_READ_SNT",
821 "I40E_NVMUPD_READ_LCB",
822 "I40E_NVMUPD_READ_SA",
823 "I40E_NVMUPD_WRITE_ERA",
824 "I40E_NVMUPD_WRITE_CON",
825 "I40E_NVMUPD_WRITE_SNT",
826 "I40E_NVMUPD_WRITE_LCB",
827 "I40E_NVMUPD_WRITE_SA",
828 "I40E_NVMUPD_CSUM_CON",
829 "I40E_NVMUPD_CSUM_SA",
830 "I40E_NVMUPD_CSUM_LCB",
831 "I40E_NVMUPD_STATUS",
832 "I40E_NVMUPD_EXEC_AQ",
833 "I40E_NVMUPD_GET_AQ_RESULT",
811static const char *i40e_nvm_update_state_str[] = {
812 "I40E_NVMUPD_INVALID",
813 "I40E_NVMUPD_READ_CON",
814 "I40E_NVMUPD_READ_SNT",
815 "I40E_NVMUPD_READ_LCB",
816 "I40E_NVMUPD_READ_SA",
817 "I40E_NVMUPD_WRITE_ERA",
818 "I40E_NVMUPD_WRITE_CON",
819 "I40E_NVMUPD_WRITE_SNT",
820 "I40E_NVMUPD_WRITE_LCB",
821 "I40E_NVMUPD_WRITE_SA",
822 "I40E_NVMUPD_CSUM_CON",
823 "I40E_NVMUPD_CSUM_SA",
824 "I40E_NVMUPD_CSUM_LCB",
825 "I40E_NVMUPD_STATUS",
826 "I40E_NVMUPD_EXEC_AQ",
827 "I40E_NVMUPD_GET_AQ_RESULT",
828 "I40E_NVMUPD_GET_AQ_EVENT",
834};
835
836/**
837 * i40e_nvmupd_command - Process an NVM update command
838 * @hw: pointer to hardware structure
839 * @cmd: pointer to nvm update command
840 * @bytes: pointer to the data buffer
841 * @perrno: pointer to return error code

--- 53 unchanged lines hidden (view full) ---

895
896 /* Clear status even it is not read and log */
897 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
898 i40e_debug(hw, I40E_DEBUG_NVM,
899 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
900 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
901 }
902
829};
830
831/**
832 * i40e_nvmupd_command - Process an NVM update command
833 * @hw: pointer to hardware structure
834 * @cmd: pointer to nvm update command
835 * @bytes: pointer to the data buffer
836 * @perrno: pointer to return error code

--- 53 unchanged lines hidden (view full) ---

890
891 /* Clear status even it is not read and log */
892 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
893 i40e_debug(hw, I40E_DEBUG_NVM,
894 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
895 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
896 }
897
898 /* Acquire lock to prevent race condition where adminq_task
899 * can execute after i40e_nvmupd_nvm_read/write but before state
900 * variables (nvm_wait_opcode, nvm_release_on_done) are updated.
901 *
902 * During NVMUpdate, it is observed that lock could be held for
903 * ~5ms for most commands. However lock is held for ~60ms for
904 * NVMUPD_CSUM_LCB command.
905 */
906 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
903 switch (hw->nvmupd_state) {
904 case I40E_NVMUPD_STATE_INIT:
905 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
906 break;
907
908 case I40E_NVMUPD_STATE_READING:
909 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
910 break;
911
912 case I40E_NVMUPD_STATE_WRITING:
913 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
914 break;
915
916 case I40E_NVMUPD_STATE_INIT_WAIT:
917 case I40E_NVMUPD_STATE_WRITE_WAIT:
918 /* if we need to stop waiting for an event, clear
919 * the wait info and return before doing anything else
920 */
921 if (cmd->offset == 0xffff) {
907 switch (hw->nvmupd_state) {
908 case I40E_NVMUPD_STATE_INIT:
909 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
910 break;
911
912 case I40E_NVMUPD_STATE_READING:
913 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
914 break;
915
916 case I40E_NVMUPD_STATE_WRITING:
917 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
918 break;
919
920 case I40E_NVMUPD_STATE_INIT_WAIT:
921 case I40E_NVMUPD_STATE_WRITE_WAIT:
922 /* if we need to stop waiting for an event, clear
923 * the wait info and return before doing anything else
924 */
925 if (cmd->offset == 0xffff) {
922 i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
923 return I40E_SUCCESS;
926 i40e_nvmupd_clear_wait_state(hw);
927 status = I40E_SUCCESS;
928 break;
924 }
925
926 status = I40E_ERR_NOT_READY;
927 *perrno = -EBUSY;
928 break;
929
930 default:
931 /* invalid state, should never happen */
932 i40e_debug(hw, I40E_DEBUG_NVM,
933 "NVMUPD: no such state %d\n", hw->nvmupd_state);
934 status = I40E_NOT_SUPPORTED;
935 *perrno = -ESRCH;
936 break;
937 }
929 }
930
931 status = I40E_ERR_NOT_READY;
932 *perrno = -EBUSY;
933 break;
934
935 default:
936 /* invalid state, should never happen */
937 i40e_debug(hw, I40E_DEBUG_NVM,
938 "NVMUPD: no such state %d\n", hw->nvmupd_state);
939 status = I40E_NOT_SUPPORTED;
940 *perrno = -ESRCH;
941 break;
942 }
943
944 i40e_release_spinlock(&hw->aq.arq_spinlock);
938 return status;
939}
940
941/**
942 * i40e_nvmupd_state_init - Handle NVM update state Init
943 * @hw: pointer to hardware structure
944 * @cmd: pointer to nvm update command buffer
945 * @bytes: pointer to the data buffer

--- 113 unchanged lines hidden (view full) ---

1059 case I40E_NVMUPD_EXEC_AQ:
1060 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
1061 break;
1062
1063 case I40E_NVMUPD_GET_AQ_RESULT:
1064 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
1065 break;
1066
945 return status;
946}
947
948/**
949 * i40e_nvmupd_state_init - Handle NVM update state Init
950 * @hw: pointer to hardware structure
951 * @cmd: pointer to nvm update command buffer
952 * @bytes: pointer to the data buffer

--- 113 unchanged lines hidden (view full) ---

1066 case I40E_NVMUPD_EXEC_AQ:
1067 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
1068 break;
1069
1070 case I40E_NVMUPD_GET_AQ_RESULT:
1071 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
1072 break;
1073
1074 case I40E_NVMUPD_GET_AQ_EVENT:
1075 status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno);
1076 break;
1077
1067 default:
1068 i40e_debug(hw, I40E_DEBUG_NVM,
1069 "NVMUPD: bad cmd %s in init state\n",
1070 i40e_nvm_update_state_str[upd_cmd]);
1071 status = I40E_ERR_NVM;
1072 *perrno = -ESRCH;
1073 break;
1074 }

--- 162 unchanged lines hidden (view full) ---

1237 }
1238 }
1239 }
1240
1241 return status;
1242}
1243
1244/**
1078 default:
1079 i40e_debug(hw, I40E_DEBUG_NVM,
1080 "NVMUPD: bad cmd %s in init state\n",
1081 i40e_nvm_update_state_str[upd_cmd]);
1082 status = I40E_ERR_NVM;
1083 *perrno = -ESRCH;
1084 break;
1085 }

--- 162 unchanged lines hidden (view full) ---

1248 }
1249 }
1250 }
1251
1252 return status;
1253}
1254
1255/**
1245 * i40e_nvmupd_check_wait_event - handle NVM update operation events
1256 * i40e_nvmupd_clear_wait_state - clear wait state on hw
1246 * @hw: pointer to the hardware structure
1257 * @hw: pointer to the hardware structure
1247 * @opcode: the event that just happened
1248 **/
1258 **/
1249void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1259void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw)
1250{
1260{
1251 if (opcode == hw->nvm_wait_opcode) {
1261 i40e_debug(hw, I40E_DEBUG_NVM,
1262 "NVMUPD: clearing wait on opcode 0x%04x\n",
1263 hw->nvm_wait_opcode);
1252
1264
1253 i40e_debug(hw, I40E_DEBUG_NVM,
1254 "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1255 if (hw->nvm_release_on_done) {
1256 i40e_release_nvm(hw);
1257 hw->nvm_release_on_done = FALSE;
1258 }
1259 hw->nvm_wait_opcode = 0;
1265 if (hw->nvm_release_on_done) {
1266 i40e_release_nvm(hw);
1267 hw->nvm_release_on_done = FALSE;
1268 }
1269 hw->nvm_wait_opcode = 0;
1260
1270
1261 if (hw->aq.arq_last_status) {
1262 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1263 return;
1264 }
1271 if (hw->aq.arq_last_status) {
1272 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1273 return;
1274 }
1265
1275
1266 switch (hw->nvmupd_state) {
1267 case I40E_NVMUPD_STATE_INIT_WAIT:
1268 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1269 break;
1276 switch (hw->nvmupd_state) {
1277 case I40E_NVMUPD_STATE_INIT_WAIT:
1278 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1279 break;
1270
1280
1271 case I40E_NVMUPD_STATE_WRITE_WAIT:
1272 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1273 break;
1281 case I40E_NVMUPD_STATE_WRITE_WAIT:
1282 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1283 break;
1274
1284
1275 default:
1276 break;
1277 }
1285 default:
1286 break;
1278 }
1279}
1280
1281/**
1287 }
1288}
1289
1290/**
1291 * i40e_nvmupd_check_wait_event - handle NVM update operation events
1292 * @hw: pointer to the hardware structure
1293 * @opcode: the event that just happened
1294 * @desc: AdminQ descriptor
1295 **/
1296void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
1297 struct i40e_aq_desc *desc)
1298{
1299 u32 aq_desc_len = sizeof(struct i40e_aq_desc);
1300
1301 if (opcode == hw->nvm_wait_opcode) {
1302 i40e_memcpy(&hw->nvm_aq_event_desc, desc,
1303 aq_desc_len, I40E_NONDMA_TO_NONDMA);
1304 i40e_nvmupd_clear_wait_state(hw);
1305 }
1306}
1307
1308/**
1282 * i40e_nvmupd_validate_command - Validate given command
1283 * @hw: pointer to hardware structure
1284 * @cmd: pointer to nvm update command buffer
1285 * @perrno: pointer to return error code
1286 *
1287 * Return one of the valid command types or I40E_NVMUPD_INVALID
1288 **/
1289static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,

--- 37 unchanged lines hidden (view full) ---

1327 upd_cmd = I40E_NVMUPD_READ_SA;
1328 break;
1329 case I40E_NVM_EXEC:
1330 if (module == 0xf)
1331 upd_cmd = I40E_NVMUPD_STATUS;
1332 else if (module == 0)
1333 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1334 break;
1309 * i40e_nvmupd_validate_command - Validate given command
1310 * @hw: pointer to hardware structure
1311 * @cmd: pointer to nvm update command buffer
1312 * @perrno: pointer to return error code
1313 *
1314 * Return one of the valid command types or I40E_NVMUPD_INVALID
1315 **/
1316static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,

--- 37 unchanged lines hidden (view full) ---

1354 upd_cmd = I40E_NVMUPD_READ_SA;
1355 break;
1356 case I40E_NVM_EXEC:
1357 if (module == 0xf)
1358 upd_cmd = I40E_NVMUPD_STATUS;
1359 else if (module == 0)
1360 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1361 break;
1362 case I40E_NVM_AQE:
1363 upd_cmd = I40E_NVMUPD_GET_AQ_EVENT;
1364 break;
1335 }
1336 break;
1337
1338 case I40E_NVM_WRITE:
1339 switch (transaction) {
1340 case I40E_NVM_CON:
1341 upd_cmd = I40E_NVMUPD_WRITE_CON;
1342 break;

--- 46 unchanged lines hidden (view full) ---

1389 enum i40e_status_code status;
1390 struct i40e_aq_desc *aq_desc;
1391 u32 buff_size = 0;
1392 u8 *buff = NULL;
1393 u32 aq_desc_len;
1394 u32 aq_data_len;
1395
1396 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1365 }
1366 break;
1367
1368 case I40E_NVM_WRITE:
1369 switch (transaction) {
1370 case I40E_NVM_CON:
1371 upd_cmd = I40E_NVMUPD_WRITE_CON;
1372 break;

--- 46 unchanged lines hidden (view full) ---

1419 enum i40e_status_code status;
1420 struct i40e_aq_desc *aq_desc;
1421 u32 buff_size = 0;
1422 u8 *buff = NULL;
1423 u32 aq_desc_len;
1424 u32 aq_data_len;
1425
1426 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1427 if (cmd->offset == 0xffff)
1428 return I40E_SUCCESS;
1429
1397 memset(&cmd_details, 0, sizeof(cmd_details));
1398 cmd_details.wb_desc = &hw->nvm_wb_desc;
1399
1400 aq_desc_len = sizeof(struct i40e_aq_desc);
1401 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1402
1403 /* get the aq descriptor */
1404 if (cmd->data_size < aq_desc_len) {

--- 20 unchanged lines hidden (view full) ---

1425
1426 if (hw->nvm_buff.va) {
1427 buff = hw->nvm_buff.va;
1428 i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len,
1429 I40E_NONDMA_TO_NONDMA);
1430 }
1431 }
1432
1430 memset(&cmd_details, 0, sizeof(cmd_details));
1431 cmd_details.wb_desc = &hw->nvm_wb_desc;
1432
1433 aq_desc_len = sizeof(struct i40e_aq_desc);
1434 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1435
1436 /* get the aq descriptor */
1437 if (cmd->data_size < aq_desc_len) {

--- 20 unchanged lines hidden (view full) ---

1458
1459 if (hw->nvm_buff.va) {
1460 buff = hw->nvm_buff.va;
1461 i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len,
1462 I40E_NONDMA_TO_NONDMA);
1463 }
1464 }
1465
1466 if (cmd->offset)
1467 memset(&hw->nvm_aq_event_desc, 0, aq_desc_len);
1468
1433 /* and away we go! */
1434 status = i40e_asq_send_command(hw, aq_desc, buff,
1435 buff_size, &cmd_details);
1436 if (status) {
1437 i40e_debug(hw, I40E_DEBUG_NVM,
1438 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1439 i40e_stat_str(hw, status),
1440 i40e_aq_str(hw, hw->aq.asq_last_status));
1441 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1469 /* and away we go! */
1470 status = i40e_asq_send_command(hw, aq_desc, buff,
1471 buff_size, &cmd_details);
1472 if (status) {
1473 i40e_debug(hw, I40E_DEBUG_NVM,
1474 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1475 i40e_stat_str(hw, status),
1476 i40e_aq_str(hw, hw->aq.asq_last_status));
1477 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1478 return status;
1442 }
1443
1444 /* should we wait for a followup event? */
1445 if (cmd->offset) {
1446 hw->nvm_wait_opcode = cmd->offset;
1447 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1448 }
1449

--- 65 unchanged lines hidden (view full) ---

1515 __func__, start_byte, start_byte + remainder);
1516 i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA);
1517 }
1518
1519 return I40E_SUCCESS;
1520}
1521
1522/**
1479 }
1480
1481 /* should we wait for a followup event? */
1482 if (cmd->offset) {
1483 hw->nvm_wait_opcode = cmd->offset;
1484 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1485 }
1486

--- 65 unchanged lines hidden (view full) ---

1552 __func__, start_byte, start_byte + remainder);
1553 i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA);
1554 }
1555
1556 return I40E_SUCCESS;
1557}
1558
1559/**
1560 * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq
1561 * @hw: pointer to hardware structure
1562 * @cmd: pointer to nvm update command buffer
1563 * @bytes: pointer to the data buffer
1564 * @perrno: pointer to return error code
1565 *
1566 * cmd structure contains identifiers and data buffer
1567 **/
1568static enum i40e_status_code i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
1569 struct i40e_nvm_access *cmd,
1570 u8 *bytes, int *perrno)
1571{
1572 u32 aq_total_len;
1573 u32 aq_desc_len;
1574
1575 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1576
1577 aq_desc_len = sizeof(struct i40e_aq_desc);
1578 aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_aq_event_desc.datalen);
1579
1580 /* check copylength range */
1581 if (cmd->data_size > aq_total_len) {
1582 i40e_debug(hw, I40E_DEBUG_NVM,
1583 "%s: copy length %d too big, trimming to %d\n",
1584 __func__, cmd->data_size, aq_total_len);
1585 cmd->data_size = aq_total_len;
1586 }
1587
1588 i40e_memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size,
1589 I40E_NONDMA_TO_NONDMA);
1590
1591 return I40E_SUCCESS;
1592}
1593
1594/**
1523 * i40e_nvmupd_nvm_read - Read NVM
1524 * @hw: pointer to hardware structure
1525 * @cmd: pointer to nvm update command buffer
1526 * @bytes: pointer to the data buffer
1527 * @perrno: pointer to return error code
1528 *
1529 * cmd structure contains identifiers and data buffer
1530 **/

--- 78 unchanged lines hidden (view full) ---

1609 **/
1610static enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1611 struct i40e_nvm_access *cmd,
1612 u8 *bytes, int *perrno)
1613{
1614 enum i40e_status_code status = I40E_SUCCESS;
1615 struct i40e_asq_cmd_details cmd_details;
1616 u8 module, transaction;
1595 * i40e_nvmupd_nvm_read - Read NVM
1596 * @hw: pointer to hardware structure
1597 * @cmd: pointer to nvm update command buffer
1598 * @bytes: pointer to the data buffer
1599 * @perrno: pointer to return error code
1600 *
1601 * cmd structure contains identifiers and data buffer
1602 **/

--- 78 unchanged lines hidden (view full) ---

1681 **/
1682static enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1683 struct i40e_nvm_access *cmd,
1684 u8 *bytes, int *perrno)
1685{
1686 enum i40e_status_code status = I40E_SUCCESS;
1687 struct i40e_asq_cmd_details cmd_details;
1688 u8 module, transaction;
1689 u8 preservation_flags;
1617 bool last;
1618
1619 transaction = i40e_nvmupd_get_transaction(cmd->config);
1620 module = i40e_nvmupd_get_module(cmd->config);
1621 last = (transaction & I40E_NVM_LCB);
1690 bool last;
1691
1692 transaction = i40e_nvmupd_get_transaction(cmd->config);
1693 module = i40e_nvmupd_get_module(cmd->config);
1694 last = (transaction & I40E_NVM_LCB);
1695 preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config);
1622
1623 memset(&cmd_details, 0, sizeof(cmd_details));
1624 cmd_details.wb_desc = &hw->nvm_wb_desc;
1625
1626 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1627 (u16)cmd->data_size, bytes, last,
1696
1697 memset(&cmd_details, 0, sizeof(cmd_details));
1698 cmd_details.wb_desc = &hw->nvm_wb_desc;
1699
1700 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1701 (u16)cmd->data_size, bytes, last,
1628 &cmd_details);
1702 preservation_flags, &cmd_details);
1629 if (status) {
1630 i40e_debug(hw, I40E_DEBUG_NVM,
1631 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1632 module, cmd->offset, cmd->data_size);
1633 i40e_debug(hw, I40E_DEBUG_NVM,
1634 "i40e_nvmupd_nvm_write status %d aq %d\n",
1635 status, hw->aq.asq_last_status);
1636 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1637 }
1638
1639 return status;
1640}
1703 if (status) {
1704 i40e_debug(hw, I40E_DEBUG_NVM,
1705 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1706 module, cmd->offset, cmd->data_size);
1707 i40e_debug(hw, I40E_DEBUG_NVM,
1708 "i40e_nvmupd_nvm_write status %d aq %d\n",
1709 status, hw->aq.asq_last_status);
1710 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1711 }
1712
1713 return status;
1714}