ixgbe_common.c (54b4b13c4aeea1f00acd809286a9d7c9fa1accfa) ixgbe_common.c (7d48aa4c721a9c37619e27608f035f944ed4a5df)
1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2017, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:

--- 2085 unchanged lines hidden (view full) ---

2094 eec &= ~IXGBE_EEC_DI;
2095 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2096 IXGBE_WRITE_FLUSH(hw);
2097}
2098
2099/**
2100 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2101 * @hw: pointer to hardware structure
1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2017, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:

--- 2085 unchanged lines hidden (view full) ---

2094 eec &= ~IXGBE_EEC_DI;
2095 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2096 IXGBE_WRITE_FLUSH(hw);
2097}
2098
2099/**
2100 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2101 * @hw: pointer to hardware structure
2102 * @count: number of bits to shift
2102 **/
2103static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2104{
2105 u32 eec;
2106 u32 i;
2107 u16 data = 0;
2108
2109 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");

--- 42 unchanged lines hidden (view full) ---

2152 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2153 IXGBE_WRITE_FLUSH(hw);
2154 usec_delay(1);
2155}
2156
2157/**
2158 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2159 * @hw: pointer to hardware structure
2103 **/
2104static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2105{
2106 u32 eec;
2107 u32 i;
2108 u16 data = 0;
2109
2110 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");

--- 42 unchanged lines hidden (view full) ---

2153 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2154 IXGBE_WRITE_FLUSH(hw);
2155 usec_delay(1);
2156}
2157
2158/**
2159 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2160 * @hw: pointer to hardware structure
2160 * @eecd: EECD's current value
2161 * @eec: EEC's current value
2161 **/
2162static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2163{
2164 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2165
2166 /*
2167 * Lower the clock input to the EEPROM (clearing the SK bit), then
2168 * delay

--- 363 unchanged lines hidden (view full) ---

2532
2533 return IXGBE_SUCCESS;
2534}
2535
2536/**
2537 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2538 * @hw: pointer to hardware structure
2539 * @addr: new address
2162 **/
2163static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2164{
2165 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2166
2167 /*
2168 * Lower the clock input to the EEPROM (clearing the SK bit), then
2169 * delay

--- 363 unchanged lines hidden (view full) ---

2533
2534 return IXGBE_SUCCESS;
2535}
2536
2537/**
2538 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2539 * @hw: pointer to hardware structure
2540 * @addr: new address
2541 * @vmdq: VMDq "set" or "pool" index
2540 *
2541 * Adds it to unused receive address register or goes into promiscuous mode.
2542 **/
2543void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2544{
2545 u32 rar_entries = hw->mac.num_rar_entries;
2546 u32 rar;
2547

--- 128 unchanged lines hidden (view full) ---

2676 /* vector can only be 12-bits or boundary will be exceeded */
2677 vector &= 0xFFF;
2678 return vector;
2679}
2680
2681/**
2682 * ixgbe_set_mta - Set bit-vector in multicast table
2683 * @hw: pointer to hardware structure
2542 *
2543 * Adds it to unused receive address register or goes into promiscuous mode.
2544 **/
2545void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2546{
2547 u32 rar_entries = hw->mac.num_rar_entries;
2548 u32 rar;
2549

--- 128 unchanged lines hidden (view full) ---

2678 /* vector can only be 12-bits or boundary will be exceeded */
2679 vector &= 0xFFF;
2680 return vector;
2681}
2682
2683/**
2684 * ixgbe_set_mta - Set bit-vector in multicast table
2685 * @hw: pointer to hardware structure
2684 * @hash_value: Multicast address hash value
2686 * @mc_addr: Multicast address
2685 *
2686 * Sets the bit-vector in the multicast table.
2687 **/
2688void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2689{
2690 u32 vector;
2691 u32 vector_bit;
2692 u32 vector_reg;

--- 687 unchanged lines hidden (view full) ---

3380 "path fully disabled. Continuing with init.\n");
3381
3382 return IXGBE_SUCCESS;
3383}
3384
3385/**
3386 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3387 * @hw: pointer to hardware structure
2687 *
2688 * Sets the bit-vector in the multicast table.
2689 **/
2690void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2691{
2692 u32 vector;
2693 u32 vector_bit;
2694 u32 vector_reg;

--- 687 unchanged lines hidden (view full) ---

3382 "path fully disabled. Continuing with init.\n");
3383
3384 return IXGBE_SUCCESS;
3385}
3386
3387/**
3388 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3389 * @hw: pointer to hardware structure
3390 * @locked: bool to indicate whether the SW/FW lock was taken
3388 * @reg_val: Value we read from AUTOC
3389 *
3390 * The default case requires no protection so just to the register read.
3391 */
3392s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3393{
3394 *locked = FALSE;
3395 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);

--- 510 unchanged lines hidden (view full) ---

3906
3907 return IXGBE_SUCCESS;
3908}
3909
3910/**
3911 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3912 * @hw: pointer to hardware structure
3913 * @vlan: VLAN id to write to VLAN filter
3391 * @reg_val: Value we read from AUTOC
3392 *
3393 * The default case requires no protection so just to the register read.
3394 */
3395s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3396{
3397 *locked = FALSE;
3398 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);

--- 510 unchanged lines hidden (view full) ---

3909
3910 return IXGBE_SUCCESS;
3911}
3912
3913/**
3914 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3915 * @hw: pointer to hardware structure
3916 * @vlan: VLAN id to write to VLAN filter
3917 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
3918 * vlanid not found
3914 *
3919 *
3920 *
3915 * return the VLVF index where this VLAN id should be placed
3916 *
3917 **/
3918s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3919{
3920 s32 regindex, first_empty_slot;
3921 u32 bits;
3922

--- 325 unchanged lines hidden (view full) ---

4248 if (hw->mac.type == ixgbe_mac_X550) {
4249 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4250 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4251 }
4252 break;
4253 case IXGBE_LINKS_SPEED_10_X550EM_A:
4254 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4255 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3921 * return the VLVF index where this VLAN id should be placed
3922 *
3923 **/
3924s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3925{
3926 s32 regindex, first_empty_slot;
3927 u32 bits;
3928

--- 325 unchanged lines hidden (view full) ---

4254 if (hw->mac.type == ixgbe_mac_X550) {
4255 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4256 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4257 }
4258 break;
4259 case IXGBE_LINKS_SPEED_10_X550EM_A:
4260 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4261 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4256 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4262 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4257 *speed = IXGBE_LINK_SPEED_10_FULL;
4263 *speed = IXGBE_LINK_SPEED_10_FULL;
4258 }
4259 break;
4260 default:
4261 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4262 }
4263
4264 return IXGBE_SUCCESS;
4265}
4266

--- 311 unchanged lines hidden (view full) ---

4578 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4579 * else returns semaphore error when encountering an error acquiring
4580 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4581 **/
4582s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4583 u32 length, u32 timeout, bool return_data)
4584{
4585 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4264 break;
4265 default:
4266 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4267 }
4268
4269 return IXGBE_SUCCESS;
4270}
4271

--- 311 unchanged lines hidden (view full) ---

4583 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4584 * else returns semaphore error when encountering an error acquiring
4585 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4586 **/
4587s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4588 u32 length, u32 timeout, bool return_data)
4589{
4590 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4586 u16 dword_len;
4591 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4587 u16 buf_len;
4588 s32 status;
4589 u32 bi;
4592 u16 buf_len;
4593 s32 status;
4594 u32 bi;
4595 u32 dword_len;
4590
4591 DEBUGFUNC("ixgbe_host_interface_command");
4592
4593 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4594 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4595 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4596 }
4597

--- 13 unchanged lines hidden (view full) ---

4611 dword_len = hdr_size >> 2;
4612
4613 /* first pull in the header so we know the buffer length */
4614 for (bi = 0; bi < dword_len; bi++) {
4615 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4616 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4617 }
4618
4596
4597 DEBUGFUNC("ixgbe_host_interface_command");
4598
4599 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4600 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4601 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4602 }
4603

--- 13 unchanged lines hidden (view full) ---

4617 dword_len = hdr_size >> 2;
4618
4619 /* first pull in the header so we know the buffer length */
4620 for (bi = 0; bi < dword_len; bi++) {
4621 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4622 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4623 }
4624
4619 /* If there is any thing in data position pull it in */
4620 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4625 /*
4626 * If there is any thing in data position pull it in
4627 * Read Flash command requires reading buffer length from
4628 * two byes instead of one byte
4629 */
4630 if (resp->cmd == 0x30) {
4631 for (; bi < dword_len + 2; bi++) {
4632 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4633 bi);
4634 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4635 }
4636 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4637 & 0xF00) | resp->buf_len;
4638 hdr_size += (2 << 2);
4639 } else {
4640 buf_len = resp->buf_len;
4641 }
4621 if (!buf_len)
4622 goto rel_out;
4623
4624 if (length < buf_len + hdr_size) {
4625 DEBUGOUT("Buffer not large enough for reply message.\n");
4626 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4627 goto rel_out;
4628 }

--- 15 unchanged lines hidden (view full) ---

4644
4645/**
4646 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4647 * @hw: pointer to the HW structure
4648 * @maj: driver version major number
4649 * @min: driver version minor number
4650 * @build: driver version build number
4651 * @sub: driver version sub build number
4642 if (!buf_len)
4643 goto rel_out;
4644
4645 if (length < buf_len + hdr_size) {
4646 DEBUGOUT("Buffer not large enough for reply message.\n");
4647 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4648 goto rel_out;
4649 }

--- 15 unchanged lines hidden (view full) ---

4665
4666/**
4667 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4668 * @hw: pointer to the HW structure
4669 * @maj: driver version major number
4670 * @min: driver version minor number
4671 * @build: driver version build number
4672 * @sub: driver version sub build number
4673 * @len: unused
4674 * @driver_ver: unused
4652 *
4653 * Sends driver version number to firmware through the manageability
4654 * block. On success return IXGBE_SUCCESS
4655 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4656 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4657 **/
4658s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4659 u8 build, u8 sub, u16 len,

--- 10 unchanged lines hidden (view full) ---

4670 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4671 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4672 fw_cmd.port_num = (u8)hw->bus.func;
4673 fw_cmd.ver_maj = maj;
4674 fw_cmd.ver_min = min;
4675 fw_cmd.ver_build = build;
4676 fw_cmd.ver_sub = sub;
4677 fw_cmd.hdr.checksum = 0;
4675 *
4676 * Sends driver version number to firmware through the manageability
4677 * block. On success return IXGBE_SUCCESS
4678 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4679 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4680 **/
4681s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4682 u8 build, u8 sub, u16 len,

--- 10 unchanged lines hidden (view full) ---

4693 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4694 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4695 fw_cmd.port_num = (u8)hw->bus.func;
4696 fw_cmd.ver_maj = maj;
4697 fw_cmd.ver_min = min;
4698 fw_cmd.ver_build = build;
4699 fw_cmd.ver_sub = sub;
4700 fw_cmd.hdr.checksum = 0;
4678 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4679 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4680 fw_cmd.pad = 0;
4681 fw_cmd.pad2 = 0;
4701 fw_cmd.pad = 0;
4702 fw_cmd.pad2 = 0;
4703 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4704 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4682
4683 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4684 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4685 sizeof(fw_cmd),
4686 IXGBE_HI_COMMAND_TIMEOUT,
4687 TRUE);
4688 if (ret_val != IXGBE_SUCCESS)
4689 continue;

--- 372 unchanged lines hidden (view full) ---

5062 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5063 return IXGBE_ERR_INVALID_ARGUMENT;
5064
5065 *value = status & BYPASS_CTL2_DATA_M;
5066
5067 return IXGBE_SUCCESS;
5068}
5069
4705
4706 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4707 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4708 sizeof(fw_cmd),
4709 IXGBE_HI_COMMAND_TIMEOUT,
4710 TRUE);
4711 if (ret_val != IXGBE_SUCCESS)
4712 continue;

--- 372 unchanged lines hidden (view full) ---

5085 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5086 return IXGBE_ERR_INVALID_ARGUMENT;
5087
5088 *value = status & BYPASS_CTL2_DATA_M;
5089
5090 return IXGBE_SUCCESS;
5091}
5092
5093/**
5094 * ixgbe_get_orom_version - Return option ROM from EEPROM
5095 *
5096 * @hw: pointer to hardware structure
5097 * @nvm_ver: pointer to output structure
5098 *
5099 * if valid option ROM version, nvm_ver->or_valid set to TRUE
5100 * else nvm_ver->or_valid is FALSE.
5101 **/
5102void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5103 struct ixgbe_nvm_version *nvm_ver)
5104{
5105 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5070
5106
5107 nvm_ver->or_valid = FALSE;
5108 /* Option Rom may or may not be present. Start with pointer */
5109 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5110
5111 /* make sure offset is valid */
5112 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5113 return;
5114
5115 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5116 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5117
5118 /* option rom exists and is valid */
5119 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5120 eeprom_cfg_blkl == NVM_VER_INVALID ||
5121 eeprom_cfg_blkh == NVM_VER_INVALID)
5122 return;
5123
5124 nvm_ver->or_valid = TRUE;
5125 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5126 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5127 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5128 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5129}
5130
5071/**
5131/**
5132 * ixgbe_get_oem_prod_version - Return OEM Product version
5133 *
5134 * @hw: pointer to hardware structure
5135 * @nvm_ver: pointer to output structure
5136 *
5137 * if valid OEM product version, nvm_ver->oem_valid set to TRUE
5138 * else nvm_ver->oem_valid is FALSE.
5139 **/
5140void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5141 struct ixgbe_nvm_version *nvm_ver)
5142{
5143 u16 rel_num, prod_ver, mod_len, cap, offset;
5144
5145 nvm_ver->oem_valid = FALSE;
5146 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5147
5148 /* Return is offset to OEM Product Version block is invalid */
5149 if (offset == 0x0 && offset == NVM_INVALID_PTR)
5150 return;
5151
5152 /* Read product version block */
5153 hw->eeprom.ops.read(hw, offset, &mod_len);
5154 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5155
5156 /* Return if OEM product version block is invalid */
5157 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5158 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5159 return;
5160
5161 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5162 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5163
5164 /* Return if version is invalid */
5165 if ((rel_num | prod_ver) == 0x0 ||
5166 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5167 return;
5168
5169 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5170 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5171 nvm_ver->oem_release = rel_num;
5172 nvm_ver->oem_valid = TRUE;
5173}
5174
5175/**
5176 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5177 *
5178 * @hw: pointer to hardware structure
5179 * @nvm_ver: pointer to output structure
5180 *
5181 * word read errors will return 0xFFFF
5182 **/
5183void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5184{
5185 u16 etk_id_l, etk_id_h;
5186
5187 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5188 etk_id_l = NVM_VER_INVALID;
5189 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5190 etk_id_h = NVM_VER_INVALID;
5191
5192 /* The word order for the version format is determined by high order
5193 * word bit 15.
5194 */
5195 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5196 nvm_ver->etk_id = etk_id_h;
5197 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5198 } else {
5199 nvm_ver->etk_id = etk_id_l;
5200 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5201 }
5202}
5203
5204
5205/**
5072 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5073 * @hw: pointer to hardware structure
5074 * @map: pointer to u8 arr for returning map
5075 *
5076 * Read the rtrup2tc HW register and resolve its content into map
5077 **/
5078void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5079{

--- 53 unchanged lines hidden (view full) ---

5133bool ixgbe_mng_present(struct ixgbe_hw *hw)
5134{
5135 u32 fwsm;
5136
5137 if (hw->mac.type < ixgbe_mac_82599EB)
5138 return FALSE;
5139
5140 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5206 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5207 * @hw: pointer to hardware structure
5208 * @map: pointer to u8 arr for returning map
5209 *
5210 * Read the rtrup2tc HW register and resolve its content into map
5211 **/
5212void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5213{

--- 53 unchanged lines hidden (view full) ---

5267bool ixgbe_mng_present(struct ixgbe_hw *hw)
5268{
5269 u32 fwsm;
5270
5271 if (hw->mac.type < ixgbe_mac_82599EB)
5272 return FALSE;
5273
5274 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5141 fwsm &= IXGBE_FWSM_MODE_MASK;
5142 return fwsm == IXGBE_FWSM_FW_MODE_PT;
5275
5276 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5143}
5144
5145/**
5146 * ixgbe_mng_enabled - Is the manageability engine enabled?
5147 * @hw: pointer to hardware structure
5148 *
5149 * Returns TRUE if the manageability engine is enabled.
5150 **/

--- 234 unchanged lines hidden --- 		5277}
5278
5279/**
5280 * ixgbe_mng_enabled - Is the manageability engine enabled?
5281 * @hw: pointer to hardware structure
5282 *
5283 * Returns TRUE if the manageability engine is enabled.
5284 **/

--- 234 unchanged lines hidden ---