if_iwmreg.h (e7065dd1e84d0501b041f130773b391cfc491bad) if_iwmreg.h (355c15130aef13484821051a655da9b9066e1015)
1/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
2/* $FreeBSD$ */
1/* $OpenBSD: if_iwmreg.h,v 1.65 2021/10/11 09:03:22 stsp Exp $ */
3
4/******************************************************************************
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *

--- 47 unchanged lines hidden (view full) ---

58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *
65 *****************************************************************************/
2
3/******************************************************************************
4 *
5 * This file is provided under a dual BSD/GPLv2 license. When using or
6 * redistributing this file, you may do so under either license.
7 *
8 * GPL LICENSE SUMMARY
9 *

--- 47 unchanged lines hidden (view full) ---

57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65
66#ifndef __IF_IWM_REG_H__
67#define __IF_IWM_REG_H__
68
69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
71
72/*
73 * BEGIN iwl-csr.h

--- 114 unchanged lines hidden (view full) ---

188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
190
191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
193
194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
66#ifndef __IF_IWM_REG_H__
67#define __IF_IWM_REG_H__
68
69#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
71
72/*
73 * BEGIN iwl-csr.h

--- 114 unchanged lines hidden (view full) ---

188#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
190
191#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
193
194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
196#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
196#define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */

--- 6 unchanged lines hidden (view full) ---

211 IWM_CSR_INT_BIT_SW_ERR | \
212 IWM_CSR_INT_BIT_RF_KILL | \
213 IWM_CSR_INT_BIT_SW_RX | \
214 IWM_CSR_INT_BIT_WAKEUP | \
215 IWM_CSR_INT_BIT_ALIVE | \
216 IWM_CSR_INT_BIT_RX_PERIODIC)
217
218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
197#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
198#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
199#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
200#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
201#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
202#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
203#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
204#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */

--- 6 unchanged lines hidden (view full) ---

211 IWM_CSR_INT_BIT_SW_ERR | \
212 IWM_CSR_INT_BIT_RF_KILL | \
213 IWM_CSR_INT_BIT_SW_RX | \
214 IWM_CSR_INT_BIT_WAKEUP | \
215 IWM_CSR_INT_BIT_ALIVE | \
216 IWM_CSR_INT_BIT_RX_PERIODIC)
217
218/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
219#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
219#define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */
220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
225
226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \

--- 73 unchanged lines hidden (view full) ---

301 * hw_rev values
302 */
303enum {
304 IWM_SILICON_A_STEP = 0,
305 IWM_SILICON_B_STEP,
306 IWM_SILICON_C_STEP,
307};
308
220#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
221#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
222#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
223#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
224#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
225
226#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \

--- 73 unchanged lines hidden (view full) ---

301 * hw_rev values
302 */
303enum {
304 IWM_SILICON_A_STEP = 0,
305 IWM_SILICON_B_STEP,
306 IWM_SILICON_C_STEP,
307};
308
309
310#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
311#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
312#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
313#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
314#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
315#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
316#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
317#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)

--- 94 unchanged lines hidden (view full) ---

412
413/* ANA_PLL */
414#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
415
416/* HPET MEM debug */
417#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
418
419/* DRAM INT TABLE */
309#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
310#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
311#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
312#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
313#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
314#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
315#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
316#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)

--- 94 unchanged lines hidden (view full) ---

411
412/* ANA_PLL */
413#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
414
415/* HPET MEM debug */
416#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
417
418/* DRAM INT TABLE */
420#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
419#define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31)
421#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
422#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
423
424/* SECURE boot registers */
425#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
420#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
421#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
422
423/* SECURE boot registers */
424#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
426enum iwm_secure_boot_config_reg {
427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
429};
430
425#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001
426#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002
431#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
432#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
427#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
428#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
433enum iwm_secure_boot_status_reg {
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
439};
429#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003
430#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002
431#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004
432#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008
433#define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010
440
441#define IWM_FH_UCODE_LOAD_STATUS 0x1af0
434
435#define IWM_FH_UCODE_LOAD_STATUS 0x1af0
436
442#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
443
437#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
438
439/* 9000 rx series registers */
440
441#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
442#define IWM_RFH_Q_FRBDCB_BA_LSB(q) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
443/* Write index table */
444#define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080
445#define IWM_RFH_Q_FRBDCB_WIDX(q) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)
446/* Write index table - shadow registers */
447#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
448#define IWM_RFH_Q_FRBDCB_WIDX_TRG(q) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
449/* Read index table */
450#define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0
451#define IWM_RFH_Q_FRBDCB_RIDX(q) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)
452/* Used list table */
453#define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
454#define IWM_RFH_Q_URBDCB_BA_LSB(q) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
455/* Write index table */
456#define IWM_RFH_Q0_URBDCB_WIDX 0xA08180
457#define IWM_RFH_Q_URBDCB_WIDX(q) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)
458#define IWM_RFH_Q0_URBDCB_VAID 0xA081C0
459#define IWM_RFH_Q_URBDCB_VAID(q) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4)
460/* stts */
461#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
462#define IWM_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
463
464#define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280
465#define IWM_RFH_Q_ORB_WPTR_LSB(q) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8)
466#define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300
467#define IWM_RFH_RBDBUF_RBD_LSB(q) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8)
468
469/**
470 * RFH Status Register
471 *
472 * Bit fields:
473 *
474 * Bit 29: RBD_FETCH_IDLE
475 * This status flag is set by the RFH when there is no active RBD fetch from
476 * DRAM.
477 * Once the RFH RBD controller starts fetching (or when there is a pending
478 * RBD read response from DRAM), this flag is immediately turned off.
479 *
480 * Bit 30: SRAM_DMA_IDLE
481 * This status flag is set by the RFH when there is no active transaction from
482 * SRAM to DRAM.
483 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
484 *
485 * Bit 31: RXF_DMA_IDLE
486 * This status flag is set by the RFH when there is no active transaction from
487 * RXF to DRAM.
488 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
489 */
490#define IWM_RFH_GEN_STATUS 0xA09808
491#define IWM_RFH_GEN_STATUS_GEN3 0xA07824
492#define IWM_RBD_FETCH_IDLE (1 << 29)
493#define IWM_SRAM_DMA_IDLE (1 << 30)
494#define IWM_RXF_DMA_IDLE (1U << 31)
495
496/* DMA configuration */
497#define IWM_RFH_RXF_DMA_CFG 0xA09820
498#define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880
499/* RB size */
500#define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
501#define IWM_RFH_RXF_DMA_RB_SIZE_POS 16
502#define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
503#define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
504#define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
505#define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
506#define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
507#define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS)
508#define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS)
509#define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS)
510#define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS)
511#define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS)
512/* RB Circular Buffer size:defines the table sizes in RBD units */
513#define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
514#define IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20
515#define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
516#define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
517#define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
518#define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
519#define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
520#define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
521#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
522#define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
523#define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
524#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
525#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24
526#define IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS)
527#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
528#define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
529#define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
530#define IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31)
531
532#define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C
533
534#define IWM_RFH_GEN_CFG 0xA09800
535#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)
536#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)
537#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
538#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
539/* the driver assumes everywhere that the default RXQ is 0 */
540#define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
541
542/* end of 9000 rx series registers */
543
444#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
445#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
446
447#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
448#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
449
450#define IWM_CSR_SECURE_TIME_OUT (100)
451
452/* extended range in FW SRAM */
453#define IWM_FW_MEM_EXTENDED_START 0x40000
454#define IWM_FW_MEM_EXTENDED_END 0x57FFF
455
456/* FW chicken bits */
457#define IWM_LMPM_CHICK 0xa01ff8
458#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
459
544#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
545#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
546
547#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
548#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
549
550#define IWM_CSR_SECURE_TIME_OUT (100)
551
552/* extended range in FW SRAM */
553#define IWM_FW_MEM_EXTENDED_START 0x40000
554#define IWM_FW_MEM_EXTENDED_END 0x57FFF
555
556/* FW chicken bits */
557#define IWM_LMPM_CHICK 0xa01ff8
558#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
559
460#define IWM_UREG_CHICK 0xa05c00
461#define IWM_UREG_CHICK_MSI_ENABLE 0x01000000
462#define IWM_UREG_CHICK_MSIX_ENABLE 0x02000000
463
464#define IWM_FH_TCSR_0_REG0 (0x1D00)
465
466/*
467 * HBUS (Host-side Bus)
468 *
469 * HBUS registers are mapped directly into PCI bus space, but are used
470 * to indirectly access device's internal memory or registers that
471 * may be powered-down.

--- 53 unchanged lines hidden (view full) ---

525#define IWM_AUX_MISC_REG 0xa200b0
526#define IWM_HW_STEP_LOCATION_BITS 24
527
528#define IWM_AUX_MISC_MASTER1_EN 0xa20818
529#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
530#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
531#define IWM_RSA_ENABLE 0xa24b08
532#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
560#define IWM_FH_TCSR_0_REG0 (0x1D00)
561
562/*
563 * HBUS (Host-side Bus)
564 *
565 * HBUS registers are mapped directly into PCI bus space, but are used
566 * to indirectly access device's internal memory or registers that
567 * may be powered-down.

--- 53 unchanged lines hidden (view full) ---

621#define IWM_AUX_MISC_REG 0xa200b0
622#define IWM_HW_STEP_LOCATION_BITS 24
623
624#define IWM_AUX_MISC_MASTER1_EN 0xa20818
625#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
626#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
627#define IWM_RSA_ENABLE 0xa24b08
628#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
629#define IWM_PREG_PRPH_WPROT_9000 0xa04ce0
630#define IWM_PREG_PRPH_WPROT_22000 0xa04d00
533#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
534#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
535#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
536#define IWM_SB_MODIFY_CFG_FLAG 0xa03088
537#define IWM_SB_CPU_1_STATUS 0xa01e30
538#define IWM_SB_CPU_2_STATUS 0Xa01e34
539
631#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
632#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
633#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
634#define IWM_SB_MODIFY_CFG_FLAG 0xa03088
635#define IWM_SB_CPU_1_STATUS 0xa01e30
636#define IWM_SB_CPU_2_STATUS 0Xa01e34
637
638#define IWM_UREG_CHICK 0xa05c00
639#define IWM_UREG_CHICK_MSI_ENABLE (1 << 24)
640#define IWM_UREG_CHICK_MSIX_ENABLE (1 << 25)
641
642#define IWM_HPM_DEBUG 0xa03440
643#define IWM_HPM_PERSISTENCE_BIT (1 << 12)
644#define IWM_PREG_WFPM_ACCESS (1 << 12)
645
540/* Used to enable DBGM */
541#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
542
543/*
544 * Per-Tx-queue write pointer (index, really!)
545 * Indicates index to next TFD that driver will fill (1 past latest filled).
546 * Bit usage:
547 * 0-7: queue write index

--- 9 unchanged lines hidden (view full) ---

557 * used with setting interrupt coalescing timer
558 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
559 *
560 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
561 */
562#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
563#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
564#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
646/* Used to enable DBGM */
647#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
648
649/*
650 * Per-Tx-queue write pointer (index, really!)
651 * Indicates index to next TFD that driver will fill (1 past latest filled).
652 * Bit usage:
653 * 0-7: queue write index

--- 9 unchanged lines hidden (view full) ---

663 * used with setting interrupt coalescing timer
664 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
665 *
666 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
667 */
668#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
669#define IWM_HOST_INT_TIMEOUT_DEF (0x40)
670#define IWM_HOST_INT_TIMEOUT_MIN (0x0)
565#define IWM_HOST_INT_OPER_MODE (1 << 31)
671#define IWM_HOST_INT_OPER_MODE (1U << 31)
566
567/*****************************************************************************
568 * 7000/3000 series SHR DTS addresses *
569 *****************************************************************************/
570
571/* Diode Results Register Structure: */
672
673/*****************************************************************************
674 * 7000/3000 series SHR DTS addresses *
675 *****************************************************************************/
676
677/* Diode Results Register Structure: */
572enum iwm_dtd_diode_reg {
573 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
574 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
575 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
576 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
577 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
578 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
678#define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */
679#define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */
680#define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */
681#define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */
682#define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */
683#define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */
579/* Those are the masks INSIDE the flags bit-field: */
684/* Those are the masks INSIDE the flags bit-field: */
580 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
581 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
582 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
583 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
685#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0
686#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */
687#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7
688#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */
689
690/*****************************************************************************
691 * MSIX related registers *
692 *****************************************************************************/
693
694#define IWM_CSR_MSIX_BASE (0x2000)
695#define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800)
696#define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804)
697#define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808)
698#define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C)
699#define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810)
700#define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880)
701#define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890)
702#define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000)
703#define IWM_CSR_MSIX_RX_IVAR(cause) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause))
704#define IWM_CSR_MSIX_IVAR(cause) (IWM_CSR_MSIX_IVAR_AD_REG + (cause))
705
706/*
707 * Causes for the FH register interrupts
708 */
709enum msix_fh_int_causes {
710 IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0),
711 IWM_MSIX_FH_INT_CAUSES_Q1 = (1 << 1),
712 IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16),
713 IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17),
714 IWM_MSIX_FH_INT_CAUSES_S2D = (1 << 19),
715 IWM_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21),
584};
585
586/*
587 * END iwl-csr.h
588 */
589
590/*
591 * BEGIN iwl-fw.h
592 */
593
716};
717
718/*
719 * END iwl-csr.h
720 */
721
722/*
723 * BEGIN iwl-fw.h
724 */
725
726/*
727 * Causes for the HW register interrupts
728 */
729enum msix_hw_int_causes {
730 IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0),
731 IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1),
732 IWM_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1),
733 IWM_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2),
734 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5),
735 IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6),
736 IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7),
737 IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8),
738 IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25),
739 IWM_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26),
740 IWM_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27),
741 IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29),
742 IWM_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30),
743};
744
745/*
746 * Registers to map causes to vectors
747 */
748enum msix_ivar_for_cause {
749 IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0,
750 IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1,
751 IWM_MSIX_IVAR_CAUSE_S2D = 0x3,
752 IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5,
753 IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10,
754 IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11,
755 IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12,
756 IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16,
757 IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17,
758 IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18,
759 IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29,
760 IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a,
761 IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b,
762 IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d,
763 IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e,
764};
765
766#define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7)
767#define IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)
768
594/**
769/**
595 * enum iwm_ucode_tlv_flag - ucode API flags
770 * uCode API flags
596 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
597 * was a separate TLV but moved here to save space.
598 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
599 * treats good CRC threshold as a boolean
600 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
771 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
772 * was a separate TLV but moved here to save space.
773 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
774 * treats good CRC threshold as a boolean
775 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
776 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
777 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
601 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
602 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
603 * offload profile config command.
604 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
605 * (rather than two) IPv6 addresses
606 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
607 * from the probe request template.
608 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
609 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
778 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
779 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
780 * offload profile config command.
781 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
782 * (rather than two) IPv6 addresses
783 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
784 * from the probe request template.
785 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
786 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
787 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
788 * single bound interface).
610 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
611 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
612 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
613 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
789 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
790 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
791 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
792 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
793 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
794 *
614 */
795 */
615enum iwm_ucode_tlv_flag {
616 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
617 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
618 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
619 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
620 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
621 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
622 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
623 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
624 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
625 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
626 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
627 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
628};
796#define IWM_UCODE_TLV_FLAGS_PAN (1 << 0)
797#define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)
798#define IWM_UCODE_TLV_FLAGS_MFP (1 << 2)
799#define IWM_UCODE_TLV_FLAGS_P2P (1 << 3)
800#define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)
801#define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)
802#define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)
803#define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)
804#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)
805#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)
806#define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21)
807#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)
808#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)
809#define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)
810#define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)
811#define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)
812#define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)
813#define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)
814#define IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)
629
630#define IWM_UCODE_TLV_FLAG_BITS \
815
816#define IWM_UCODE_TLV_FLAG_BITS \
631 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
632Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
633L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
634P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
817 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
635
636/**
818
819/**
637 * enum iwm_ucode_tlv_api - ucode api
820 * uCode TLV api
638 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
639 * longer than the passive one, which is essential for fragmented scan.
640 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
821 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
822 * longer than the passive one, which is essential for fragmented scan.
823 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
824 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
641 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
642 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format
825 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
826 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format
827 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
828 * (command version 3) that supports per-chain limits
643 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
644 * iteration complete notification, and the timestamp reported for RX
645 * received during scan, are reported in TSF of the mac specified in the
646 * scan request.
647 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
648 * ADD_MODIFY_STA_KEY_API_S_VER_2.
649 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
829 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
830 * iteration complete notification, and the timestamp reported for RX
831 * received during scan, are reported in TSF of the mac specified in the
832 * scan request.
833 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
834 * ADD_MODIFY_STA_KEY_API_S_VER_2.
835 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
650 * @IWM_UCODE_TLV_API_NAN2_VER2: This ucode supports NAN API version 2
836 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
837 * instead of 3.
651 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
838 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
652 * @IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY: Quota command includes a field
653 * indicating low latency direction.
654 * @IWM_UCODE_TLV_API_DEPRECATE_TTAK: RX status flag TTAK ok (bit 7) is
655 * deprecated.
656 * @IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2: This ucode supports version 8
657 * of scan request: SCAN_REQUEST_CMD_UMAC_API_S_VER_8
658 * @IWM_UCODE_TLV_API_FRAG_EBS: This ucode supports fragmented EBS
659 * @IWM_UCODE_TLV_API_REDUCE_TX_POWER: This ucode supports v5 of
660 * the REDUCE_TX_POWER_CMD.
661 * @IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF: This ucode supports the short
662 * version of the beacon notification.
663 * @IWM_UCODE_TLV_API_BEACON_FILTER_V4: This ucode supports v4 of
664 * BEACON_FILTER_CONFIG_API_S_VER_4.
665 * @IWM_UCODE_TLV_API_REGULATORY_NVM_INFO: This ucode supports v4 of
666 * REGULATORY_NVM_GET_INFO_RSP_API_S.
667 * @IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ: This ucode supports v7 of
668 * LOCATION_RANGE_REQ_CMD_API_S and v6 of LOCATION_RANGE_RESP_NTFY_API_S.
669 * @IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS: This ucode supports v2 of
670 * SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S and v3 of
671 * SCAN_OFFLOAD_PROFILES_QUERY_RSP_S.
672 * @IWM_UCODE_TLV_API_MBSSID_HE: This ucode supports v2 of
673 * STA_CONTEXT_DOT11AX_API_S
674 * @IWM_UCODE_TLV_CAPA_SAR_TABLE_VER: This ucode supports different sar
675 * version tables.
676 *
677 * @IWM_NUM_UCODE_TLV_API: number of bits used
678 */
839 *
840 * @IWM_NUM_UCODE_TLV_API: number of bits used
841 */
679enum iwm_ucode_tlv_api {
680 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8,
681 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9,
682 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18,
683 IWM_UCODE_TLV_API_NEW_VERSION = 20,
684 IWM_UCODE_TLV_API_SCAN_TSF_REPORT = 28,
685 IWM_UCODE_TLV_API_TKIP_MIC_KEYS = 29,
686 IWM_UCODE_TLV_API_STA_TYPE = 30,
687 IWM_UCODE_TLV_API_NAN2_VER2 = 31,
688 IWM_UCODE_TLV_API_ADAPTIVE_DWELL = 32,
689 IWM_UCODE_TLV_API_OCE = 33,
690 IWM_UCODE_TLV_API_NEW_BEACON_TEMPLATE = 34,
691 IWM_UCODE_TLV_API_NEW_RX_STATS = 35,
692 IWM_UCODE_TLV_API_WOWLAN_KEY_MATERIAL = 36,
693 IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY = 38,
694 IWM_UCODE_TLV_API_DEPRECATE_TTAK = 41,
695 IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = 42,
696 IWM_UCODE_TLV_API_FRAG_EBS = 44,
697 IWM_UCODE_TLV_API_REDUCE_TX_POWER = 45,
698 IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF = 46,
699 IWM_UCODE_TLV_API_BEACON_FILTER_V4 = 47,
700 IWM_UCODE_TLV_API_REGULATORY_NVM_INFO = 48,
701 IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ = 49,
702 IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS = 50,
703 IWM_UCODE_TLV_API_MBSSID_HE = 52,
704 IWM_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE = 53,
705 IWM_UCODE_TLV_API_FTM_RTT_ACCURACY = 54,
706 IWM_UCODE_TLV_API_SAR_TABLE_VER = 55,
707 IWM_UCODE_TLV_API_ADWELL_HB_DEF_N_AP = 57,
708 IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER = 58,
842#define IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8
843#define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9
844#define IWM_UCODE_TLV_API_WIDE_CMD_HDR 14
845#define IWM_UCODE_TLV_API_LQ_SS_PARAMS 18
846#define IWM_UCODE_TLV_API_NEW_VERSION 20
847#define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24
848#define IWM_UCODE_TLV_API_TX_POWER_CHAIN 27
849#define IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28
850#define IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29
851#define IWM_UCODE_TLV_API_STA_TYPE 30
852#define IWM_UCODE_TLV_API_NAN2_VER2 31
853#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32
854#define IWM_UCODE_TLV_API_NEW_RX_STATS 35
855#define IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38
856#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42
857#define IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58
858#define IWM_NUM_UCODE_TLV_API 128
709
859
710 IWM_NUM_UCODE_TLV_API = 128,
711};
860#define IWM_UCODE_TLV_API_BITS \
861 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"
712
713/**
862
863/**
714 * enum iwm_ucode_tlv_capa - ucode capabilities
864 * uCode capabilities
715 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
716 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
717 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
718 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
719 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
720 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
721 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
722 * tx power value into TPC Report action frame and Link Measurement Report

--- 35 unchanged lines hidden (view full) ---

758 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
759 * thresholds reporting
760 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
761 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
762 * regular image.
763 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
764 * memory addresses from the firmware.
765 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
865 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
866 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
867 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
868 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
869 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
870 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
871 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
872 * tx power value into TPC Report action frame and Link Measurement Report

--- 35 unchanged lines hidden (view full) ---

908 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
909 * thresholds reporting
910 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
911 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
912 * regular image.
913 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
914 * memory addresses from the firmware.
915 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
766 * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger
767 * command size (command version 4) that supports toggling ACK TX
768 * power reduction.
916 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
917 * 0=no support)
769 *
770 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
771 */
918 *
919 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
920 */
772enum iwm_ucode_tlv_capa {
773 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
774 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
775 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
776 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
777 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
778 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
779 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
780 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
781 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
782 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
783 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
784 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
785 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
786 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
787 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
788 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
789 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
790 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
791 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
792 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
793 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
794 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
795 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
796 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
797 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
798 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
799 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
800 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
801 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
802 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
803 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
804 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
805 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
806 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
807 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
808 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
809 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
810 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
811 IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84,
921#define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0
922#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1
923#define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2
924#define IWM_UCODE_TLV_CAPA_BEAMFORMER 3
925#define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5
926#define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6
927#define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8
928#define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9
929#define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10
930#define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11
931#define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12
932#define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13
933#define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17
934#define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18
935#define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19
936#define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20
937#define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21
938#define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22
939#define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26
940#define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28
941#define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29
942#define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30
943#define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31
944#define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34
945#define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35
946#define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37
947#define IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39
948#define IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40
949#define IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44
950#define IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48
951#define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64
952#define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65
953#define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67
954#define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68
955#define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71
956#define IWM_UCODE_TLV_CAPA_BEACON_STORING 72
957#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73
958#define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74
959#define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75
960#define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76
961#define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77
962#define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79
963#define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80
964#define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81
812
965
813 IWM_NUM_UCODE_TLV_CAPA = 128
814};
966#define IWM_NUM_UCODE_TLV_CAPA 128
815
816/* The default calibrate table size if not specified by firmware file */
817#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
818#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
819#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
820
821/* The default max probe length if not specified by the firmware file */
822#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
823
824/*
967
968/* The default calibrate table size if not specified by firmware file */
969#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
970#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
971#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
972
973/* The default max probe length if not specified by the firmware file */
974#define IWM_DEFAULT_MAX_PROBE_LENGTH 200
975
976/*
825 * enumeration of ucode section.
826 * This enumeration is used directly for older firmware (before 16.0).
827 * For new firmware, there can be up to 4 sections (see below) but the
828 * first one packaged into the firmware file is the DATA section and
829 * some debugging code accesses that.
830 */
831enum iwm_ucode_sec {
832 IWM_UCODE_SECTION_DATA,
833 IWM_UCODE_SECTION_INST,
834};
835/*
836 * For 16.0 uCode and above, there is no differentiation between sections,
837 * just an offset to the HW address.
838 */
839#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
840#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
841
842/* uCode version contains 4 values: Major/Minor/API/Serial */
843#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)

--- 9 unchanged lines hidden (view full) ---

853 * @event_trigger: bitmap for which calibrations to perform according to
854 * event triggers.
855 */
856struct iwm_tlv_calib_ctrl {
857 uint32_t flow_trigger;
858 uint32_t event_trigger;
859} __packed;
860
977 * For 16.0 uCode and above, there is no differentiation between sections,
978 * just an offset to the HW address.
979 */
980#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
981#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
982
983/* uCode version contains 4 values: Major/Minor/API/Serial */
984#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)

--- 9 unchanged lines hidden (view full) ---

994 * @event_trigger: bitmap for which calibrations to perform according to
995 * event triggers.
996 */
997struct iwm_tlv_calib_ctrl {
998 uint32_t flow_trigger;
999 uint32_t event_trigger;
1000} __packed;
1001
861enum iwm_fw_phy_cfg {
862 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
863 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
864 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
865 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
866 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
867 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
868 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
869 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
870 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
871 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
872};
1002#define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0
1003#define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS)
1004#define IWM_FW_PHY_CFG_RADIO_STEP_POS 2
1005#define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS)
1006#define IWM_FW_PHY_CFG_RADIO_DASH_POS 4
1007#define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS)
1008#define IWM_FW_PHY_CFG_TX_CHAIN_POS 16
1009#define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS)
1010#define IWM_FW_PHY_CFG_RX_CHAIN_POS 20
1011#define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS)
873
874#define IWM_UCODE_MAX_CS 1
875
876/**
877 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
878 * @cipher: a cipher suite selector
879 * @flags: cipher scheme flags (currently reserved for a future use)
880 * @hdr_len: a size of MPDU security header

--- 92 unchanged lines hidden (view full) ---

973 IWM_UCODE_TLV_SEC_WOWLAN = 21,
974 IWM_UCODE_TLV_DEF_CALIB = 22,
975 IWM_UCODE_TLV_PHY_SKU = 23,
976 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
977 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
978 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
979 IWM_UCODE_TLV_NUM_OF_CPU = 27,
980 IWM_UCODE_TLV_CSCHEME = 28,
1012
1013#define IWM_UCODE_MAX_CS 1
1014
1015/**
1016 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
1017 * @cipher: a cipher suite selector
1018 * @flags: cipher scheme flags (currently reserved for a future use)
1019 * @hdr_len: a size of MPDU security header

--- 92 unchanged lines hidden (view full) ---

1112 IWM_UCODE_TLV_SEC_WOWLAN = 21,
1113 IWM_UCODE_TLV_DEF_CALIB = 22,
1114 IWM_UCODE_TLV_PHY_SKU = 23,
1115 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
1116 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
1117 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
1118 IWM_UCODE_TLV_NUM_OF_CPU = 27,
1119 IWM_UCODE_TLV_CSCHEME = 28,
981
982 /*
983 * Following two are not in our base tag, but allow
984 * handling ucode version 9.
985 */
986 IWM_UCODE_TLV_API_CHANGES_SET = 29,
987 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
1120 /*
1121 * Following two are not in our base tag, but allow
1122 * handling ucode version 9.
1123 */
1124 IWM_UCODE_TLV_API_CHANGES_SET = 29,
1125 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
988
989 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
990 IWM_UCODE_TLV_PAGING = 32,
991 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
992 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
993 IWM_UCODE_TLV_FW_VERSION = 36,
994 IWM_UCODE_TLV_FW_DBG_DEST = 38,
995 IWM_UCODE_TLV_FW_DBG_CONF = 39,
996 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
997 IWM_UCODE_TLV_CMD_VERSIONS = 48,
998 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
999 IWM_UCODE_TLV_FW_MEM_SEG = 51,
1126 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
1127 IWM_UCODE_TLV_PAGING = 32,
1128 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
1129 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
1130 IWM_UCODE_TLV_FW_VERSION = 36,
1131 IWM_UCODE_TLV_FW_DBG_DEST = 38,
1132 IWM_UCODE_TLV_FW_DBG_CONF = 39,
1133 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
1134 IWM_UCODE_TLV_CMD_VERSIONS = 48,
1135 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
1136 IWM_UCODE_TLV_FW_MEM_SEG = 51,
1137 IWM_UCODE_TLV_UMAC_DEBUG_ADDRS = 54,
1138 IWM_UCODE_TLV_LMAC_DEBUG_ADDRS = 55,
1139 IWM_UCODE_TLV_HW_TYPE = 58,
1000};
1001
1140};
1141
1142#define IWM_UCODE_TLV_DEBUG_BASE 0x1000005
1143#define IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0)
1144#define IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWM_UCODE_TLV_DEBUG_BASE + 1)
1145#define IWM_UCODE_TLV_TYPE_HCMD (IWM_UCODE_TLV_DEBUG_BASE + 2)
1146#define IWM_UCODE_TLV_TYPE_REGIONS (IWM_UCODE_TLV_DEBUG_BASE + 3)
1147#define IWM_UCODE_TLV_TYPE_TRIGGERS (IWM_UCODE_TLV_DEBUG_BASE + 4)
1148#define IWM_UCODE_TLV_DEBUG_MAX IWM_UCODE_TLV_TYPE_TRIGGERS
1149
1002struct iwm_ucode_tlv {
1003 uint32_t type; /* see above */
1004 uint32_t length; /* not including type/length fields */
1005 uint8_t data[0];
1006};
1007
1008struct iwm_ucode_api {
1009 uint32_t api_index;

--- 81 unchanged lines hidden (view full) ---

1091#define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1092#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1093#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1094#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1095
1096/*
1097 * Device reset for family 8000
1098 * write to bit 24 in order to reset the CPU
1150struct iwm_ucode_tlv {
1151 uint32_t type; /* see above */
1152 uint32_t length; /* not including type/length fields */
1153 uint8_t data[0];
1154};
1155
1156struct iwm_ucode_api {
1157 uint32_t api_index;

--- 81 unchanged lines hidden (view full) ---

1239#define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1240#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1241#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1242#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1243
1244/*
1245 * Device reset for family 8000
1246 * write to bit 24 in order to reset the CPU
1099 */
1247*/
1100#define IWM_RELEASE_CPU_RESET 0x300c
1101#define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1102
1103
1104/*****************************************************************************
1105 * 7000/3000 series SHR DTS addresses *
1106 *****************************************************************************/
1107

--- 418 unchanged lines hidden (view full) ---

1526#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1527#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1528 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1529
1530#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1531
1532#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1533
1248#define IWM_RELEASE_CPU_RESET 0x300c
1249#define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1250
1251
1252/*****************************************************************************
1253 * 7000/3000 series SHR DTS addresses *
1254 *****************************************************************************/
1255

--- 418 unchanged lines hidden (view full) ---

1674#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1675#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1676 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1677
1678#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1679
1680#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1681
1534/* 9000 rx series registers */
1535
1536#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xa08000
1537#define IWM_RFH_Q_FRBDCB_BA_LSB (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
1538/* Write index table */
1539#define IWM_RFH_Q0_FRBDCB_WIDX 0xa08080
1540#define IWM_RFH_Q_FRBDCB_WIDX (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)
1541/* Write index table - shadow registers */
1542#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1c80
1543#define IWM_RFH_Q_FRBDCB_WIDX_TRG (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
1544/* Read index table */
1545#define IWM_RFH_Q0_FRBDCB_RIDX 0xa080c0
1546#define IWM_RFH_Q_FRBDCB_RIDX (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)
1547/* Used list table */
1548#define IWM_RFH_Q0_URBDCB_BA_LSB 0xa08100
1549#define IWM_RFH_Q_URBDCB_BA_LSB (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
1550/* Write index table */
1551#define IWM_RFH_Q0_URBDCB_WIDX 0xa08180
1552#define IWM_RFH_Q_URBDCB_WIDX (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)
1553/* stts */
1554#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xa08200
1555#define IWM_RFH_Q_URBD_STTS_WPTR_LSB (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
1556
1557#define IWM_RFH_GEN_STATUS 0xa09808
1558#define IWM_RXF_DMA_IDLE 0x80000000
1559
1560/* DMA configuration */
1561#define IWM_RFH_RXF_DMA_CFG 0xa09820
1562#define IWM_RFH_RXF_DMA_RB_SIZE_1K 0x00010000
1563#define IWM_RFH_RXF_DMA_RB_SIZE_2K 0x00020000
1564#define IWM_RFH_RXF_DMA_RB_SIZE_4K 0x00040000
1565#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 0x00900000
1566#define IWM_RFH_RXF_DMA_MIN_RB_4_8 0x03000000
1567#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK 0x04000000
1568#define IWM_RFH_DMA_EN_ENABLE_VAL 0x80000000
1569
1570#define IWM_RFH_GEN_CFG 0xa09800
1571#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP 0x00000001
1572#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP 0x00000002
1573#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
1574#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
1575
1576#define IWM_RFH_RXF_RXQ_ACTIVE 0xa0980c
1577
1578/* end of 9000 rx series registers */
1579
1580/* TFDB Area - TFDs buffer table */
1581#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1582#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1583#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1584#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1585#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1586
1587/**

--- 212 unchanged lines hidden (view full) ---

1800 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1801 * @tfd_offset 0-12 - tx command byte count
1802 * 12-16 - station index
1803 */
1804struct iwm_agn_scd_bc_tbl {
1805 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1806} __packed;
1807
1682/* TFDB Area - TFDs buffer table */
1683#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1684#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1685#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1686#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1687#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1688
1689/**

--- 212 unchanged lines hidden (view full) ---

1902 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1903 * @tfd_offset 0-12 - tx command byte count
1904 * 12-16 - station index
1905 */
1906struct iwm_agn_scd_bc_tbl {
1907 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1908} __packed;
1909
1910
1808/*
1809 * END iwl-fh.h
1810 */
1811
1812/*
1813 * BEGIN mvm/fw-api.h
1814 */
1815
1911/*
1912 * END iwl-fh.h
1913 */
1914
1915/*
1916 * BEGIN mvm/fw-api.h
1917 */
1918
1919#define IWM_TX_CRC_SIZE 4
1920#define IWM_TX_DELIMITER_SIZE 4
1921
1816/* Maximum number of Tx queues. */
1817#define IWM_MAX_QUEUES 31
1818
1922/* Maximum number of Tx queues. */
1923#define IWM_MAX_QUEUES 31
1924
1819/* Tx queue numbers */
1820enum {
1821 IWM_OFFCHANNEL_QUEUE = 8,
1822 IWM_CMD_QUEUE = 9,
1823 IWM_AUX_QUEUE = 15,
1824};
1925/**
1926 * DQA - Dynamic Queue Allocation -introduction
1927 *
1928 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi
1929 * to allow dynamic allocation of queues on-demand, rather than allocate them
1930 * statically ahead of time. Ideally, we would like to allocate one queue
1931 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2
1932 * even if it also needs to send traffic to a sleeping STA1, without being
1933 * blocked by the sleeping station.
1934 *
1935 * Although the queues in DQA mode are dynamically allocated, there are still
1936 * some queues that are statically allocated:
1937 * TXQ #0 - command queue
1938 * TXQ #1 - aux frames
1939 * TXQ #2 - P2P device frames
1940 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames
1941 * TXQ #4 - BSS DATA frames queue
1942 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool
1943 * TXQ #9 - P2P GO/SoftAP probe responses
1944 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation)
1945 */
1825
1946
1826enum iwm_tx_fifo {
1827 IWM_TX_FIFO_BK = 0,
1828 IWM_TX_FIFO_BE,
1829 IWM_TX_FIFO_VI,
1830 IWM_TX_FIFO_VO,
1831 IWM_TX_FIFO_MCAST = 5,
1832 IWM_TX_FIFO_CMD = 7,
1833};
1947/* static DQA Tx queue numbers */
1948#define IWM_DQA_CMD_QUEUE 0
1949#define IWM_DQA_AUX_QUEUE 1
1950#define IWM_DQA_P2P_DEVICE_QUEUE 2
1951#define IWM_DQA_INJECT_MONITOR_QUEUE 2
1952#define IWM_DQA_GCAST_QUEUE 3
1953#define IWM_DQA_BSS_CLIENT_QUEUE 4
1954#define IWM_DQA_MIN_MGMT_QUEUE 5
1955#define IWM_DQA_MAX_MGMT_QUEUE 8
1956#define IWM_DQA_AP_PROBE_RESP_QUEUE 9
1957#define IWM_DQA_MIN_DATA_QUEUE 10
1958#define IWM_DQA_MAX_DATA_QUEUE 31
1834
1959
1960/* Reserve 8 DQA Tx queues, from 10 up to 17, for A-MPDU aggregation. */
1961#define IWM_MAX_TID_COUNT 8
1962#define IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE
1963#define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1)
1964
1965/* legacy non-DQA queues; the legacy command queue uses a different number! */
1966#define IWM_OFFCHANNEL_QUEUE 8
1967#define IWM_CMD_QUEUE 9
1968#define IWM_AUX_QUEUE 15
1969
1970#define IWM_TX_FIFO_BK 0
1971#define IWM_TX_FIFO_BE 1
1972#define IWM_TX_FIFO_VI 2
1973#define IWM_TX_FIFO_VO 3
1974#define IWM_TX_FIFO_MCAST 5
1975#define IWM_TX_FIFO_CMD 7
1976
1835#define IWM_STATION_COUNT 16
1836
1977#define IWM_STATION_COUNT 16
1978
1837/* commands */
1838enum {
1839 IWM_ALIVE = 0x1,
1840 IWM_REPLY_ERROR = 0x2,
1979/*
1980 * Commands
1981 */
1982#define IWM_ALIVE 0x1
1983#define IWM_REPLY_ERROR 0x2
1984#define IWM_INIT_COMPLETE_NOTIF 0x4
1841
1985
1842 IWM_INIT_COMPLETE_NOTIF = 0x4,
1986/* PHY context commands */
1987#define IWM_PHY_CONTEXT_CMD 0x8
1988#define IWM_DBG_CFG 0x9
1843
1989
1844 /* PHY context commands */
1845 IWM_PHY_CONTEXT_CMD = 0x8,
1846 IWM_DBG_CFG = 0x9,
1990/* UMAC scan commands */
1991#define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5
1992#define IWM_SCAN_CFG_CMD 0xc
1993#define IWM_SCAN_REQ_UMAC 0xd
1994#define IWM_SCAN_ABORT_UMAC 0xe
1995#define IWM_SCAN_COMPLETE_UMAC 0xf
1847
1996
1848 /* UMAC scan commands */
1849 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1850 IWM_SCAN_CFG_CMD = 0xc,
1851 IWM_SCAN_REQ_UMAC = 0xd,
1852 IWM_SCAN_ABORT_UMAC = 0xe,
1853 IWM_SCAN_COMPLETE_UMAC = 0xf,
1997/* station table */
1998#define IWM_ADD_STA_KEY 0x17
1999#define IWM_ADD_STA 0x18
2000#define IWM_REMOVE_STA 0x19
1854
2001
1855 /* station table */
1856 IWM_ADD_STA_KEY = 0x17,
1857 IWM_ADD_STA = 0x18,
1858 IWM_REMOVE_STA = 0x19,
2002/* TX */
2003#define IWM_TX_CMD 0x1c
2004#define IWM_TXPATH_FLUSH 0x1e
2005#define IWM_MGMT_MCAST_KEY 0x1f
1859
2006
1860 /* TX */
1861 IWM_TX_CMD = 0x1c,
1862 IWM_TXPATH_FLUSH = 0x1e,
1863 IWM_MGMT_MCAST_KEY = 0x1f,
2007/* scheduler config */
2008#define IWM_SCD_QUEUE_CFG 0x1d
1864
2009
1865 /* scheduler config */
1866 IWM_SCD_QUEUE_CFG = 0x1d,
2010/* global key */
2011#define IWM_WEP_KEY 0x20
1867
2012
1868 /* global key */
1869 IWM_WEP_KEY = 0x20,
2013/* MAC and Binding commands */
2014#define IWM_MAC_CONTEXT_CMD 0x28
2015#define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */
2016#define IWM_TIME_EVENT_NOTIFICATION 0x2a
2017#define IWM_BINDING_CONTEXT_CMD 0x2b
2018#define IWM_TIME_QUOTA_CMD 0x2c
2019#define IWM_NON_QOS_TX_COUNTER_CMD 0x2d
1870
2020
1871 /* MAC and Binding commands */
1872 IWM_MAC_CONTEXT_CMD = 0x28,
1873 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1874 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1875 IWM_BINDING_CONTEXT_CMD = 0x2b,
1876 IWM_TIME_QUOTA_CMD = 0x2c,
1877 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
2021#define IWM_LQ_CMD 0x4e
1878
2022
1879 IWM_LQ_CMD = 0x4e,
2023/* Calibration */
2024#define IWM_TEMPERATURE_NOTIFICATION 0x62
2025#define IWM_CALIBRATION_CFG_CMD 0x65
2026#define IWM_CALIBRATION_RES_NOTIFICATION 0x66
2027#define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67
2028#define IWM_RADIO_VERSION_NOTIFICATION 0x68
1880
2029
1881 /* paging block to FW cpu2 */
1882 IWM_FW_PAGING_BLOCK_CMD = 0x4f,
2030/* paging block to FW cpu2 */
2031#define IWM_FW_PAGING_BLOCK_CMD 0x4f
1883
2032
1884 /* Scan offload */
1885 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1886 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1887 IWM_HOT_SPOT_CMD = 0x53,
1888 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1889 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1890 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1891 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1892 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
2033/* Scan offload */
2034#define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51
2035#define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52
2036#define IWM_HOT_SPOT_CMD 0x53
2037#define IWM_SCAN_OFFLOAD_COMPLETE 0x6d
2038#define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e
2039#define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f
2040#define IWM_MATCH_FOUND_NOTIFICATION 0xd9
2041#define IWM_SCAN_ITERATION_COMPLETE 0xe7
1893
2042
1894 /* Phy */
1895 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1896 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1897 IWM_PHY_DB_CMD = 0x6c,
2043/* Phy */
2044#define IWM_PHY_CONFIGURATION_CMD 0x6a
2045#define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b
2046#define IWM_PHY_DB_CMD 0x6c
1898
2047
1899 /* Power - legacy power table command */
1900 IWM_POWER_TABLE_CMD = 0x77,
1901 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1902 IWM_LTR_CONFIG = 0xee,
2048/* Power - legacy power table command */
2049#define IWM_POWER_TABLE_CMD 0x77
2050#define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78
2051#define IWM_LTR_CONFIG 0xee
1903
2052
1904 /* Thermal Throttling*/
1905 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
2053/* Thermal Throttling*/
2054#define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e
1906
2055
1907 /* NVM */
1908 IWM_NVM_ACCESS_CMD = 0x88,
2056/* NVM */
2057#define IWM_NVM_ACCESS_CMD 0x88
1909
2058
1910 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
2059#define IWM_SET_CALIB_DEFAULT_CMD 0x8e
1911
2060
1912 IWM_BEACON_NOTIFICATION = 0x90,
1913 IWM_BEACON_TEMPLATE_CMD = 0x91,
1914 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1915 IWM_BT_CONFIG = 0x9b,
1916 IWM_STATISTICS_NOTIFICATION = 0x9d,
1917 IWM_REDUCE_TX_POWER_CMD = 0x9f,
2061#define IWM_BEACON_NOTIFICATION 0x90
2062#define IWM_BEACON_TEMPLATE_CMD 0x91
2063#define IWM_TX_ANT_CONFIGURATION_CMD 0x98
2064#define IWM_BT_CONFIG 0x9b
2065#define IWM_STATISTICS_NOTIFICATION 0x9d
2066#define IWM_REDUCE_TX_POWER_CMD 0x9f
1918
2067
1919 /* RF-KILL commands and notifications */
1920 IWM_CARD_STATE_CMD = 0xa0,
1921 IWM_CARD_STATE_NOTIFICATION = 0xa1,
2068/* RF-KILL commands and notifications */
2069#define IWM_CARD_STATE_CMD 0xa0
2070#define IWM_CARD_STATE_NOTIFICATION 0xa1
1922
2071
1923 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
2072#define IWM_MISSED_BEACONS_NOTIFICATION 0xa2
1924
2073
1925 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
2074#define IWM_MFUART_LOAD_NOTIFICATION 0xb1
1926
2075
1927 /* Power - new power table command */
1928 IWM_MAC_PM_POWER_TABLE = 0xa9,
2076/* Power - new power table command */
2077#define IWM_MAC_PM_POWER_TABLE 0xa9
1929
2078
1930 IWM_REPLY_RX_PHY_CMD = 0xc0,
1931 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1932 IWM_BA_NOTIF = 0xc5,
2079#define IWM_REPLY_RX_PHY_CMD 0xc0
2080#define IWM_REPLY_RX_MPDU_CMD 0xc1
2081#define IWM_BA_NOTIF 0xc5
1933
2082
1934 /* Location Aware Regulatory */
1935 IWM_MCC_UPDATE_CMD = 0xc8,
1936 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
2083/* Location Aware Regulatory */
2084#define IWM_MCC_UPDATE_CMD 0xc8
2085#define IWM_MCC_CHUB_UPDATE_CMD 0xc9
1937
2086
1938 /* BT Coex */
1939 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1940 IWM_BT_COEX_PROT_ENV = 0xcd,
1941 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1942 IWM_BT_COEX_CI = 0x5d,
2087/* BT Coex */
2088#define IWM_BT_COEX_PRIO_TABLE 0xcc
2089#define IWM_BT_COEX_PROT_ENV 0xcd
2090#define IWM_BT_PROFILE_NOTIFICATION 0xce
2091#define IWM_BT_COEX_CI 0x5d
1943
2092
1944 IWM_REPLY_SF_CFG_CMD = 0xd1,
1945 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
2093#define IWM_REPLY_SF_CFG_CMD 0xd1
2094#define IWM_REPLY_BEACON_FILTERING_CMD 0xd2
1946
2095
1947 /* DTS measurements */
1948 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1949 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
2096/* DTS measurements */
2097#define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc
2098#define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd
1950
2099
1951 IWM_REPLY_DEBUG_CMD = 0xf0,
1952 IWM_DEBUG_LOG_MSG = 0xf7,
2100#define IWM_REPLY_DEBUG_CMD 0xf0
2101#define IWM_DEBUG_LOG_MSG 0xf7
1953
2102
1954 IWM_MCAST_FILTER_CMD = 0xd0,
2103#define IWM_MCAST_FILTER_CMD 0xd0
1955
2104
1956 /* D3 commands/notifications */
1957 IWM_D3_CONFIG_CMD = 0xd3,
1958 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1959 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1960 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
2105/* D3 commands/notifications */
2106#define IWM_D3_CONFIG_CMD 0xd3
2107#define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4
2108#define IWM_OFFLOADS_QUERY_CMD 0xd5
2109#define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6
1961
2110
1962 /* for WoWLAN in particular */
1963 IWM_WOWLAN_PATTERNS = 0xe0,
1964 IWM_WOWLAN_CONFIGURATION = 0xe1,
1965 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1966 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1967 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1968 IWM_WOWLAN_GET_STATUSES = 0xe5,
1969 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
2111/* for WoWLAN in particular */
2112#define IWM_WOWLAN_PATTERNS 0xe0
2113#define IWM_WOWLAN_CONFIGURATION 0xe1
2114#define IWM_WOWLAN_TSC_RSC_PARAM 0xe2
2115#define IWM_WOWLAN_TKIP_PARAM 0xe3
2116#define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4
2117#define IWM_WOWLAN_GET_STATUSES 0xe5
2118#define IWM_WOWLAN_TX_POWER_PER_DB 0xe6
1970
2119
1971 /* and for NetDetect */
1972 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1973 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1974 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1975 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1976 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1977};
2120/* and for NetDetect */
2121#define IWM_NET_DETECT_CONFIG_CMD 0x54
2122#define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56
2123#define IWM_NET_DETECT_PROFILES_CMD 0x57
2124#define IWM_NET_DETECT_HOTSPOTS_CMD 0x58
2125#define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59
1978
2126
1979enum iwm_phy_ops_subcmd_ids {
1980 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0,
1981 IWM_CTDP_CONFIG_CMD = 0x03,
1982 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
1983 IWM_CT_KILL_NOTIFICATION = 0xFE,
1984 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF,
1985};
2127/* system group command IDs */
2128#define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff
1986
2129
2130#define IWM_REPLY_MAX 0xff
2131
2132/* PHY_OPS subcommand IDs */
2133#define IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0
2134#define IWM_CTDP_CONFIG_CMD 0x03
2135#define IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04
2136#define IWM_CT_KILL_NOTIFICATION 0xFE
2137#define IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF
2138
1987/* command groups */
2139/* command groups */
1988enum {
1989 IWM_LEGACY_GROUP = 0x0,
1990 IWM_LONG_GROUP = 0x1,
1991 IWM_SYSTEM_GROUP = 0x2,
1992 IWM_MAC_CONF_GROUP = 0x3,
1993 IWM_PHY_OPS_GROUP = 0x4,
1994 IWM_DATA_PATH_GROUP = 0x5,
1995 IWM_PROT_OFFLOAD_GROUP = 0xb,
1996};
2140#define IWM_LEGACY_GROUP 0x0
2141#define IWM_LONG_GROUP 0x1
2142#define IWM_SYSTEM_GROUP 0x2
2143#define IWM_MAC_CONF_GROUP 0x3
2144#define IWM_PHY_OPS_GROUP 0x4
2145#define IWM_DATA_PATH_GROUP 0x5
2146#define IWM_PROT_OFFLOAD_GROUP 0xb
1997
2147
2148/* SYSTEM_GROUP group subcommand IDs */
2149
2150#define IWM_SHARED_MEM_CFG_CMD 0x00
2151#define IWM_SOC_CONFIGURATION_CMD 0x01
2152#define IWM_INIT_EXTENDED_CFG_CMD 0x03
2153#define IWM_FW_ERROR_RECOVERY_CMD 0x07
2154
2155/* DATA_PATH group subcommand IDs */
2156#define IWM_DQA_ENABLE_CMD 0x00
2157
2158/*
2159 * struct iwm_dqa_enable_cmd
2160 * @cmd_queue: the TXQ number of the command queue
2161 */
2162struct iwm_dqa_enable_cmd {
2163 uint32_t cmd_queue;
2164} __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */
2165
1998/**
1999 * struct iwm_cmd_response - generic response struct for most commands
2000 * @status: status of the command asked, changes for each one
2001 */
2002struct iwm_cmd_response {
2003 uint32_t status;
2004};
2005

--- 13 unchanged lines hidden (view full) ---

2019 * @pwr_restriction: TX power restriction in dBms.
2020 */
2021struct iwm_reduce_tx_power_cmd {
2022 uint8_t flags;
2023 uint8_t mac_context_id;
2024 uint16_t pwr_restriction;
2025} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
2026
2166/**
2167 * struct iwm_cmd_response - generic response struct for most commands
2168 * @status: status of the command asked, changes for each one
2169 */
2170struct iwm_cmd_response {
2171 uint32_t status;
2172};
2173

--- 13 unchanged lines hidden (view full) ---

2187 * @pwr_restriction: TX power restriction in dBms.
2188 */
2189struct iwm_reduce_tx_power_cmd {
2190 uint8_t flags;
2191 uint8_t mac_context_id;
2192 uint16_t pwr_restriction;
2193} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
2194
2027enum iwm_dev_tx_power_cmd_mode {
2028 IWM_TX_POWER_MODE_SET_MAC = 0,
2029 IWM_TX_POWER_MODE_SET_DEVICE = 1,
2030 IWM_TX_POWER_MODE_SET_CHAINS = 2,
2031 IWM_TX_POWER_MODE_SET_ACK = 3,
2032}; /* TX_POWER_REDUCED_FLAGS_TYPE_API_E_VER_4 */;
2033
2034#define IWM_NUM_CHAIN_LIMITS 2
2035#define IWM_NUM_SUB_BANDS 5
2036
2037/**
2038 * struct iwm_dev_tx_power_cmd - TX power reduction command
2039 * @set_mode: see &enum iwl_dev_tx_power_cmd_mode
2040 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
2041 * @pwr_restriction: TX power restriction in 1/8 dBms.
2042 * @dev_24: device TX power restriction in 1/8 dBms
2043 * @dev_52_low: device TX power restriction upper band - low
2044 * @dev_52_high: device TX power restriction upper band - high
2045 * @per_chain_restriction: per chain restrictions
2046 */
2047struct iwm_dev_tx_power_cmd_v3 {
2048 uint32_t set_mode;
2049 uint32_t mac_context_id;
2050 uint16_t pwr_restriction;
2051 uint16_t dev_24;
2052 uint16_t dev_52_low;
2053 uint16_t dev_52_high;
2054 uint16_t per_chain_restriction[IWM_NUM_CHAIN_LIMITS][IWM_NUM_SUB_BANDS];
2055} __packed; /* TX_REDUCED_POWER_API_S_VER_3 */
2056
2057#define IWM_DEV_MAX_TX_POWER 0x7FFF
2058
2059/**
2060 * struct iwm_dev_tx_power_cmd - TX power reduction command
2061 * @v3: version 3 of the command, embedded here for easier software handling
2062 * @enable_ack_reduction: enable or disable close range ack TX power
2063 * reduction.
2064 */
2065struct iwm_dev_tx_power_cmd {
2066 /* v4 is just an extension of v3 - keep this here */
2067 struct iwm_dev_tx_power_cmd_v3 v3;
2068 uint8_t enable_ack_reduction;
2069 uint8_t reserved[3];
2070} __packed; /* TX_REDUCED_POWER_API_S_VER_4 */
2071
2072/*
2073 * Calibration control struct.
2074 * Sent as part of the phy configuration command.
2075 * @flow_trigger: bitmap for which calibrations to perform according to
2076 * flow triggers.
2077 * @event_trigger: bitmap for which calibrations to perform according to
2078 * event triggers.
2079 */
2080struct iwm_calib_ctrl {
2081 uint32_t flow_trigger;
2082 uint32_t event_trigger;
2083} __packed;
2084
2195/*
2196 * Calibration control struct.
2197 * Sent as part of the phy configuration command.
2198 * @flow_trigger: bitmap for which calibrations to perform according to
2199 * flow triggers.
2200 * @event_trigger: bitmap for which calibrations to perform according to
2201 * event triggers.
2202 */
2203struct iwm_calib_ctrl {
2204 uint32_t flow_trigger;
2205 uint32_t event_trigger;
2206} __packed;
2207
2085/* This enum defines the bitmap of various calibrations to enable in both
2208/* This defines the bitmap of various calibrations to enable in both
2086 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
2087 */
2209 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
2210 */
2088enum iwm_calib_cfg {
2089 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
2090 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
2091 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
2092 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
2093 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
2094 IWM_CALIB_CFG_DC_IDX = (1 << 5),
2095 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
2096 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
2097 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
2098 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
2099 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
2100 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
2101 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
2102 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
2103 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
2104 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
2105 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
2106 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
2107 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
2108};
2211#define IWM_CALIB_CFG_XTAL_IDX (1 << 0)
2212#define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1)
2213#define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)
2214#define IWM_CALIB_CFG_PAPD_IDX (1 << 3)
2215#define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4)
2216#define IWM_CALIB_CFG_DC_IDX (1 << 5)
2217#define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6)
2218#define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)
2219#define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8)
2220#define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)
2221#define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10)
2222#define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)
2223#define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12)
2224#define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)
2225#define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)
2226#define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)
2227#define IWM_CALIB_CFG_DAC_IDX (1 << 16)
2228#define IWM_CALIB_CFG_ABS_IDX (1 << 17)
2229#define IWM_CALIB_CFG_AGC_IDX (1 << 18)
2109
2110/*
2111 * Phy configuration command.
2112 */
2113struct iwm_phy_cfg_cmd {
2114 uint32_t phy_cfg;
2115 struct iwm_calib_ctrl calib_control;
2116} __packed;

--- 4 unchanged lines hidden (view full) ---

2121#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2122#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
2123#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
2124#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
2125#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
2126#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
2127#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
2128
2230
2231/*
2232 * Phy configuration command.
2233 */
2234struct iwm_phy_cfg_cmd {
2235 uint32_t phy_cfg;
2236 struct iwm_calib_ctrl calib_control;
2237} __packed;

--- 4 unchanged lines hidden (view full) ---

2242#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2243#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
2244#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
2245#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
2246#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
2247#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
2248#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
2249
2250#define IWM_MAX_DTS_TRIPS 8
2129
2251
2130/* Target of the IWM_NVM_ACCESS_CMD */
2131enum {
2132 IWM_NVM_ACCESS_TARGET_CACHE = 0,
2133 IWM_NVM_ACCESS_TARGET_OTP = 1,
2134 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
2252/**
2253 * struct iwm_ct_kill_notif - CT-kill entry notification
2254 *
2255 * @temperature: the current temperature in celsius
2256 * @reserved: reserved
2257 */
2258struct iwm_ct_kill_notif {
2259 uint16_t temperature;
2260 uint16_t reserved;
2261} __packed; /* GRP_PHY_CT_KILL_NTF */
2262
2263/**
2264 * struct iwm_temp_report_ths_cmd - set temperature thresholds
2265 * (IWM_TEMP_REPORTING_THRESHOLDS_CMD)
2266 *
2267 * @num_temps: number of temperature thresholds passed
2268 * @thresholds: array with the thresholds to be configured
2269 */
2270struct iwm_temp_report_ths_cmd {
2271 uint32_t num_temps;
2272 uint16_t thresholds[IWM_MAX_DTS_TRIPS];
2273} __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */
2274
2275/*
2276 * PHY db
2277 */
2278
2279enum iwm_phy_db_section_type {
2280 IWM_PHY_DB_CFG = 1,
2281 IWM_PHY_DB_CALIB_NCH,
2282 IWM_PHY_DB_UNUSED,
2283 IWM_PHY_DB_CALIB_CHG_PAPD,
2284 IWM_PHY_DB_CALIB_CHG_TXP,
2285 IWM_PHY_DB_MAX
2135};
2136
2286};
2287
2288/*
2289 * phy db - configure operational ucode
2290 */
2291struct iwm_phy_db_cmd {
2292 uint16_t type;
2293 uint16_t length;
2294 uint8_t data[];
2295} __packed;
2296
2297/* for parsing of tx power channel group data that comes from the firmware*/
2298struct iwm_phy_db_chg_txp {
2299 uint32_t space;
2300 uint16_t max_channel_idx;
2301} __packed;
2302
2303/*
2304 * phy db - Receive phy db chunk after calibrations
2305 */
2306struct iwm_calib_res_notif_phy_db {
2307 uint16_t type;
2308 uint16_t length;
2309 uint8_t data[];
2310} __packed;
2311
2312/* 7k family NVM HW-Section offset (in words) definitions */
2313#define IWM_HW_ADDR 0x15
2314/* 7k family NVM SW-Section offset (in words) definitions */
2315#define IWM_NVM_SW_SECTION 0x1C0
2316#define IWM_NVM_VERSION 0
2317#define IWM_RADIO_CFG 1
2318#define IWM_SKU 2
2319#define IWM_N_HW_ADDRS 3
2320#define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION
2321/* 7k family NVM calibration section offset (in words) definitions */
2322#define IWM_NVM_CALIB_SECTION 0x2B8
2323#define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION)
2324
2325/* 8k family NVM HW-Section offset (in words) definitions */
2326#define IWM_HW_ADDR0_WFPM_8000 0x12
2327#define IWM_HW_ADDR1_WFPM_8000 0x16
2328#define IWM_HW_ADDR0_PCIE_8000 0x8A
2329#define IWM_HW_ADDR1_PCIE_8000 0x8E
2330#define IWM_MAC_ADDRESS_OVERRIDE_8000 1
2331
2332/* 8k family NVM SW-Section offset (in words) definitions */
2333#define IWM_NVM_SW_SECTION_8000 0x1C0
2334#define IWM_NVM_VERSION_8000 0
2335#define IWM_RADIO_CFG_8000 0
2336#define IWM_SKU_8000 2
2337#define IWM_N_HW_ADDRS_8000 3
2338
2339/* 8k family NVM REGULATORY -Section offset (in words) definitions */
2340#define IWM_NVM_CHANNELS_8000 0
2341#define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7
2342#define IWM_NVM_LAR_OFFSET_8000 0x507
2343#define IWM_NVM_LAR_ENABLED_8000 0x7
2344
2345/* 8k family NVM calibration section offset (in words) definitions */
2346#define IWM_NVM_CALIB_SECTION_8000 0x2B8
2347#define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000)
2348
2349/* SKU Capabilities (actual values from NVM definition) */
2350#define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0)
2351#define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1)
2352#define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2)
2353#define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3)
2354#define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5)
2355
2356/* radio config bits (actual values from NVM definition) */
2357#define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
2358#define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
2359#define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
2360#define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
2361#define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
2362#define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
2363
2364#define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF)
2365#define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF)
2366#define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF)
2367#define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF)
2368#define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF)
2369#define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF)
2370
2371/*
2372 * channel flags in NVM
2373 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo
2374 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel
2375 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed
2376 * @IWM_NVM_CHANNEL_RADAR: radar detection required
2377 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate
2378 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
2379 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
2380 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
2381 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
2382 */
2383#define IWM_NVM_CHANNEL_VALID (1 << 0)
2384#define IWM_NVM_CHANNEL_IBSS (1 << 1)
2385#define IWM_NVM_CHANNEL_ACTIVE (1 << 3)
2386#define IWM_NVM_CHANNEL_RADAR (1 << 4)
2387#define IWM_NVM_CHANNEL_DFS (1 << 7)
2388#define IWM_NVM_CHANNEL_WIDE (1 << 8)
2389#define IWM_NVM_CHANNEL_40MHZ (1 << 9)
2390#define IWM_NVM_CHANNEL_80MHZ (1 << 10)
2391#define IWM_NVM_CHANNEL_160MHZ (1 << 11)
2392
2393/* Target of the IWM_NVM_ACCESS_CMD */
2394#define IWM_NVM_ACCESS_TARGET_CACHE 0
2395#define IWM_NVM_ACCESS_TARGET_OTP 1
2396#define IWM_NVM_ACCESS_TARGET_EEPROM 2
2397
2137/* Section types for IWM_NVM_ACCESS_CMD */
2398/* Section types for IWM_NVM_ACCESS_CMD */
2138enum {
2139 IWM_NVM_SECTION_TYPE_SW = 1,
2140 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
2141 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
2142 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
2143 IWM_NVM_SECTION_TYPE_REGULATORY_SDP = 8,
2144 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
2145 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
2146 IWM_NVM_MAX_NUM_SECTIONS = 13,
2147};
2399#define IWM_NVM_SECTION_TYPE_HW 0
2400#define IWM_NVM_SECTION_TYPE_SW 1
2401#define IWM_NVM_SECTION_TYPE_PAPD 2
2402#define IWM_NVM_SECTION_TYPE_REGULATORY 3
2403#define IWM_NVM_SECTION_TYPE_CALIBRATION 4
2404#define IWM_NVM_SECTION_TYPE_PRODUCTION 5
2405#define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6
2406/* 7 unknown */
2407#define IWM_NVM_SECTION_TYPE_REGULATORY_SDP 8
2408/* 9 unknown */
2409#define IWM_NVM_SECTION_TYPE_HW_8000 10
2410#define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11
2411#define IWM_NVM_SECTION_TYPE_PHY_SKU 12
2412#define IWM_NVM_NUM_OF_SECTIONS 13
2148
2149/**
2150 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2151 * @op_code: 0 - read, 1 - write
2152 * @target: IWM_NVM_ACCESS_TARGET_*
2153 * @type: IWM_NVM_SECTION_TYPE_*
2154 * @offset: offset in bytes into the section
2155 * @length: in bytes, to read/write
2156 * @data: if write operation, the data to write. On read its empty
2157 */
2158struct iwm_nvm_access_cmd {
2159 uint8_t op_code;
2160 uint8_t target;
2161 uint16_t type;
2162 uint16_t offset;
2163 uint16_t length;
2164 uint8_t data[];
2165} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2166
2413
2414/**
2415 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2416 * @op_code: 0 - read, 1 - write
2417 * @target: IWM_NVM_ACCESS_TARGET_*
2418 * @type: IWM_NVM_SECTION_TYPE_*
2419 * @offset: offset in bytes into the section
2420 * @length: in bytes, to read/write
2421 * @data: if write operation, the data to write. On read its empty
2422 */
2423struct iwm_nvm_access_cmd {
2424 uint8_t op_code;
2425 uint8_t target;
2426 uint16_t type;
2427 uint16_t offset;
2428 uint16_t length;
2429 uint8_t data[];
2430} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2431
2167#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
2432/*
2433 * Block paging calculations
2434 */
2435#define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */
2436#define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */
2437#define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3
2438/* 8 pages per group */
2439#define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE)
2440/* don't change, support only 32KB size */
2441#define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE)
2442/* 32K == 2^15 */
2443#define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE)
2168
2169/*
2444
2445/*
2446 * Image paging calculations
2447 */
2448#define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5
2449/* 2^5 == 32 blocks per image */
2450#define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE)
2451/* maximum image size 1024KB */
2452#define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE)
2453
2454/* Virtual address signature */
2455#define IWM_PAGING_ADDR_SIG 0xAA000000
2456
2457#define IWM_PAGING_CMD_IS_SECURED (1 << 9)
2458#define IWM_PAGING_CMD_IS_ENABLED (1 << 8)
2459#define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0
2460#define IWM_PAGING_TLV_SECURE_MASK 1
2461
2462#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
2463
2464/*
2170 * struct iwm_fw_paging_cmd - paging layout
2171 *
2172 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2173 *
2174 * Send to FW the paging layout in the driver.
2175 *
2176 * @flags: various flags for the command
2177 * @block_size: the block size in powers of 2
2178 * @block_num: number of blocks specified in the command.
2179 * @device_phy_addr: virtual addresses from device side
2180*/
2181struct iwm_fw_paging_cmd {
2182 uint32_t flags;
2183 uint32_t block_size;
2184 uint32_t block_num;
2185 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];
2186} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */
2187
2465 * struct iwm_fw_paging_cmd - paging layout
2466 *
2467 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2468 *
2469 * Send to FW the paging layout in the driver.
2470 *
2471 * @flags: various flags for the command
2472 * @block_size: the block size in powers of 2
2473 * @block_num: number of blocks specified in the command.
2474 * @device_phy_addr: virtual addresses from device side
2475*/
2476struct iwm_fw_paging_cmd {
2477 uint32_t flags;
2478 uint32_t block_size;
2479 uint32_t block_num;
2480 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];
2481} __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */
2482
2188/*
2189 * Fw items ID's
2190 *
2191 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload
2192 * download
2193 */
2194enum iwm_fw_item_id {
2195 IWM_FW_ITEM_ID_PAGING = 3,
2196};
2197
2198/*
2199 * struct iwm_fw_get_item_cmd - get an item from the fw
2200 */
2201struct iwm_fw_get_item_cmd {
2202 uint32_t item_id;
2203} __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */
2204
2205/**
2206 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2207 * @offset: offset in bytes into the section
2208 * @length: in bytes, either how much was written or read
2209 * @type: IWM_NVM_SECTION_TYPE_*
2210 * @status: 0 for success, fail otherwise
2211 * @data: if read operation, the data returned. Empty on write.
2212 */

--- 7 unchanged lines hidden (view full) ---

2220
2221/* IWM_ALIVE 0x1 */
2222
2223/* alive response is_valid values */
2224#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2225#define IWM_ALIVE_RESP_RFKILL (1 << 1)
2226
2227/* alive response ver_type values */
2483/**
2484 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2485 * @offset: offset in bytes into the section
2486 * @length: in bytes, either how much was written or read
2487 * @type: IWM_NVM_SECTION_TYPE_*
2488 * @status: 0 for success, fail otherwise
2489 * @data: if read operation, the data returned. Empty on write.
2490 */

--- 7 unchanged lines hidden (view full) ---

2498
2499/* IWM_ALIVE 0x1 */
2500
2501/* alive response is_valid values */
2502#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2503#define IWM_ALIVE_RESP_RFKILL (1 << 1)
2504
2505/* alive response ver_type values */
2228enum {
2229 IWM_FW_TYPE_HW = 0,
2230 IWM_FW_TYPE_PROT = 1,
2231 IWM_FW_TYPE_AP = 2,
2232 IWM_FW_TYPE_WOWLAN = 3,
2233 IWM_FW_TYPE_TIMING = 4,
2234 IWM_FW_TYPE_WIPAN = 5
2235};
2506#define IWM_FW_TYPE_HW 0
2507#define IWM_FW_TYPE_PROT 1
2508#define IWM_FW_TYPE_AP 2
2509#define IWM_FW_TYPE_WOWLAN 3
2510#define IWM_FW_TYPE_TIMING 4
2511#define IWM_FW_TYPE_WIPAN 5
2236
2237/* alive response ver_subtype values */
2512
2513/* alive response ver_subtype values */
2238enum {
2239 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2240 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2241 IWM_FW_SUBTYPE_REDUCED = 2,
2242 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2243 IWM_FW_SUBTYPE_WOWLAN = 4,
2244 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2245 IWM_FW_SUBTYPE_WIPAN = 6,
2246 IWM_FW_SUBTYPE_INITIALIZE = 9
2247};
2514#define IWM_FW_SUBTYPE_FULL_FEATURE 0
2515#define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */
2516#define IWM_FW_SUBTYPE_REDUCED 2
2517#define IWM_FW_SUBTYPE_ALIVE_ONLY 3
2518#define IWM_FW_SUBTYPE_WOWLAN 4
2519#define IWM_FW_SUBTYPE_AP_SUBTYPE 5
2520#define IWM_FW_SUBTYPE_WIPAN 6
2521#define IWM_FW_SUBTYPE_INITIALIZE 9
2248
2249#define IWM_ALIVE_STATUS_ERR 0xDEAD
2250#define IWM_ALIVE_STATUS_OK 0xCAFE
2251
2252#define IWM_ALIVE_FLG_RFKILL (1 << 0)
2253
2254struct iwm_lmac_alive {
2255 uint32_t ucode_major;

--- 9 unchanged lines hidden (view full) ---

2265 uint32_t dbgm_config_ptr;
2266 uint32_t alive_counter_ptr;
2267 uint32_t scd_base_ptr; /* SRAM address for SCD */
2268 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2269 uint32_t st_fwrd_size;
2270} __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */
2271
2272struct iwm_umac_alive {
2522
2523#define IWM_ALIVE_STATUS_ERR 0xDEAD
2524#define IWM_ALIVE_STATUS_OK 0xCAFE
2525
2526#define IWM_ALIVE_FLG_RFKILL (1 << 0)
2527
2528struct iwm_lmac_alive {
2529 uint32_t ucode_major;

--- 9 unchanged lines hidden (view full) ---

2539 uint32_t dbgm_config_ptr;
2540 uint32_t alive_counter_ptr;
2541 uint32_t scd_base_ptr; /* SRAM address for SCD */
2542 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2543 uint32_t st_fwrd_size;
2544} __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */
2545
2546struct iwm_umac_alive {
2273 uint32_t umac_major; /* UMAC version: major */
2274 uint32_t umac_minor; /* UMAC version: minor */
2275 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2547 uint32_t umac_major; /* UMAC version: major */
2548 uint32_t umac_minor; /* UMAC version: minor */
2549 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2276 uint32_t dbg_print_buff_addr;
2277} __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */
2278
2279struct iwm_alive_resp_v3 {
2280 uint16_t status;
2281 uint16_t flags;
2282 struct iwm_lmac_alive lmac_data;
2283 struct iwm_umac_alive umac_data;
2284} __packed; /* ALIVE_RES_API_S_VER_3 */
2285
2286struct iwm_alive_resp {
2287 uint16_t status;
2288 uint16_t flags;
2289 struct iwm_lmac_alive lmac_data[2];
2290 struct iwm_umac_alive umac_data;
2550 uint32_t dbg_print_buff_addr;
2551} __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */
2552
2553struct iwm_alive_resp_v3 {
2554 uint16_t status;
2555 uint16_t flags;
2556 struct iwm_lmac_alive lmac_data;
2557 struct iwm_umac_alive umac_data;
2558} __packed; /* ALIVE_RES_API_S_VER_3 */
2559
2560struct iwm_alive_resp {
2561 uint16_t status;
2562 uint16_t flags;
2563 struct iwm_lmac_alive lmac_data[2];
2564 struct iwm_umac_alive umac_data;
2291} __packed; /* ALIVE_RES_API_S_VER_4 */
2565}__packed; /* ALIVE_RES_API_S_VER_4 */
2292
2566
2567
2568#define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)
2569#define IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1)
2570
2571#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc
2572#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0
2573#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1
2574#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2
2575#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3
2576
2577/**
2578 * struct iwm_soc_configuration_cmd - Set device stabilization latency
2579 *
2580 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE
2581 * flag, because the FW treats the whole value as an integer. In
2582 * VER_2, we can set the bits independently.
2583 * @latency: time for SOC to ensure stable power & XTAL
2584 */
2585struct iwm_soc_configuration_cmd {
2586 uint32_t flags;
2587 uint32_t latency;
2588} __packed; /*
2589 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above)
2590 * SOC_CONFIGURATION_CMD_S_VER_2
2591 */
2592
2593
2293/* Error response/notification */
2594/* Error response/notification */
2294enum {
2295 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2296 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2297 IWM_FW_ERR_SERVICE = 0x2,
2298 IWM_FW_ERR_ARC_MEMORY = 0x3,
2299 IWM_FW_ERR_ARC_CODE = 0x4,
2300 IWM_FW_ERR_WATCH_DOG = 0x5,
2301 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2302 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2303 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2304 IWM_FW_ERR_UNEXPECTED = 0xFE,
2305 IWM_FW_ERR_FATAL = 0xFF
2306};
2595#define IWM_FW_ERR_UNKNOWN_CMD 0x0
2596#define IWM_FW_ERR_INVALID_CMD_PARAM 0x1
2597#define IWM_FW_ERR_SERVICE 0x2
2598#define IWM_FW_ERR_ARC_MEMORY 0x3
2599#define IWM_FW_ERR_ARC_CODE 0x4
2600#define IWM_FW_ERR_WATCH_DOG 0x5
2601#define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10
2602#define IWM_FW_ERR_WEP_KEY_SIZE 0x11
2603#define IWM_FW_ERR_OBSOLETE_FUNC 0x12
2604#define IWM_FW_ERR_UNEXPECTED 0xFE
2605#define IWM_FW_ERR_FATAL 0xFF
2307
2308/**
2309 * struct iwm_error_resp - FW error indication
2310 * ( IWM_REPLY_ERROR = 0x2 )
2311 * @error_type: one of IWM_FW_ERR_*
2606
2607/**
2608 * struct iwm_error_resp - FW error indication
2609 * ( IWM_REPLY_ERROR = 0x2 )
2610 * @error_type: one of IWM_FW_ERR_*
2312 * @cmd_id: the command ID for which the error occurred
2611 * @cmd_id: the command ID for which the error occured
2313 * @bad_cmd_seq_num: sequence number of the erroneous command
2314 * @error_service: which service created the error, applicable only if
2315 * error_type = 2, otherwise 0
2316 * @timestamp: TSF in usecs.
2317 */
2318struct iwm_error_resp {
2319 uint32_t error_type;
2320 uint8_t cmd_id;
2321 uint8_t reserved1;
2322 uint16_t bad_cmd_seq_num;
2323 uint32_t error_service;
2324 uint64_t timestamp;
2325} __packed;
2326
2612 * @bad_cmd_seq_num: sequence number of the erroneous command
2613 * @error_service: which service created the error, applicable only if
2614 * error_type = 2, otherwise 0
2615 * @timestamp: TSF in usecs.
2616 */
2617struct iwm_error_resp {
2618 uint32_t error_type;
2619 uint8_t cmd_id;
2620 uint8_t reserved1;
2621 uint16_t bad_cmd_seq_num;
2622 uint32_t error_service;
2623 uint64_t timestamp;
2624} __packed;
2625
2626#define IWM_FW_CMD_VER_UNKNOWN 99
2327
2627
2628/**
2629 * struct iwm_fw_cmd_version - firmware command version entry
2630 * @cmd: command ID
2631 * @group: group ID
2632 * @cmd_ver: command version
2633 * @notif_ver: notification version
2634 */
2635struct iwm_fw_cmd_version {
2636 uint8_t cmd;
2637 uint8_t group;
2638 uint8_t cmd_ver;
2639 uint8_t notif_ver;
2640} __packed;
2641
2642
2328/* Common PHY, MAC and Bindings definitions */
2329
2330#define IWM_MAX_MACS_IN_BINDING (3)
2643/* Common PHY, MAC and Bindings definitions */
2644
2645#define IWM_MAX_MACS_IN_BINDING (3)
2331#define IWM_MAX_BINDINGS (4)
2646#define IWM_MAX_BINDINGS (4)
2332#define IWM_AUX_BINDING_INDEX (3)
2333#define IWM_MAX_PHYS (4)
2334
2335/* Used to extract ID and color from the context dword */
2647#define IWM_AUX_BINDING_INDEX (3)
2648#define IWM_MAX_PHYS (4)
2649
2650/* Used to extract ID and color from the context dword */
2336#define IWM_FW_CTXT_ID_POS (0)
2337#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2338#define IWM_FW_CTXT_COLOR_POS (8)
2339#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2340#define IWM_FW_CTXT_INVALID (0xffffffff)
2651#define IWM_FW_CTXT_ID_POS (0)
2652#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2653#define IWM_FW_CTXT_COLOR_POS (8)
2654#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2655#define IWM_FW_CTXT_INVALID (0xffffffff)
2341
2342#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2343 (_color << IWM_FW_CTXT_COLOR_POS))
2344
2345/* Possible actions on PHYs, MACs and Bindings */
2656
2657#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2658 (_color << IWM_FW_CTXT_COLOR_POS))
2659
2660/* Possible actions on PHYs, MACs and Bindings */
2346enum {
2347 IWM_FW_CTXT_ACTION_STUB = 0,
2348 IWM_FW_CTXT_ACTION_ADD,
2349 IWM_FW_CTXT_ACTION_MODIFY,
2350 IWM_FW_CTXT_ACTION_REMOVE,
2351 IWM_FW_CTXT_ACTION_NUM
2352}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2661#define IWM_FW_CTXT_ACTION_STUB 0
2662#define IWM_FW_CTXT_ACTION_ADD 1
2663#define IWM_FW_CTXT_ACTION_MODIFY 2
2664#define IWM_FW_CTXT_ACTION_REMOVE 3
2665#define IWM_FW_CTXT_ACTION_NUM 4
2666/* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2353
2354/* Time Events */
2355
2356/* Time Event types, according to MAC type */
2667
2668/* Time Events */
2669
2670/* Time Event types, according to MAC type */
2357enum iwm_time_event_type {
2358 /* BSS Station Events */
2359 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2360 IWM_TE_BSS_STA_ASSOC,
2361 IWM_TE_BSS_EAP_DHCP_PROT,
2362 IWM_TE_BSS_QUIET_PERIOD,
2363
2671
2364 /* P2P Device Events */
2365 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2366 IWM_TE_P2P_DEVICE_LISTEN,
2367 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2368 IWM_TE_P2P_DEVICE_FULL_SCAN,
2672/* BSS Station Events */
2673#define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0
2674#define IWM_TE_BSS_STA_ASSOC 1
2675#define IWM_TE_BSS_EAP_DHCP_PROT 2
2676#define IWM_TE_BSS_QUIET_PERIOD 3
2369
2677
2370 /* P2P Client Events */
2371 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2372 IWM_TE_P2P_CLIENT_ASSOC,
2373 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2678/* P2P Device Events */
2679#define IWM_TE_P2P_DEVICE_DISCOVERABLE 4
2680#define IWM_TE_P2P_DEVICE_LISTEN 5
2681#define IWM_TE_P2P_DEVICE_ACTION_SCAN 6
2682#define IWM_TE_P2P_DEVICE_FULL_SCAN 7
2374
2683
2375 /* P2P GO Events */
2376 IWM_TE_P2P_GO_ASSOC_PROT,
2377 IWM_TE_P2P_GO_REPETITIVE_NOA,
2378 IWM_TE_P2P_GO_CT_WINDOW,
2684/* P2P Client Events */
2685#define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8
2686#define IWM_TE_P2P_CLIENT_ASSOC 9
2687#define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10
2379
2688
2380 /* WiDi Sync Events */
2381 IWM_TE_WIDI_TX_SYNC,
2689/* P2P GO Events */
2690#define IWM_TE_P2P_GO_ASSOC_PROT 11
2691#define IWM_TE_P2P_GO_REPETITIVE_NOA 12
2692#define IWM_TE_P2P_GO_CT_WINDOW 13
2382
2693
2383 IWM_TE_MAX
2384}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2694/* WiDi Sync Events */
2695#define IWM_TE_WIDI_TX_SYNC 14
2385
2696
2697#define IWM_TE_MAX 15
2698/* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2386
2387
2699
2700
2701
2388/* Time event - defines for command API v1 */
2389
2390/*
2391 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2392 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2393 * the first fragment is scheduled.
2394 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2395 * the first 2 fragments are scheduled.
2396 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2397 * number of fragments are valid.
2398 *
2399 * Other than the constant defined above, specifying a fragmentation value 'x'
2400 * means that the event can be fragmented but only the first 'x' will be
2401 * scheduled.
2402 */
2702/* Time event - defines for command API v1 */
2703
2704/*
2705 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2706 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2707 * the first fragment is scheduled.
2708 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2709 * the first 2 fragments are scheduled.
2710 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2711 * number of fragments are valid.
2712 *
2713 * Other than the constant defined above, specifying a fragmentation value 'x'
2714 * means that the event can be fragmented but only the first 'x' will be
2715 * scheduled.
2716 */
2403enum {
2404 IWM_TE_V1_FRAG_NONE = 0,
2405 IWM_TE_V1_FRAG_SINGLE = 1,
2406 IWM_TE_V1_FRAG_DUAL = 2,
2407 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2408};
2717#define IWM_TE_V1_FRAG_NONE 0
2718#define IWM_TE_V1_FRAG_SINGLE 1
2719#define IWM_TE_V1_FRAG_DUAL 2
2720#define IWM_TE_V1_FRAG_ENDLESS 0xffffffff
2409
2410/* If a Time Event can be fragmented, this is the max number of fragments */
2411#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2412/* Repeat the time event endlessly (until removed) */
2413#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2414/* If a Time Event has bounded repetitions, this is the maximal value */
2415#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2416
2417/* Time Event dependencies: none, on another TE, or in a specific time */
2721
2722/* If a Time Event can be fragmented, this is the max number of fragments */
2723#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2724/* Repeat the time event endlessly (until removed) */
2725#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2726/* If a Time Event has bounded repetitions, this is the maximal value */
2727#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2728
2729/* Time Event dependencies: none, on another TE, or in a specific time */
2418enum {
2419 IWM_TE_V1_INDEPENDENT = 0,
2420 IWM_TE_V1_DEP_OTHER = (1 << 0),
2421 IWM_TE_V1_DEP_TSF = (1 << 1),
2422 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2423}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2730#define IWM_TE_V1_INDEPENDENT 0
2731#define IWM_TE_V1_DEP_OTHER (1 << 0)
2732#define IWM_TE_V1_DEP_TSF (1 << 1)
2733#define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2)
2734/* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2424
2425/*
2426 * @IWM_TE_V1_NOTIF_NONE: no notifications
2427 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2428 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2429 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2430 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2431 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2432 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2433 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2434 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2435 *
2436 * Supported Time event notifications configuration.
2437 * A notification (both event and fragment) includes a status indicating weather
2438 * the FW was able to schedule the event or not. For fragment start/end
2439 * notification the status is always success. There is no start/end fragment
2440 * notification for monolithic events.
2441 */
2735
2736/*
2737 * @IWM_TE_V1_NOTIF_NONE: no notifications
2738 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2739 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2740 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2741 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2742 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2743 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2744 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2745 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2746 *
2747 * Supported Time event notifications configuration.
2748 * A notification (both event and fragment) includes a status indicating weather
2749 * the FW was able to schedule the event or not. For fragment start/end
2750 * notification the status is always success. There is no start/end fragment
2751 * notification for monolithic events.
2752 */
2442enum {
2443 IWM_TE_V1_NOTIF_NONE = 0,
2444 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2445 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2446 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2447 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2448 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2449 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2450 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2451 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2452 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2453}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2753#define IWM_TE_V1_NOTIF_NONE 0
2754#define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0)
2755#define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1)
2756#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2)
2757#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3)
2758#define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4)
2759#define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5)
2760#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6)
2761#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7)
2762/* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2454
2763
2764
2455/* Time event - defines for command API */
2456
2765/* Time event - defines for command API */
2766
2767/**
2768 * DOC: Time Events - what is it?
2769 *
2770 * Time Events are a fw feature that allows the driver to control the presence
2771 * of the device on the channel. Since the fw supports multiple channels
2772 * concurrently, the fw may choose to jump to another channel at any time.
2773 * In order to make sure that the fw is on a specific channel at a certain time
2774 * and for a certain duration, the driver needs to issue a time event.
2775 *
2776 * The simplest example is for BSS association. The driver issues a time event,
2777 * waits for it to start, and only then tells mac80211 that we can start the
2778 * association. This way, we make sure that the association will be done
2779 * smoothly and won't be interrupted by channel switch decided within the fw.
2780 */
2781
2782 /**
2783 * DOC: The flow against the fw
2784 *
2785 * When the driver needs to make sure we are in a certain channel, at a certain
2786 * time and for a certain duration, it sends a Time Event. The flow against the
2787 * fw goes like this:
2788 * 1) Driver sends a TIME_EVENT_CMD to the fw
2789 * 2) Driver gets the response for that command. This response contains the
2790 * Unique ID (UID) of the event.
2791 * 3) The fw sends notification when the event starts.
2792 *
2793 * Of course the API provides various options that allow to cover parameters
2794 * of the flow.
2795 * What is the duration of the event?
2796 * What is the start time of the event?
2797 * Is there an end-time for the event?
2798 * How much can the event be delayed?
2799 * Can the event be split?
2800 * If yes what is the maximal number of chunks?
2801 * etc...
2802 */
2803
2457/*
2458 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2459 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2460 * the first fragment is scheduled.
2461 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2462 * the first 2 fragments are scheduled.
2463 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2464 * number of fragments are valid.
2465 *
2466 * Other than the constant defined above, specifying a fragmentation value 'x'
2467 * means that the event can be fragmented but only the first 'x' will be
2468 * scheduled.
2469 */
2804/*
2805 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2806 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2807 * the first fragment is scheduled.
2808 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2809 * the first 2 fragments are scheduled.
2810 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2811 * number of fragments are valid.
2812 *
2813 * Other than the constant defined above, specifying a fragmentation value 'x'
2814 * means that the event can be fragmented but only the first 'x' will be
2815 * scheduled.
2816 */
2470enum {
2471 IWM_TE_V2_FRAG_NONE = 0,
2472 IWM_TE_V2_FRAG_SINGLE = 1,
2473 IWM_TE_V2_FRAG_DUAL = 2,
2474 IWM_TE_V2_FRAG_MAX = 0xfe,
2475 IWM_TE_V2_FRAG_ENDLESS = 0xff
2476};
2817#define IWM_TE_V2_FRAG_NONE 0
2818#define IWM_TE_V2_FRAG_SINGLE 1
2819#define IWM_TE_V2_FRAG_DUAL 2
2820#define IWM_TE_V2_FRAG_MAX 0xfe
2821#define IWM_TE_V2_FRAG_ENDLESS 0xff
2477
2478/* Repeat the time event endlessly (until removed) */
2479#define IWM_TE_V2_REPEAT_ENDLESS 0xff
2480/* If a Time Event has bounded repetitions, this is the maximal value */
2481#define IWM_TE_V2_REPEAT_MAX 0xfe
2482
2483#define IWM_TE_V2_PLACEMENT_POS 12
2484#define IWM_TE_V2_ABSENCE_POS 15

--- 13 unchanged lines hidden (view full) ---

2498 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2499 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2500 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2501 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2502 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2503 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2504 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2505 */
2822
2823/* Repeat the time event endlessly (until removed) */
2824#define IWM_TE_V2_REPEAT_ENDLESS 0xff
2825/* If a Time Event has bounded repetitions, this is the maximal value */
2826#define IWM_TE_V2_REPEAT_MAX 0xfe
2827
2828#define IWM_TE_V2_PLACEMENT_POS 12
2829#define IWM_TE_V2_ABSENCE_POS 15

--- 13 unchanged lines hidden (view full) ---

2843 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2844 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2845 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2846 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2847 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2848 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2849 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2850 */
2506enum {
2507 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2851#define IWM_TE_V2_DEFAULT_POLICY 0x0
2508
2852
2509 /* notifications (event start/stop, fragment start/stop) */
2510 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2511 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2512 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2513 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2853/* notifications (event start/stop, fragment start/stop) */
2854#define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)
2855#define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)
2856#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)
2857#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)
2514
2858
2515 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2516 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2517 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2518 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2859#define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)
2860#define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)
2861#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)
2862#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)
2863#define IWM_T2_V2_START_IMMEDIATELY (1 << 11)
2519
2864
2520 IWM_TE_V2_NOTIF_MSK = 0xff,
2865#define IWM_TE_V2_NOTIF_MSK 0xff
2521
2866
2522 /* placement characteristics */
2523 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2524 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2525 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2867/* placement characteristics */
2868#define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS)
2869#define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1))
2870#define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2))
2526
2871
2527 /* are we present or absent during the Time Event. */
2528 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2529};
2872/* are we present or absent during the Time Event. */
2873#define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS)
2530
2531/**
2532 * struct iwm_time_event_cmd_api - configuring Time Events
2533 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2534 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2535 * ( IWM_TIME_EVENT_CMD = 0x29 )
2536 * @id_and_color: ID and color of the relevant MAC
2537 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*

--- 62 unchanged lines hidden (view full) ---

2600 uint32_t action;
2601 uint32_t status;
2602} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2603
2604
2605/* Bindings and Time Quota */
2606
2607/**
2874
2875/**
2876 * struct iwm_time_event_cmd_api - configuring Time Events
2877 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2878 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2879 * ( IWM_TIME_EVENT_CMD = 0x29 )
2880 * @id_and_color: ID and color of the relevant MAC
2881 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*

--- 62 unchanged lines hidden (view full) ---

2944 uint32_t action;
2945 uint32_t status;
2946} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2947
2948
2949/* Bindings and Time Quota */
2950
2951/**
2952 * struct iwm_binding_cmd_v1 - configuring bindings
2953 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2954 * @id_and_color: ID and color of the relevant Binding
2955 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2956 * @macs: array of MAC id and colors which belong to the binding
2957 * @phy: PHY id and color which belongs to the binding
2958 * @lmac_id: the lmac id the binding belongs to
2959 */
2960struct iwm_binding_cmd_v1 {
2961 /* COMMON_INDEX_HDR_API_S_VER_1 */
2962 uint32_t id_and_color;
2963 uint32_t action;
2964 /* IWM_BINDING_DATA_API_S_VER_1 */
2965 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2966 uint32_t phy;
2967} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2968
2969/**
2608 * struct iwm_binding_cmd - configuring bindings
2609 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2610 * @id_and_color: ID and color of the relevant Binding
2611 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2612 * @macs: array of MAC id and colors which belong to the binding
2613 * @phy: PHY id and color which belongs to the binding
2970 * struct iwm_binding_cmd - configuring bindings
2971 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2972 * @id_and_color: ID and color of the relevant Binding
2973 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2974 * @macs: array of MAC id and colors which belong to the binding
2975 * @phy: PHY id and color which belongs to the binding
2976 * @lmac_id: the lmac id the binding belongs to
2614 */
2615struct iwm_binding_cmd {
2616 /* COMMON_INDEX_HDR_API_S_VER_1 */
2617 uint32_t id_and_color;
2618 uint32_t action;
2619 /* IWM_BINDING_DATA_API_S_VER_1 */
2620 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2621 uint32_t phy;
2977 */
2978struct iwm_binding_cmd {
2979 /* COMMON_INDEX_HDR_API_S_VER_1 */
2980 uint32_t id_and_color;
2981 uint32_t action;
2982 /* IWM_BINDING_DATA_API_S_VER_1 */
2983 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2984 uint32_t phy;
2622} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2985 uint32_t lmac_id;
2986} __packed; /* IWM_BINDING_CMD_API_S_VER_2 */
2623
2987
2988#define IWM_LMAC_24G_INDEX 0
2989#define IWM_LMAC_5G_INDEX 1
2990
2624/* The maximal number of fragments in the FW's schedule session */
2625#define IWM_MAX_QUOTA 128
2626
2627/**
2628 * struct iwm_time_quota_data - configuration of time quota per binding
2629 * @id_and_color: ID and color of the relevant Binding
2630 * @quota: absolute time quota in TU. The scheduler will try to divide the
2631 * remainig quota (after Time Events) according to this quota.
2632 * @max_duration: max uninterrupted context duration in TU
2633 */
2991/* The maximal number of fragments in the FW's schedule session */
2992#define IWM_MAX_QUOTA 128
2993
2994/**
2995 * struct iwm_time_quota_data - configuration of time quota per binding
2996 * @id_and_color: ID and color of the relevant Binding
2997 * @quota: absolute time quota in TU. The scheduler will try to divide the
2998 * remainig quota (after Time Events) according to this quota.
2999 * @max_duration: max uninterrupted context duration in TU
3000 */
2634struct iwm_time_quota_data {
3001struct iwm_time_quota_data_v1 {
2635 uint32_t id_and_color;
2636 uint32_t quota;
2637 uint32_t max_duration;
2638} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2639
2640/**
2641 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2642 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2643 * @quotas: allocations per binding
2644 */
3002 uint32_t id_and_color;
3003 uint32_t quota;
3004 uint32_t max_duration;
3005} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
3006
3007/**
3008 * struct iwm_time_quota_cmd - configuration of time quota between bindings
3009 * ( IWM_TIME_QUOTA_CMD = 0x2c )
3010 * @quotas: allocations per binding
3011 */
3012struct iwm_time_quota_cmd_v1 {
3013 struct iwm_time_quota_data_v1 quotas[IWM_MAX_BINDINGS];
3014} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
3015
3016#define IWM_QUOTA_LOW_LATENCY_NONE 0
3017#define IWM_QUOTA_LOW_LATENCY_TX (1 << 0)
3018#define IWM_QUOTA_LOW_LATENCY_RX (1 << 1)
3019
3020/**
3021 * struct iwm_time_quota_data - configuration of time quota per binding
3022 * @id_and_color: ID and color of the relevant Binding.
3023 * @quota: absolute time quota in TU. The scheduler will try to divide the
3024 * remainig quota (after Time Events) according to this quota.
3025 * @max_duration: max uninterrupted context duration in TU
3026 * @low_latency: low latency status IWM_QUOTA_LOW_LATENCY_*
3027 */
3028struct iwm_time_quota_data {
3029 uint32_t id_and_color;
3030 uint32_t quota;
3031 uint32_t max_duration;
3032 uint32_t low_latency;
3033}; /* TIME_QUOTA_DATA_API_S_VER_2 */
3034
3035/**
3036 * struct iwm_time_quota_cmd - configuration of time quota between bindings
3037 * ( TIME_QUOTA_CMD = 0x2c )
3038 * Note: on non-CDB the fourth one is the auxilary mac and is essentially zero.
3039 * On CDB the fourth one is a regular binding.
3040 *
3041 * @quotas: allocations per binding
3042 */
2645struct iwm_time_quota_cmd {
2646 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
3043struct iwm_time_quota_cmd {
3044 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2647} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
3045} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_2 */
2648
2649
2650/* PHY context */
2651
2652/* Supported bands */
2653#define IWM_PHY_BAND_5 (0)
2654#define IWM_PHY_BAND_24 (1)
2655

--- 25 unchanged lines hidden (view full) ---

2681#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2682
2683/*
2684 * @band: IWM_PHY_BAND_*
2685 * @channel: channel number
2686 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2687 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2688 */
3046
3047
3048/* PHY context */
3049
3050/* Supported bands */
3051#define IWM_PHY_BAND_5 (0)
3052#define IWM_PHY_BAND_24 (1)
3053

--- 25 unchanged lines hidden (view full) ---

3079#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
3080
3081/*
3082 * @band: IWM_PHY_BAND_*
3083 * @channel: channel number
3084 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3085 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3086 */
2689struct iwm_fw_channel_info {
3087struct iwm_fw_channel_info_v1 {
2690 uint8_t band;
2691 uint8_t channel;
2692 uint8_t width;
2693 uint8_t ctrl_pos;
3088 uint8_t band;
3089 uint8_t channel;
3090 uint8_t width;
3091 uint8_t ctrl_pos;
2694} __packed;
3092} __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
2695
3093
3094/*
3095 * struct iwm_fw_channel_info - channel information
3096 *
3097 * @channel: channel number
3098 * @band: PHY_BAND_*
3099 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3100 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3101 * @reserved: for future use and alignment
3102 */
3103struct iwm_fw_channel_info {
3104 uint32_t channel;
3105 uint8_t band;
3106 uint8_t width;
3107 uint8_t ctrl_pos;
3108 uint8_t reserved;
3109} __packed; /* CHANNEL_CONFIG_API_S_VER_2 */
3110
2696#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2697#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2698 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2699#define IWM_PHY_RX_CHAIN_VALID_POS (1)
2700#define IWM_PHY_RX_CHAIN_VALID_MSK \
2701 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2702#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2703#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \

--- 24 unchanged lines hidden (view full) ---

2728 * other value means apply new params after X usecs
2729 * @tx_param_color: ???
2730 * @channel_info:
2731 * @txchain_info: ???
2732 * @rxchain_info: ???
2733 * @acquisition_data: ???
2734 * @dsp_cfg_flags: set to 0
2735 */
3111#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
3112#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
3113 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
3114#define IWM_PHY_RX_CHAIN_VALID_POS (1)
3115#define IWM_PHY_RX_CHAIN_VALID_MSK \
3116 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
3117#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
3118#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \

--- 24 unchanged lines hidden (view full) ---

3143 * other value means apply new params after X usecs
3144 * @tx_param_color: ???
3145 * @channel_info:
3146 * @txchain_info: ???
3147 * @rxchain_info: ???
3148 * @acquisition_data: ???
3149 * @dsp_cfg_flags: set to 0
3150 */
2736struct iwm_phy_context_cmd {
3151/*
3152 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased
3153 * the size of fw_channel_info from v1 to v2.
3154 * To keep things simple we define two versions of this struct, and both
3155 * are labled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark
3156 * magic with pointers to struct members instead.)
3157 */
3158/* This version must be used if IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */
3159struct iwm_phy_context_cmd_uhb {
2737 /* COMMON_INDEX_HDR_API_S_VER_1 */
2738 uint32_t id_and_color;
2739 uint32_t action;
2740 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2741 uint32_t apply_time;
2742 uint32_t tx_param_color;
2743 struct iwm_fw_channel_info ci;
2744 uint32_t txchain_info;
2745 uint32_t rxchain_info;
2746 uint32_t acquisition_data;
2747 uint32_t dsp_cfg_flags;
2748} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
3160 /* COMMON_INDEX_HDR_API_S_VER_1 */
3161 uint32_t id_and_color;
3162 uint32_t action;
3163 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
3164 uint32_t apply_time;
3165 uint32_t tx_param_color;
3166 struct iwm_fw_channel_info ci;
3167 uint32_t txchain_info;
3168 uint32_t rxchain_info;
3169 uint32_t acquisition_data;
3170 uint32_t dsp_cfg_flags;
3171} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
3172/* This version must be used otherwise: */
3173struct iwm_phy_context_cmd {
3174 /* COMMON_INDEX_HDR_API_S_VER_1 */
3175 uint32_t id_and_color;
3176 uint32_t action;
3177 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
3178 uint32_t apply_time;
3179 uint32_t tx_param_color;
3180 struct iwm_fw_channel_info_v1 ci;
3181 uint32_t txchain_info;
3182 uint32_t rxchain_info;
3183 uint32_t acquisition_data;
3184 uint32_t dsp_cfg_flags;
3185} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2749
2750#define IWM_RX_INFO_PHY_CNT 8
2751#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2752#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2753#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2754#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2755#define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2756#define IWM_RX_INFO_ENERGY_ANT_B_POS 8

--- 45 unchanged lines hidden (view full) ---

2802 uint8_t reserved1;
2803 uint32_t system_timestamp;
2804 uint64_t timestamp;
2805 uint32_t beacon_time_stamp;
2806 uint16_t phy_flags;
2807#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2808 uint16_t channel;
2809 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
3186
3187#define IWM_RX_INFO_PHY_CNT 8
3188#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
3189#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
3190#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
3191#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
3192#define IWM_RX_INFO_ENERGY_ANT_A_POS 0
3193#define IWM_RX_INFO_ENERGY_ANT_B_POS 8

--- 45 unchanged lines hidden (view full) ---

3239 uint8_t reserved1;
3240 uint32_t system_timestamp;
3241 uint64_t timestamp;
3242 uint32_t beacon_time_stamp;
3243 uint16_t phy_flags;
3244#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
3245 uint16_t channel;
3246 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
3247#if 0
3248 /* OpenBSD update; will need to convert code to use this field */
3249 uint32_t rate_n_flags;
3250#else
2810 uint8_t rate;
2811 uint8_t rflags;
2812 uint16_t xrflags;
3251 uint8_t rate;
3252 uint8_t rflags;
3253 uint16_t xrflags;
3254#endif
2813 uint32_t byte_count;
2814 uint16_t mac_active_msk;
2815 uint16_t frame_time;
2816} __packed;
2817
2818struct iwm_rx_mpdu_res_start {
2819 uint16_t byte_count;
2820 uint16_t reserved;
2821} __packed;
2822
2823/**
3255 uint32_t byte_count;
3256 uint16_t mac_active_msk;
3257 uint16_t frame_time;
3258} __packed;
3259
3260struct iwm_rx_mpdu_res_start {
3261 uint16_t byte_count;
3262 uint16_t reserved;
3263} __packed;
3264
3265/**
2824 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
3266 * Values to parse %iwm_rx_phy_info phy_flags
2825 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2826 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2827 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2828 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2829 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2830 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2831 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2832 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2833 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2834 */
3267 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
3268 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
3269 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
3270 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
3271 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
3272 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
3273 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
3274 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
3275 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
3276 */
2835enum iwm_rx_phy_flags {
2836 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2837 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2838 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2839 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2840 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2841 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2842 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2843 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2844 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2845 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2846};
3277#define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)
3278#define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)
3279#define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)
3280#define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)
3281#define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)
3282#define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4
3283#define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7)
3284#define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)
3285#define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)
3286#define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)
2847
2848/**
3287
3288/**
2849 * enum iwm_rx_status - written by fw for each Rx packet
3289 * Values written by fw for each Rx packet
2850 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2851 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2852 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2853 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2854 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2855 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2856 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2857 * in the driver.

--- 14 unchanged lines hidden (view full) ---

2872 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2873 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2874 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2875 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2876 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2877 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2878 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2879 */
3290 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
3291 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
3292 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
3293 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
3294 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
3295 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
3296 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
3297 * in the driver.

--- 14 unchanged lines hidden (view full) ---

3312 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
3313 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
3314 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
3315 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
3316 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
3317 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
3318 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
3319 */
2880enum iwm_rx_status {
2881 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2882 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2883 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2884 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2885 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2886 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2887 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2888 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2889 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2890 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2891 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2892 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2893 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2894 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2895 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2896 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2897 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2898 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2899 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2900 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2901 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2902 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2903 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2904 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2905 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2906 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2907 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2908};
3320#define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)
3321#define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)
3322#define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)
3323#define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)
3324#define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)
3325#define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)
3326#define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)
3327#define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
3328#define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)
3329#define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)
3330#define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)
3331#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)
3332#define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)
3333#define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)
3334#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)
3335#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)
3336#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)
3337#define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)
3338#define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)
3339#define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)
3340#define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)
3341#define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)
3342#define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)
3343#define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)
3344#define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)
3345#define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)
3346#define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)
2909
3347
2910enum iwm_rx_mpdu_mac_flags1 {
2911 IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK = 0x03,
2912 IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0,
2913 IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3,
2914};
3348#define IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03
3349#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0
3350#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3
2915
3351
2916enum iwm_rx_mpdu_mac_flags2 {
2917 IWM_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f,
2918 IWM_RX_MPDU_MFLG2_PAD = 0x20,
2919 IWM_RX_MPDU_MFLG2_AMSDU = 0x40,
2920};
3352#define IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f
3353#define IWM_RX_MPDU_MFLG2_PAD 0x20
3354#define IWM_RX_MPDU_MFLG2_AMSDU 0x40
2921
3355
2922enum iwm_rx_mpdu_phy_info {
2923 IWM_RX_MPDU_PHY_AMPDU = (1 << 5),
2924 IWM_RX_MPDU_PHY_AMPDU_TOGGLE = (1 << 6),
2925 IWM_RX_MPDU_PHY_SHORT_PREAMBLE = (1 << 7),
2926 IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY = (1 << 7),
2927 IWM_RX_MPDU_PHY_TSF_OVERLOAD = (1 << 8),
2928};
3356#define IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f
3357#define IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80
2929
3358
3359#define IWM_RX_MPDU_PHY_AMPDU (1 << 5)
3360#define IWM_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6)
3361#define IWM_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7)
3362#define IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7)
3363#define IWM_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8)
3364
2930struct iwm_rx_mpdu_desc_v1 {
2931 union {
2932 uint32_t rss_hash;
2933 uint32_t phy_data2;
2934 };
2935 union {
2936 uint32_t filter_match;
2937 uint32_t phy_data3;

--- 8 unchanged lines hidden (view full) ---

2946 uint64_t tsf_on_air_rise;
2947 struct {
2948 uint32_t phy_data0;
2949 uint32_t phy_data1;
2950 };
2951 };
2952} __packed;
2953
3365struct iwm_rx_mpdu_desc_v1 {
3366 union {
3367 uint32_t rss_hash;
3368 uint32_t phy_data2;
3369 };
3370 union {
3371 uint32_t filter_match;
3372 uint32_t phy_data3;

--- 8 unchanged lines hidden (view full) ---

3381 uint64_t tsf_on_air_rise;
3382 struct {
3383 uint32_t phy_data0;
3384 uint32_t phy_data1;
3385 };
3386 };
3387} __packed;
3388
3389#define IWM_RX_REORDER_DATA_INVALID_BAID 0x7f
3390
3391#define IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff
3392#define IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000
3393#define IWM_RX_MPDU_REORDER_SN_SHIFT 12
3394#define IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000
3395#define IWM_RX_MPDU_REORDER_BAID_SHIFT 24
3396#define IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000
3397
2954struct iwm_rx_mpdu_desc {
2955 uint16_t mpdu_len;
2956 uint8_t mac_flags1;
2957 uint8_t mac_flags2;
2958 uint8_t amsdu_info;
2959 uint16_t phy_info;
2960 uint8_t mac_phy_idx;
2961 uint16_t raw_csum;

--- 16 unchanged lines hidden (view full) ---

2978 * @radio_dash:
2979 */
2980struct iwm_radio_version_notif {
2981 uint32_t radio_flavor;
2982 uint32_t radio_step;
2983 uint32_t radio_dash;
2984} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2985
3398struct iwm_rx_mpdu_desc {
3399 uint16_t mpdu_len;
3400 uint8_t mac_flags1;
3401 uint8_t mac_flags2;
3402 uint8_t amsdu_info;
3403 uint16_t phy_info;
3404 uint8_t mac_phy_idx;
3405 uint16_t raw_csum;

--- 16 unchanged lines hidden (view full) ---

3422 * @radio_dash:
3423 */
3424struct iwm_radio_version_notif {
3425 uint32_t radio_flavor;
3426 uint32_t radio_step;
3427 uint32_t radio_dash;
3428} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
3429
2986enum iwm_card_state_flags {
2987 IWM_CARD_ENABLED = 0x00,
2988 IWM_HW_CARD_DISABLED = 0x01,
2989 IWM_SW_CARD_DISABLED = 0x02,
2990 IWM_CT_KILL_CARD_DISABLED = 0x04,
2991 IWM_HALT_CARD_DISABLED = 0x08,
2992 IWM_CARD_DISABLED_MSK = 0x0f,
2993 IWM_CARD_IS_RX_ON = 0x10,
2994};
3430#define IWM_CARD_ENABLED 0x00
3431#define IWM_HW_CARD_DISABLED 0x01
3432#define IWM_SW_CARD_DISABLED 0x02
3433#define IWM_CT_KILL_CARD_DISABLED 0x04
3434#define IWM_HALT_CARD_DISABLED 0x08
3435#define IWM_CARD_DISABLED_MSK 0x0f
3436#define IWM_CARD_IS_RX_ON 0x10
2995
2996/**
2997 * struct iwm_radio_version_notif - information on the radio version
2998 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2999 * @flags: %iwm_card_state_flags
3000 */
3001struct iwm_card_state_notif {
3002 uint32_t flags;

--- 66 unchanged lines hidden (view full) ---

3069 uint8_t port_id;
3070 uint8_t count;
3071 uint8_t pass_all;
3072 uint8_t bssid[6];
3073 uint8_t reserved[2];
3074 uint8_t addr_list[0];
3075} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
3076
3437
3438/**
3439 * struct iwm_radio_version_notif - information on the radio version
3440 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
3441 * @flags: %iwm_card_state_flags
3442 */
3443struct iwm_card_state_notif {
3444 uint32_t flags;

--- 66 unchanged lines hidden (view full) ---

3511 uint8_t port_id;
3512 uint8_t count;
3513 uint8_t pass_all;
3514 uint8_t bssid[6];
3515 uint8_t reserved[2];
3516 uint8_t addr_list[0];
3517} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
3518
3077/*
3078 * The first MAC indices (starting from 0)
3079 * are available to the driver, AUX follows
3080 */
3081#define IWM_MAC_INDEX_AUX 4
3082#define IWM_MAC_INDEX_MIN_DRIVER 0
3083#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3084#define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1)
3085
3086/***********************************
3087 * Statistics API
3088 ***********************************/
3089struct iwm_statistics_dbg {
3090 uint32_t burst_check;
3091 uint32_t burst_count;
3092 uint32_t wait_for_silence_timeout_cnt;
3093 uint32_t reserved[3];
3094} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
3095
3096struct iwm_statistics_div {
3097 uint32_t tx_on_a;
3098 uint32_t tx_on_b;
3099 uint32_t exec_time;
3100 uint32_t probe_time;
3101 uint32_t rssi_ant;
3102 uint32_t reserved2;
3103} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
3104
3519struct iwm_statistics_dbg {
3520 uint32_t burst_check;
3521 uint32_t burst_count;
3522 uint32_t wait_for_silence_timeout_cnt;
3523 uint32_t reserved[3];
3524} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
3525
3526struct iwm_statistics_div {
3527 uint32_t tx_on_a;
3528 uint32_t tx_on_b;
3529 uint32_t exec_time;
3530 uint32_t probe_time;
3531 uint32_t rssi_ant;
3532 uint32_t reserved2;
3533} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
3534
3535struct iwm_statistics_general_common {
3536 uint32_t temperature; /* radio temperature */
3537 uint32_t temperature_m; /* radio voltage */
3538 struct iwm_statistics_dbg dbg;
3539 uint32_t sleep_time;
3540 uint32_t slots_out;
3541 uint32_t slots_idle;
3542 uint32_t ttl_timestamp;
3543 struct iwm_statistics_div div;
3544 uint32_t rx_enable_counter;
3545 /*
3546 * num_of_sos_states:
3547 * count the number of times we have to re-tune
3548 * in order to get out of bad PHY status
3549 */
3550 uint32_t num_of_sos_states;
3551} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3552
3105struct iwm_statistics_rx_non_phy {
3106 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3107 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3108 uint32_t non_bssid_frames; /* number of frames with BSSID that
3109 * doesn't belong to the STA BSSID */
3110 uint32_t filtered_frames; /* count frames that were dumped in the
3111 * filtering process */
3112 uint32_t non_channel_beacons; /* beacons with our bss id but not on

--- 54 unchanged lines hidden (view full) ---

3167 uint32_t crc32_err;
3168 uint32_t mh_format_err;
3169 uint32_t agg_crc32_good;
3170 uint32_t agg_mpdu_cnt;
3171 uint32_t agg_cnt;
3172 uint32_t unsupport_mcs;
3173} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3174
3553struct iwm_statistics_rx_non_phy {
3554 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3555 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3556 uint32_t non_bssid_frames; /* number of frames with BSSID that
3557 * doesn't belong to the STA BSSID */
3558 uint32_t filtered_frames; /* count frames that were dumped in the
3559 * filtering process */
3560 uint32_t non_channel_beacons; /* beacons with our bss id but not on

--- 54 unchanged lines hidden (view full) ---

3615 uint32_t crc32_err;
3616 uint32_t mh_format_err;
3617 uint32_t agg_crc32_good;
3618 uint32_t agg_mpdu_cnt;
3619 uint32_t agg_cnt;
3620 uint32_t unsupport_mcs;
3621} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3622
3175struct iwm_statistics_tx_non_phy {
3176 uint32_t preamble_cnt;
3177 uint32_t rx_detected_cnt;
3178 uint32_t bt_prio_defer_cnt;
3179 uint32_t bt_prio_kill_cnt;
3180 uint32_t few_bytes_cnt;
3181 uint32_t cts_timeout;
3182 uint32_t ack_timeout;
3183 uint32_t expected_ack_cnt;
3184 uint32_t actual_ack_cnt;
3185 uint32_t dump_msdu_cnt;
3186 uint32_t burst_abort_next_frame_mismatch_cnt;
3187 uint32_t burst_abort_missing_next_frame_cnt;
3188 uint32_t cts_timeout_collision;
3189 uint32_t ack_or_ba_timeout_collision;
3190} __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */
3191
3192#define IWM_MAX_CHAINS 3
3193
3194struct iwm_statistics_tx_non_phy_agg {
3195 uint32_t ba_timeout;
3196 uint32_t ba_reschedule_frames;
3197 uint32_t scd_query_agg_frame_cnt;
3198 uint32_t scd_query_no_agg;
3199 uint32_t scd_query_agg;

--- 14 unchanged lines hidden (view full) ---

3214 uint32_t ext_cca_narrow_ch160[4];
3215 uint32_t last_tx_ch_width_indx;
3216 uint32_t rx_detected_per_ch_width[4];
3217 uint32_t success_per_ch_width[4];
3218 uint32_t fail_per_ch_width[4];
3219}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3220
3221struct iwm_statistics_tx {
3623#define IWM_MAX_CHAINS 3
3624
3625struct iwm_statistics_tx_non_phy_agg {
3626 uint32_t ba_timeout;
3627 uint32_t ba_reschedule_frames;
3628 uint32_t scd_query_agg_frame_cnt;
3629 uint32_t scd_query_no_agg;
3630 uint32_t scd_query_agg;

--- 14 unchanged lines hidden (view full) ---

3645 uint32_t ext_cca_narrow_ch160[4];
3646 uint32_t last_tx_ch_width_indx;
3647 uint32_t rx_detected_per_ch_width[4];
3648 uint32_t success_per_ch_width[4];
3649 uint32_t fail_per_ch_width[4];
3650}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3651
3652struct iwm_statistics_tx {
3222 struct iwm_statistics_tx_non_phy general;
3653 uint32_t preamble_cnt;
3654 uint32_t rx_detected_cnt;
3655 uint32_t bt_prio_defer_cnt;
3656 uint32_t bt_prio_kill_cnt;
3657 uint32_t few_bytes_cnt;
3658 uint32_t cts_timeout;
3659 uint32_t ack_timeout;
3660 uint32_t expected_ack_cnt;
3661 uint32_t actual_ack_cnt;
3662 uint32_t dump_msdu_cnt;
3663 uint32_t burst_abort_next_frame_mismatch_cnt;
3664 uint32_t burst_abort_missing_next_frame_cnt;
3665 uint32_t cts_timeout_collision;
3666 uint32_t ack_or_ba_timeout_collision;
3223 struct iwm_statistics_tx_non_phy_agg agg;
3224 struct iwm_statistics_tx_channel_width channel_width;
3225} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3226
3227
3228struct iwm_statistics_bt_activity {
3229 uint32_t hi_priority_tx_req_cnt;
3230 uint32_t hi_priority_tx_denied_cnt;
3231 uint32_t lo_priority_tx_req_cnt;
3232 uint32_t lo_priority_tx_denied_cnt;
3233 uint32_t hi_priority_rx_req_cnt;
3234 uint32_t hi_priority_rx_denied_cnt;
3235 uint32_t lo_priority_rx_req_cnt;
3236 uint32_t lo_priority_rx_denied_cnt;
3237} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3238
3667 struct iwm_statistics_tx_non_phy_agg agg;
3668 struct iwm_statistics_tx_channel_width channel_width;
3669} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3670
3671
3672struct iwm_statistics_bt_activity {
3673 uint32_t hi_priority_tx_req_cnt;
3674 uint32_t hi_priority_tx_denied_cnt;
3675 uint32_t lo_priority_tx_req_cnt;
3676 uint32_t lo_priority_tx_denied_cnt;
3677 uint32_t hi_priority_rx_req_cnt;
3678 uint32_t hi_priority_rx_denied_cnt;
3679 uint32_t lo_priority_rx_req_cnt;
3680 uint32_t lo_priority_rx_denied_cnt;
3681} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3682
3239struct iwm_statistics_general_v8 {
3240 uint32_t radio_temperature;
3241 uint32_t radio_voltage;
3242 struct iwm_statistics_dbg dbg;
3243 uint32_t sleep_time;
3244 uint32_t slots_out;
3245 uint32_t slots_idle;
3246 uint32_t ttl_timestamp;
3247 struct iwm_statistics_div slow_div;
3248 uint32_t rx_enable_counter;
3249 /*
3250 * num_of_sos_states:
3251 * count the number of times we have to re-tune
3252 * in order to get out of bad PHY status
3253 */
3254 uint32_t num_of_sos_states;
3683struct iwm_statistics_general {
3684 struct iwm_statistics_general_common common;
3255 uint32_t beacon_filtered;
3256 uint32_t missed_beacons;
3685 uint32_t beacon_filtered;
3686 uint32_t missed_beacons;
3257 uint8_t beacon_filter_average_energy;
3258 uint8_t beacon_filter_reason;
3259 uint8_t beacon_filter_current_energy;
3260 uint8_t beacon_filter_reserved;
3687 int8_t beacon_filter_average_energy;
3688 int8_t beacon_filter_reason;
3689 int8_t beacon_filter_current_energy;
3690 int8_t beacon_filter_reserved;
3261 uint32_t beacon_filter_delta_time;
3262 struct iwm_statistics_bt_activity bt_activity;
3691 uint32_t beacon_filter_delta_time;
3692 struct iwm_statistics_bt_activity bt_activity;
3263 uint64_t rx_time;
3264 uint64_t on_time_rf;
3265 uint64_t on_time_scan;
3266 uint64_t tx_time;
3267 uint32_t beacon_counter[IWM_NUM_MAC_INDEX];
3268 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX];
3269 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)];
3270} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */
3693} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3271
3272struct iwm_statistics_rx {
3273 struct iwm_statistics_rx_phy ofdm;
3274 struct iwm_statistics_rx_phy cck;
3275 struct iwm_statistics_rx_non_phy general;
3276 struct iwm_statistics_rx_ht_phy ofdm_ht;
3277} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3278
3279/*
3280 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3281 *
3282 * By default, uCode issues this notification after receiving a beacon
3283 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3694
3695struct iwm_statistics_rx {
3696 struct iwm_statistics_rx_phy ofdm;
3697 struct iwm_statistics_rx_phy cck;
3698 struct iwm_statistics_rx_non_phy general;
3699 struct iwm_statistics_rx_ht_phy ofdm_ht;
3700} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3701
3702/*
3703 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3704 *
3705 * By default, uCode issues this notification after receiving a beacon
3706 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3284 * IWM_STATISTICS_CMD (0x9c), below.
3707 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3708 *
3709 * Statistics counters continue to increment beacon after beacon, but are
3710 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3711 * 0x9c with CLEAR_STATS bit set (see above).
3712 *
3713 * uCode also issues this notification during scans. uCode clears statistics
3714 * appropriately so that each notification contains statistics for only the
3715 * one channel that has just been scanned.
3285 */
3286
3716 */
3717
3287struct iwm_notif_statistics_v10 {
3718struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3288 uint32_t flag;
3289 struct iwm_statistics_rx rx;
3290 struct iwm_statistics_tx tx;
3719 uint32_t flag;
3720 struct iwm_statistics_rx rx;
3721 struct iwm_statistics_tx tx;
3291 struct iwm_statistics_general_v8 general;
3292} __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */
3722 struct iwm_statistics_general general;
3723} __packed;
3293
3724
3294#define IWM_STATISTICS_FLG_CLEAR 0x1
3295#define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2
3296
3297struct iwm_statistics_cmd {
3298 uint32_t flags;
3299} __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */
3300
3301/***********************************
3302 * Smart Fifo API
3303 ***********************************/
3304/* Smart Fifo state */
3725/***********************************
3726 * Smart Fifo API
3727 ***********************************/
3728/* Smart Fifo state */
3729
3305enum iwm_sf_state {
3306 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3307 IWM_SF_FULL_ON,
3308 IWM_SF_UNINIT,
3309 IWM_SF_INIT_OFF,
3310 IWM_SF_HW_NUM_STATES
3311};
3312

--- 17 unchanged lines hidden (view full) ---

3330#define IWM_SF_W_MARK_LEGACY 4096
3331#define IWM_SF_W_MARK_SCAN 4096
3332
3333/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3334#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3335#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3336#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3337#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3730enum iwm_sf_state {
3731 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3732 IWM_SF_FULL_ON,
3733 IWM_SF_UNINIT,
3734 IWM_SF_INIT_OFF,
3735 IWM_SF_HW_NUM_STATES
3736};
3737

--- 17 unchanged lines hidden (view full) ---

3755#define IWM_SF_W_MARK_LEGACY 4096
3756#define IWM_SF_W_MARK_SCAN 4096
3757
3758/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3759#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3760#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3761#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3762#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3338#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3763#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
3339#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3340#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3341#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3342#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3343#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3344
3345/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3346#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */

--- 8 unchanged lines hidden (view full) ---

3355#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3356
3357#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3358
3359#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3360
3361/**
3362 * Smart Fifo configuration command.
3764#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3765#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3766#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3767#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3768#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3769
3770/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3771#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */

--- 8 unchanged lines hidden (view full) ---

3780#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3781
3782#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3783
3784#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3785
3786/**
3787 * Smart Fifo configuration command.
3363 * @state: smart fifo state, types listed in iwm_sf_state.
3364 * @watermark: Minimum allowed available free space in RXF for transient state.
3788 * @state: smart fifo state, types listed in enum %iwm_sf_state.
3789 * @watermark: Minimum allowed availabe free space in RXF for transient state.
3365 * @long_delay_timeouts: aging and idle timer values for each scenario
3366 * in long delay state.
3367 * @full_on_timeouts: timer values for each scenario in full on state.
3368 */
3369struct iwm_sf_cfg_cmd {
3370 uint32_t state;
3371 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3372 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3373 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3374} __packed; /* IWM_SF_CFG_API_S_VER_2 */
3375
3376/*
3377 * END mvm/fw-api.h
3378 */
3379
3380/*
3381 * BEGIN mvm/fw-api-mac.h
3382 */
3383
3790 * @long_delay_timeouts: aging and idle timer values for each scenario
3791 * in long delay state.
3792 * @full_on_timeouts: timer values for each scenario in full on state.
3793 */
3794struct iwm_sf_cfg_cmd {
3795 uint32_t state;
3796 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3797 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3798 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3799} __packed; /* IWM_SF_CFG_API_S_VER_2 */
3800
3801/*
3802 * END mvm/fw-api.h
3803 */
3804
3805/*
3806 * BEGIN mvm/fw-api-mac.h
3807 */
3808
3384enum iwm_ac {
3385 IWM_AC_BK,
3386 IWM_AC_BE,
3387 IWM_AC_VI,
3388 IWM_AC_VO,
3389 IWM_AC_NUM,
3390};
3809/*
3810 * The first MAC indices (starting from 0)
3811 * are available to the driver, AUX follows
3812 */
3813#define IWM_MAC_INDEX_AUX 4
3814#define IWM_MAC_INDEX_MIN_DRIVER 0
3815#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3391
3816
3817#define IWM_AC_BK 0
3818#define IWM_AC_BE 1
3819#define IWM_AC_VI 2
3820#define IWM_AC_VO 3
3821#define IWM_AC_NUM 4
3822
3392/**
3823/**
3393 * enum iwm_mac_protection_flags - MAC context flags
3824 * MAC context flags
3394 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3395 * this will require CCK RTS/CTS2self.
3396 * RTS/CTS will protect full burst time.
3397 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3398 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3399 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3400 */
3825 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3826 * this will require CCK RTS/CTS2self.
3827 * RTS/CTS will protect full burst time.
3828 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3829 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3830 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3831 */
3401enum iwm_mac_protection_flags {
3402 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3403 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3404 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3405 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3406};
3832#define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3)
3833#define IWM_MAC_PROT_FLG_HT_PROT (1 << 23)
3834#define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24)
3835#define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)
3407
3408#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3836
3837#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3409#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3838#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3410
3411/**
3839
3840/**
3412 * enum iwm_mac_types - Supported MAC types
3841 * Supported MAC types
3413 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3414 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3415 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3416 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3417 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3418 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3419 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3420 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3421 * @IWM_FW_MAC_TYPE_GO: P2P GO
3422 * @IWM_FW_MAC_TYPE_TEST: ?
3423 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3424 */
3842 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3843 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3844 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3845 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3846 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3847 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3848 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3849 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3850 * @IWM_FW_MAC_TYPE_GO: P2P GO
3851 * @IWM_FW_MAC_TYPE_TEST: ?
3852 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3853 */
3425enum iwm_mac_types {
3426 IWM_FW_MAC_TYPE_FIRST = 1,
3427 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3428 IWM_FW_MAC_TYPE_LISTENER,
3429 IWM_FW_MAC_TYPE_PIBSS,
3430 IWM_FW_MAC_TYPE_IBSS,
3431 IWM_FW_MAC_TYPE_BSS_STA,
3432 IWM_FW_MAC_TYPE_P2P_DEVICE,
3433 IWM_FW_MAC_TYPE_P2P_STA,
3434 IWM_FW_MAC_TYPE_GO,
3435 IWM_FW_MAC_TYPE_TEST,
3436 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3437}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3854#define IWM_FW_MAC_TYPE_FIRST 1
3855#define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST
3856#define IWM_FW_MAC_TYPE_LISTENER 2
3857#define IWM_FW_MAC_TYPE_PIBSS 3
3858#define IWM_FW_MAC_TYPE_IBSS 4
3859#define IWM_FW_MAC_TYPE_BSS_STA 5
3860#define IWM_FW_MAC_TYPE_P2P_DEVICE 6
3861#define IWM_FW_MAC_TYPE_P2P_STA 7
3862#define IWM_FW_MAC_TYPE_GO 8
3863#define IWM_FW_MAC_TYPE_TEST 9
3864#define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST
3865/* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3438
3439/**
3866
3867/**
3440 * enum iwm_tsf_id - TSF hw timer ID
3868 * TSF hw timer ID
3441 * @IWM_TSF_ID_A: use TSF A
3442 * @IWM_TSF_ID_B: use TSF B
3443 * @IWM_TSF_ID_C: use TSF C
3444 * @IWM_TSF_ID_D: use TSF D
3445 * @IWM_NUM_TSF_IDS: number of TSF timers available
3446 */
3869 * @IWM_TSF_ID_A: use TSF A
3870 * @IWM_TSF_ID_B: use TSF B
3871 * @IWM_TSF_ID_C: use TSF C
3872 * @IWM_TSF_ID_D: use TSF D
3873 * @IWM_NUM_TSF_IDS: number of TSF timers available
3874 */
3447enum iwm_tsf_id {
3448 IWM_TSF_ID_A = 0,
3449 IWM_TSF_ID_B = 1,
3450 IWM_TSF_ID_C = 2,
3451 IWM_TSF_ID_D = 3,
3452 IWM_NUM_TSF_IDS = 4,
3453}; /* IWM_TSF_ID_API_E_VER_1 */
3875#define IWM_TSF_ID_A 0
3876#define IWM_TSF_ID_B 1
3877#define IWM_TSF_ID_C 2
3878#define IWM_TSF_ID_D 3
3879#define IWM_NUM_TSF_IDS 4
3880/* IWM_TSF_ID_API_E_VER_1 */
3454
3455/**
3456 * struct iwm_mac_data_ap - configuration data for AP MAC context
3457 * @beacon_time: beacon transmit time in system time
3458 * @beacon_tsf: beacon transmit time in TSF
3459 * @bi: beacon interval in TU
3460 * @bi_reciprocal: 2^32 / bi
3461 * @dtim_interval: dtim transmit time in TU
3462 * @dtim_reciprocal: 2^32 / dtim_interval
3463 * @mcast_qid: queue ID for multicast traffic
3881
3882/**
3883 * struct iwm_mac_data_ap - configuration data for AP MAC context
3884 * @beacon_time: beacon transmit time in system time
3885 * @beacon_tsf: beacon transmit time in TSF
3886 * @bi: beacon interval in TU
3887 * @bi_reciprocal: 2^32 / bi
3888 * @dtim_interval: dtim transmit time in TU
3889 * @dtim_reciprocal: 2^32 / dtim_interval
3890 * @mcast_qid: queue ID for multicast traffic
3891 * NOTE: obsolete from VER2 and on
3464 * @beacon_template: beacon template ID
3465 */
3466struct iwm_mac_data_ap {
3467 uint32_t beacon_time;
3468 uint64_t beacon_tsf;
3469 uint32_t bi;
3470 uint32_t bi_reciprocal;
3471 uint32_t dtim_interval;
3472 uint32_t dtim_reciprocal;
3473 uint32_t mcast_qid;
3474 uint32_t beacon_template;
3892 * @beacon_template: beacon template ID
3893 */
3894struct iwm_mac_data_ap {
3895 uint32_t beacon_time;
3896 uint64_t beacon_tsf;
3897 uint32_t bi;
3898 uint32_t bi_reciprocal;
3899 uint32_t dtim_interval;
3900 uint32_t dtim_reciprocal;
3901 uint32_t mcast_qid;
3902 uint32_t beacon_template;
3475} __packed; /* AP_MAC_DATA_API_S_VER_1 */
3903} __packed; /* AP_MAC_DATA_API_S_VER_2 */
3476
3477/**
3478 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3479 * @beacon_time: beacon transmit time in system time
3480 * @beacon_tsf: beacon transmit time in TSF
3481 * @bi: beacon interval in TU
3482 * @bi_reciprocal: 2^32 / bi
3483 * @beacon_template: beacon template ID

--- 73 unchanged lines hidden (view full) ---

3557 * effect on the platform power, as this setting opens the Rx filters on
3558 * all macs.
3559 */
3560struct iwm_mac_data_p2p_dev {
3561 uint32_t is_disc_extended;
3562} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3563
3564/**
3904
3905/**
3906 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3907 * @beacon_time: beacon transmit time in system time
3908 * @beacon_tsf: beacon transmit time in TSF
3909 * @bi: beacon interval in TU
3910 * @bi_reciprocal: 2^32 / bi
3911 * @beacon_template: beacon template ID

--- 73 unchanged lines hidden (view full) ---

3985 * effect on the platform power, as this setting opens the Rx filters on
3986 * all macs.
3987 */
3988struct iwm_mac_data_p2p_dev {
3989 uint32_t is_disc_extended;
3990} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3991
3992/**
3565 * enum iwm_mac_filter_flags - MAC context filter flags
3993 * MAC context filter flags
3566 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3567 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3568 * control frames to the host
3569 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3570 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3571 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3572 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3573 * (in station mode when associated)
3574 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3575 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3576 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3577 */
3994 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3995 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3996 * control frames to the host
3997 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3998 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3999 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
4000 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
4001 * (in station mode when associated)
4002 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
4003 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
4004 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
4005 */
3578enum iwm_mac_filter_flags {
3579 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3580 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3581 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3582 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3583 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3584 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3585 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3586 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3587 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3588};
4006#define IWM_MAC_FILTER_IN_PROMISC (1 << 0)
4007#define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)
4008#define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2)
4009#define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3)
4010#define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)
4011#define IWM_MAC_FILTER_IN_BEACON (1 << 6)
4012#define IWM_MAC_FILTER_OUT_BCAST (1 << 8)
4013#define IWM_MAC_FILTER_IN_CRC32 (1 << 11)
4014#define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)
3589
3590/**
4015
4016/**
3591 * enum iwm_mac_qos_flags - QoS flags
4017 * QoS flags
3592 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3593 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3594 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3595 *
3596 */
4018 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
4019 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
4020 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
4021 *
4022 */
3597enum iwm_mac_qos_flags {
3598 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3599 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3600 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3601};
4023#define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)
4024#define IWM_MAC_QOS_FLG_TGN (1 << 1)
4025#define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4)
3602
3603/**
3604 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3605 * @cw_min: Contention window, start value in numbers of slots.
3606 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3607 * @cw_max: Contention window, max value in numbers of slots.
3608 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3609 * @aifsn: Number of slots in Arbitration Interframe Space (before

--- 17 unchanged lines hidden (view full) ---

3627} __packed; /* IWM_AC_QOS_API_S_VER_2 */
3628
3629/**
3630 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3631 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3632 * @id_and_color: ID and color of the MAC
3633 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3634 * @mac_type: one of IWM_FW_MAC_TYPE_*
4026
4027/**
4028 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
4029 * @cw_min: Contention window, start value in numbers of slots.
4030 * Should be a power-of-2, minus 1. Device's default is 0x0f.
4031 * @cw_max: Contention window, max value in numbers of slots.
4032 * Should be a power-of-2, minus 1. Device's default is 0x3f.
4033 * @aifsn: Number of slots in Arbitration Interframe Space (before

--- 17 unchanged lines hidden (view full) ---

4051} __packed; /* IWM_AC_QOS_API_S_VER_2 */
4052
4053/**
4054 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
4055 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
4056 * @id_and_color: ID and color of the MAC
4057 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
4058 * @mac_type: one of IWM_FW_MAC_TYPE_*
3635 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
4059 * @tsf_id: TSF HW timer, one of IWM_TSF_ID_*
3636 * @node_addr: MAC address
3637 * @bssid_addr: BSSID
3638 * @cck_rates: basic rates available for CCK
3639 * @ofdm_rates: basic rates available for OFDM
3640 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3641 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3642 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3643 * @filter_flags: combination of IWM_MAC_FILTER_*

--- 55 unchanged lines hidden (view full) ---

3699
3700/*
3701 * BEGIN mvm/fw-api-power.h
3702 */
3703
3704/* Power Management Commands, Responses, Notifications */
3705
3706/**
4060 * @node_addr: MAC address
4061 * @bssid_addr: BSSID
4062 * @cck_rates: basic rates available for CCK
4063 * @ofdm_rates: basic rates available for OFDM
4064 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
4065 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
4066 * @short_slot: 0x10 for enabling short slots, 0 otherwise
4067 * @filter_flags: combination of IWM_MAC_FILTER_*

--- 55 unchanged lines hidden (view full) ---

4123
4124/*
4125 * BEGIN mvm/fw-api-power.h
4126 */
4127
4128/* Power Management Commands, Responses, Notifications */
4129
4130/**
3707 * enum iwm_ltr_config_flags - masks for LTR config command flags
4131 * masks for LTR config command flags
3708 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status
3709 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow
3710 * memory access
3711 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR
3712 * reg change
3713 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from
3714 * D0 to D3
3715 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register
3716 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register
3717 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD
3718 */
4132 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status
4133 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow
4134 * memory access
4135 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR
4136 * reg change
4137 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from
4138 * D0 to D3
4139 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register
4140 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register
4141 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD
4142 */
3719enum iwm_ltr_config_flags {
3720 IWM_LTR_CFG_FLAG_FEATURE_ENABLE = (1 << 0),
3721 IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = (1 << 1),
3722 IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = (1 << 2),
3723 IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = (1 << 3),
3724 IWM_LTR_CFG_FLAG_SW_SET_SHORT = (1 << 4),
3725 IWM_LTR_CFG_FLAG_SW_SET_LONG = (1 << 5),
3726 IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD = (1 << 6),
3727};
4143#define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001
4144#define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002
4145#define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004
4146#define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008
4147#define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010
4148#define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020
4149#define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040
3728
3729/**
3730 * struct iwm_ltr_config_cmd_v1 - configures the LTR
3731 * @flags: See %enum iwm_ltr_config_flags
3732 */
3733struct iwm_ltr_config_cmd_v1 {
3734 uint32_t flags;
3735 uint32_t static_long;

--- 19 unchanged lines hidden (view full) ---

3755} __packed; /* LTR_CAPABLE_API_S_VER_2 */
3756
3757/* Radio LP RX Energy Threshold measured in dBm */
3758#define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3759#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3760#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3761
3762/**
4150
4151/**
4152 * struct iwm_ltr_config_cmd_v1 - configures the LTR
4153 * @flags: See %enum iwm_ltr_config_flags
4154 */
4155struct iwm_ltr_config_cmd_v1 {
4156 uint32_t flags;
4157 uint32_t static_long;

--- 19 unchanged lines hidden (view full) ---

4177} __packed; /* LTR_CAPABLE_API_S_VER_2 */
4178
4179/* Radio LP RX Energy Threshold measured in dBm */
4180#define IWM_POWER_LPRX_RSSI_THRESHOLD 75
4181#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
4182#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
4183
4184/**
3763 * enum iwm_scan_flags - masks for power table command flags
4185 * Masks for iwm_mac_power_cmd command flags
3764 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3765 * receiver and transmitter. '0' - does not allow.
3766 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3767 * '1' Driver enables PM (use rest of parameters)
3768 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3769 * '1' PM could sleep over DTIM till listen Interval.
3770 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3771 * access categories are both delivery and trigger enabled.
3772 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3773 * PBW Snoozing enabled
3774 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3775 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3776 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3777 * detection enablement
3778*/
4186 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
4187 * receiver and transmitter. '0' - does not allow.
4188 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
4189 * '1' Driver enables PM (use rest of parameters)
4190 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
4191 * '1' PM could sleep over DTIM till listen Interval.
4192 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
4193 * access categories are both delivery and trigger enabled.
4194 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
4195 * PBW Snoozing enabled
4196 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
4197 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
4198 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
4199 * detection enablement
4200*/
3779enum iwm_power_flags {
3780 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3781 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3782 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3783 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3784 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3785 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3786 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3787 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3788};
4201#define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4202#define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)
4203#define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)
4204#define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)
4205#define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8)
4206#define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)
4207#define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)
4208#define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)
3789
3790#define IWM_POWER_VEC_SIZE 5
3791
3792/**
4209
4210#define IWM_POWER_VEC_SIZE 5
4211
4212/**
3793 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3794 * is used also with a new power API for device wide power settings.
3795 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3796 *
3797 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3798 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3799 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3800 * set regardless of power scheme or current power state.
3801 * FW use this value also when PM is disabled.
3802 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3803 * PSM transition - legacy PM
3804 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3805 * PSM transition - legacy PM
3806 * @sleep_interval: not in use
3807 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3808 * is set. For example, if it is required to skip over
3809 * one DTIM, this value need to be set to 2 (DTIM periods).
3810 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3811 * Default: 80dbm
4213 * Masks for device power command flags
4214 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK:
4215 * '1' Allow to save power by turning off receiver and transmitter.
4216 * '0' Do not allow. This flag should be always set to '1' unless
4217 * one needs to disable actual power down for debug purposes.
4218 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK:
4219 * '1' CAM (Continuous Active Mode) is set, power management is disabled.
4220 * '0' Power management is enabled, one of the power schemes is applied.
3812 */
4221 */
3813struct iwm_powertable_cmd {
3814 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3815 uint16_t flags;
3816 uint8_t keep_alive_seconds;
3817 uint8_t debug_flags;
3818 uint32_t rx_data_timeout;
3819 uint32_t tx_data_timeout;
3820 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3821 uint32_t skip_dtim_periods;
3822 uint32_t lprx_rssi_threshold;
3823} __packed;
4222#define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4223#define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)
3824
3825/**
4224
4225/**
3826 * enum iwm_device_power_flags - masks for device power command flags
3827 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3828 * receiver and transmitter. '0' - does not allow.
3829 */
3830enum iwm_device_power_flags {
3831 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3832};
3833
3834/**
3835 * struct iwm_device_power_cmd - device wide power command.
4226 * struct iwm_device_power_cmd - device wide power command.
3836 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
4227 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3837 *
3838 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3839 */
3840struct iwm_device_power_cmd {
3841 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3842 uint16_t flags;
3843 uint16_t reserved;
3844} __packed;

--- 63 unchanged lines hidden (view full) ---

3908 uint8_t heavy_tx_thld_packets;
3909 uint8_t heavy_rx_thld_packets;
3910 uint8_t heavy_tx_thld_percentage;
3911 uint8_t heavy_rx_thld_percentage;
3912 uint8_t limited_ps_threshold;
3913 uint8_t reserved;
3914} __packed;
3915
4228 *
4229 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
4230 */
4231struct iwm_device_power_cmd {
4232 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
4233 uint16_t flags;
4234 uint16_t reserved;
4235} __packed;

--- 63 unchanged lines hidden (view full) ---

4299 uint8_t heavy_tx_thld_packets;
4300 uint8_t heavy_rx_thld_packets;
4301 uint8_t heavy_tx_thld_percentage;
4302 uint8_t heavy_rx_thld_percentage;
4303 uint8_t limited_ps_threshold;
4304 uint8_t reserved;
4305} __packed;
4306
4307#define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)
4308#define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)
4309
3916/*
3917 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3918 * associated AP is identified as improperly implementing uAPSD protocol.
3919 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3920 * @sta_id: index of station in uCode's station table - associated AP ID in
3921 * this context.
3922 */
3923struct iwm_uapsd_misbehaving_ap_notif {

--- 25 unchanged lines hidden (view full) ---

3949 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3950 * If the current temperature is above this threshold - Fast filter
3951 * will be used, If the current temperature is below this threshold -
3952 * Slow filter will be used.
3953 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3954 * calculated for this and the last passed beacon is greater than this
3955 * threshold. Zero value means that the temperature change is ignored for
3956 * beacon filtering; beacons will not be forced to be sent to driver
4310/*
4311 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
4312 * associated AP is identified as improperly implementing uAPSD protocol.
4313 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
4314 * @sta_id: index of station in uCode's station table - associated AP ID in
4315 * this context.
4316 */
4317struct iwm_uapsd_misbehaving_ap_notif {

--- 25 unchanged lines hidden (view full) ---

4343 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
4344 * If the current temperature is above this threshold - Fast filter
4345 * will be used, If the current temperature is below this threshold -
4346 * Slow filter will be used.
4347 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
4348 * calculated for this and the last passed beacon is greater than this
4349 * threshold. Zero value means that the temperature change is ignored for
4350 * beacon filtering; beacons will not be forced to be sent to driver
3957 * regardless of whether its temperature has been changed.
4351 * regardless of whether its temerature has been changed.
3958 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3959 * calculated for this and the last passed beacon is greater than this
3960 * threshold. Zero value means that the temperature change is ignored for
3961 * beacon filtering; beacons will not be forced to be sent to driver
4352 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
4353 * calculated for this and the last passed beacon is greater than this
4354 * threshold. Zero value means that the temperature change is ignored for
4355 * beacon filtering; beacons will not be forced to be sent to driver
3962 * regardless of whether its temperature has been changed.
4356 * regardless of whether its temerature has been changed.
3963 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
4357 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3964 * @bf_filter_escape_timer: Send beacons to the driver if no beacons were passed
4358 * @bf_escape_timer: Send beacons to driver if no beacons were passed
3965 * for a specific period of time. Units: Beacons.
3966 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3967 * for a longer period of time then this escape-timeout. Units: Beacons.
3968 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3969 */
3970struct iwm_beacon_filter_cmd {
3971 uint32_t bf_energy_delta;
3972 uint32_t bf_roaming_energy_delta;

--- 63 unchanged lines hidden (view full) ---

4036/*
4037 * END mvm/fw-api-power.h
4038 */
4039
4040/*
4041 * BEGIN mvm/fw-api-rs.h
4042 */
4043
4359 * for a specific period of time. Units: Beacons.
4360 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
4361 * for a longer period of time then this escape-timeout. Units: Beacons.
4362 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
4363 */
4364struct iwm_beacon_filter_cmd {
4365 uint32_t bf_energy_delta;
4366 uint32_t bf_roaming_energy_delta;

--- 63 unchanged lines hidden (view full) ---

4430/*
4431 * END mvm/fw-api-power.h
4432 */
4433
4434/*
4435 * BEGIN mvm/fw-api-rs.h
4436 */
4437
4438
4439/* uCode API values for HT/VHT bit rates */
4440#define IWM_RATE_HT_SISO_MCS_0_PLCP 0
4441#define IWM_RATE_HT_SISO_MCS_1_PLCP 1
4442#define IWM_RATE_HT_SISO_MCS_2_PLCP 2
4443#define IWM_RATE_HT_SISO_MCS_3_PLCP 3
4444#define IWM_RATE_HT_SISO_MCS_4_PLCP 4
4445#define IWM_RATE_HT_SISO_MCS_5_PLCP 5
4446#define IWM_RATE_HT_SISO_MCS_6_PLCP 6
4447#define IWM_RATE_HT_SISO_MCS_7_PLCP 7
4448#define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8
4449#define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9
4450#define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA
4451#define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB
4452#define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC
4453#define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD
4454#define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE
4455#define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF
4456#define IWM_RATE_VHT_SISO_MCS_0_PLCP 0
4457#define IWM_RATE_VHT_SISO_MCS_1_PLCP 1
4458#define IWM_RATE_VHT_SISO_MCS_2_PLCP 2
4459#define IWM_RATE_VHT_SISO_MCS_3_PLCP 3
4460#define IWM_RATE_VHT_SISO_MCS_4_PLCP 4
4461#define IWM_RATE_VHT_SISO_MCS_5_PLCP 5
4462#define IWM_RATE_VHT_SISO_MCS_6_PLCP 6
4463#define IWM_RATE_VHT_SISO_MCS_7_PLCP 7
4464#define IWM_RATE_VHT_SISO_MCS_8_PLCP 8
4465#define IWM_RATE_VHT_SISO_MCS_9_PLCP 9
4466#define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10
4467#define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11
4468#define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12
4469#define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13
4470#define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14
4471#define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15
4472#define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16
4473#define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17
4474#define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18
4475#define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19
4476#define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20
4477#define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
4478#define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
4479#define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
4480#define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
4481#define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP
4482
4044/*
4045 * These serve as indexes into
4046 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
4047 * TODO: avoid overlap between legacy and HT rates
4048 */
4049enum {
4050 IWM_RATE_1M_INDEX = 0,
4051 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,

--- 25 unchanged lines hidden (view full) ---

4077 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
4078 IWM_RATE_MCS_8_INDEX,
4079 IWM_RATE_MCS_9_INDEX,
4080 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
4081 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
4082 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
4083};
4084
4483/*
4484 * These serve as indexes into
4485 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
4486 * TODO: avoid overlap between legacy and HT rates
4487 */
4488enum {
4489 IWM_RATE_1M_INDEX = 0,
4490 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,

--- 25 unchanged lines hidden (view full) ---

4516 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
4517 IWM_RATE_MCS_8_INDEX,
4518 IWM_RATE_MCS_9_INDEX,
4519 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
4520 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
4521 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
4522};
4523
4524
4085#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
4086
4087/* fw API values for legacy bit rates, both OFDM and CCK */
4525#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
4526
4527/* fw API values for legacy bit rates, both OFDM and CCK */
4088enum {
4089 IWM_RATE_6M_PLCP = 13,
4090 IWM_RATE_9M_PLCP = 15,
4091 IWM_RATE_12M_PLCP = 5,
4092 IWM_RATE_18M_PLCP = 7,
4093 IWM_RATE_24M_PLCP = 9,
4094 IWM_RATE_36M_PLCP = 11,
4095 IWM_RATE_48M_PLCP = 1,
4096 IWM_RATE_54M_PLCP = 3,
4097 IWM_RATE_1M_PLCP = 10,
4098 IWM_RATE_2M_PLCP = 20,
4099 IWM_RATE_5M_PLCP = 55,
4100 IWM_RATE_11M_PLCP = 110,
4101 IWM_RATE_INVM_PLCP = -1,
4102};
4528#define IWM_RATE_6M_PLCP 13
4529#define IWM_RATE_9M_PLCP 15
4530#define IWM_RATE_12M_PLCP 5
4531#define IWM_RATE_18M_PLCP 7
4532#define IWM_RATE_24M_PLCP 9
4533#define IWM_RATE_36M_PLCP 11
4534#define IWM_RATE_48M_PLCP 1
4535#define IWM_RATE_54M_PLCP 3
4536#define IWM_RATE_1M_PLCP 10
4537#define IWM_RATE_2M_PLCP 20
4538#define IWM_RATE_5M_PLCP 55
4539#define IWM_RATE_11M_PLCP 110
4540#define IWM_RATE_INVM_PLCP 0xff
4103
4104/*
4105 * rate_n_flags bit fields
4106 *
4107 * The 32-bit value has different layouts in the low 8 bites depending on the
4108 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
4109 * for CCK and OFDM).
4110 *

--- 14 unchanged lines hidden (view full) ---

4125/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
4126#define IWM_RATE_MCS_CCK_POS 9
4127#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
4128
4129/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
4130#define IWM_RATE_MCS_VHT_POS 26
4131#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
4132
4541
4542/*
4543 * rate_n_flags bit fields
4544 *
4545 * The 32-bit value has different layouts in the low 8 bites depending on the
4546 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
4547 * for CCK and OFDM).
4548 *

--- 14 unchanged lines hidden (view full) ---

4563/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
4564#define IWM_RATE_MCS_CCK_POS 9
4565#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
4566
4567/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
4568#define IWM_RATE_MCS_VHT_POS 26
4569#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
4570
4571/* Bit 31: (1) RTS (2) CTS */
4572#define IWM_RATE_MCS_RTS_REQUIRED_POS 30
4573#define IWM_RATE_MCS_RTS_REQUIRED_MSK (1 << IWM_RATE_MCS_RTS_REQUIRED_POS)
4133
4134/*
4135 * High-throughput (HT) rate format for bits 7:0
4136 *
4137 * 2-0: MCS rate base
4138 * 0) 6 Mbps
4139 * 1) 12 Mbps
4140 * 2) 18 Mbps

--- 62 unchanged lines hidden (view full) ---

4203 */
4204#define IWM_RATE_LEGACY_RATE_MSK 0xff
4205
4206
4207/*
4208 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4209 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4210 */
4574
4575/*
4576 * High-throughput (HT) rate format for bits 7:0
4577 *
4578 * 2-0: MCS rate base
4579 * 0) 6 Mbps
4580 * 1) 12 Mbps
4581 * 2) 18 Mbps

--- 62 unchanged lines hidden (view full) ---

4644 */
4645#define IWM_RATE_LEGACY_RATE_MSK 0xff
4646
4647
4648/*
4649 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4650 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4651 */
4211#define IWM_RATE_MCS_CHAN_WIDTH_POS 11
4212#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4213#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4214#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4215#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4216#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4652#define IWM_RATE_MCS_CHAN_WIDTH_POS 11
4653#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4654#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4655#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4656#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4657#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4217
4218/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4219#define IWM_RATE_MCS_SGI_POS 13
4220#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
4221
4222/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4223#define IWM_RATE_MCS_ANT_POS 14
4224#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4225#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4226#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4227#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4228 IWM_RATE_MCS_ANT_B_MSK)
4658
4659/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4660#define IWM_RATE_MCS_SGI_POS 13
4661#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
4662
4663/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4664#define IWM_RATE_MCS_ANT_POS 14
4665#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4666#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4667#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4668#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4669 IWM_RATE_MCS_ANT_B_MSK)
4229#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4670#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4230 IWM_RATE_MCS_ANT_C_MSK)
4231#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4232#define IWM_RATE_MCS_ANT_NUM 3
4233
4234/* Bit 17-18: (0) SS, (1) SS*2 */
4235#define IWM_RATE_MCS_STBC_POS 17
4236#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4237
4238/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4671 IWM_RATE_MCS_ANT_C_MSK)
4672#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4673#define IWM_RATE_MCS_ANT_NUM 3
4674
4675/* Bit 17-18: (0) SS, (1) SS*2 */
4676#define IWM_RATE_MCS_STBC_POS 17
4677#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4678
4679/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4239#define IWM_RATE_MCS_BF_POS 19
4240#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4680#define IWM_RATE_MCS_BF_POS 19
4681#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4241
4242/* Bit 20: (0) ZLF is off, (1) ZLF is on */
4243#define IWM_RATE_MCS_ZLF_POS 20
4244#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4245
4246/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4247#define IWM_RATE_MCS_DUP_POS 24
4248#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)

--- 6 unchanged lines hidden (view full) ---

4255/* Link Quality definitions */
4256
4257/* # entries in rate scale table to support Tx retries */
4258#define IWM_LQ_MAX_RETRY_NUM 16
4259
4260/* Link quality command flags bit fields */
4261
4262/* Bit 0: (0) Don't use RTS (1) Use RTS */
4682
4683/* Bit 20: (0) ZLF is off, (1) ZLF is on */
4684#define IWM_RATE_MCS_ZLF_POS 20
4685#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4686
4687/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4688#define IWM_RATE_MCS_DUP_POS 24
4689#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)

--- 6 unchanged lines hidden (view full) ---

4696/* Link Quality definitions */
4697
4698/* # entries in rate scale table to support Tx retries */
4699#define IWM_LQ_MAX_RETRY_NUM 16
4700
4701/* Link quality command flags bit fields */
4702
4703/* Bit 0: (0) Don't use RTS (1) Use RTS */
4263#define IWM_LQ_FLAG_USE_RTS_POS 0
4264#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4704#define IWM_LQ_FLAG_USE_RTS_POS 0
4705#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4265
4266/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4706
4707/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4267#define IWM_LQ_FLAG_COLOR_POS 1
4268#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4708#define IWM_LQ_FLAG_COLOR_POS 1
4709#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4269
4270/* Bit 4-5: Tx RTS BW Signalling
4271 * (0) No RTS BW signalling
4272 * (1) Static BW signalling
4273 * (2) Dynamic BW signalling
4274 */
4710
4711/* Bit 4-5: Tx RTS BW Signalling
4712 * (0) No RTS BW signalling
4713 * (1) Static BW signalling
4714 * (2) Dynamic BW signalling
4715 */
4275#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4276#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4277#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4278#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4716#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4717#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4718#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4719#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4279
4280/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4281 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4282 */
4720
4721/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4722 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4723 */
4283#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4284#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4724#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4725#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4285
4726
4286/* Single Stream Tx Parameters (lq_cmd->ss_params)
4287 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
4288 * used for single stream Tx.
4289 */
4727/* Antenna flags. */
4728#define IWM_ANT_A (1 << 0)
4729#define IWM_ANT_B (1 << 1)
4730#define IWM_ANT_C (1 << 2)
4731/* Shortcuts. */
4732#define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B)
4733#define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C)
4734#define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C)
4290
4735
4291/* Bit 0-1: Max STBC streams allowed. Can be 0-3.
4292 * (0) - No STBC allowed
4293 * (1) - 2x1 STBC allowed (HT/VHT)
4294 * (2) - 4x2 STBC allowed (HT/VHT)
4295 * (3) - 3x2 STBC allowed (HT only)
4296 * All our chips are at most 2 antennas so only (1) is valid for now.
4297 */
4298#define IWM_LQ_SS_STBC_ALLOWED_POS 0
4299#define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK)
4300
4301/* 2x1 STBC is allowed */
4302#define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS)
4303
4304/* Bit 2: Beamformer (VHT only) is allowed */
4305#define IWM_LQ_SS_BFER_ALLOWED_POS 2
4306#define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS)
4307
4308/* Bit 3: Force BFER or STBC for testing
4309 * If this is set:
4310 * If BFER is allowed then force the ucode to choose BFER else
4311 * If STBC is allowed then force the ucode to choose STBC over SISO
4312 */
4313#define IWM_LQ_SS_FORCE_POS 3
4314#define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS)
4315
4316/* Bit 31: ss_params field is valid. Used for FW backward compatibility
4317 * with other drivers which don't support the ss_params API yet
4318 */
4319#define IWM_LQ_SS_PARAMS_VALID_POS 31
4320#define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS)
4321
4322/**
4323 * struct iwm_lq_cmd - link quality command
4324 * @sta_id: station to update
4325 * @control: not used
4326 * @flags: combination of IWM_LQ_FLAG_*
4327 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4328 * and SISO rates
4329 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4736/**
4737 * struct iwm_lq_cmd - link quality command
4738 * @sta_id: station to update
4739 * @control: not used
4740 * @flags: combination of IWM_LQ_FLAG_*
4741 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4742 * and SISO rates
4743 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4330 * Should be ANT_[ABC]
4331 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4744 * Should be IWM_ANT_[ABC]
4745 * @dual_stream_ant_msk: best antennas for MIMO, combination of IWM_ANT_[ABC]
4332 * @initial_rate_index: first index from rs_table per AC category
4333 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4334 * value of 100 is one usec. Range is 100 to 8000
4335 * @agg_disable_start_th: try-count threshold for starting aggregation.
4336 * If a frame has higher try-count, it should not be selected for
4337 * starting an aggregation sequence.
4338 * @agg_frame_cnt_limit: max frame count in an aggregation.
4339 * 0: no limit
4340 * 1: no aggregation (one frame per aggregation)
4341 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4342 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4343 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4746 * @initial_rate_index: first index from rs_table per AC category
4747 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4748 * value of 100 is one usec. Range is 100 to 8000
4749 * @agg_disable_start_th: try-count threshold for starting aggregation.
4750 * If a frame has higher try-count, it should not be selected for
4751 * starting an aggregation sequence.
4752 * @agg_frame_cnt_limit: max frame count in an aggregation.
4753 * 0: no limit
4754 * 1: no aggregation (one frame per aggregation)
4755 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4756 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4757 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4344 * @ss_params: single stream features. declare whether STBC or BFER are allowed.
4758 * @bf_params: beam forming params, currently not used
4345 */
4346struct iwm_lq_cmd {
4347 uint8_t sta_id;
4759 */
4760struct iwm_lq_cmd {
4761 uint8_t sta_id;
4348 uint8_t reduced_tpc;
4762 uint8_t reserved1;
4349 uint16_t control;
4350 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4351 uint8_t flags;
4352 uint8_t mimo_delim;
4353 uint8_t single_stream_ant_msk;
4354 uint8_t dual_stream_ant_msk;
4355 uint8_t initial_rate_index[IWM_AC_NUM];
4356 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4357 uint16_t agg_time_limit;
4358 uint8_t agg_disable_start_th;
4359 uint8_t agg_frame_cnt_limit;
4360 uint32_t reserved2;
4361 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4763 uint16_t control;
4764 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4765 uint8_t flags;
4766 uint8_t mimo_delim;
4767 uint8_t single_stream_ant_msk;
4768 uint8_t dual_stream_ant_msk;
4769 uint8_t initial_rate_index[IWM_AC_NUM];
4770 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4771 uint16_t agg_time_limit;
4772 uint8_t agg_disable_start_th;
4773 uint8_t agg_frame_cnt_limit;
4774 uint32_t reserved2;
4775 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4362 uint32_t ss_params;
4776 uint32_t bf_params;
4363}; /* LINK_QUALITY_CMD_API_S_VER_1 */
4364
4365/*
4366 * END mvm/fw-api-rs.h
4367 */
4368
4369/*
4370 * BEGIN mvm/fw-api-tx.h
4371 */
4372
4373/**
4777}; /* LINK_QUALITY_CMD_API_S_VER_1 */
4778
4779/*
4780 * END mvm/fw-api-rs.h
4781 */
4782
4783/*
4784 * BEGIN mvm/fw-api-tx.h
4785 */
4786
4787/**
4374 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4788 * bitmasks for tx_flags in TX command
4375 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4376 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4377 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4378 * Otherwise, use rate_n_flags from the TX command
4379 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4380 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4381 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4382 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection

--- 8 unchanged lines hidden (view full) ---

4391 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4392 * Should be set for beacons and probe responses
4393 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4394 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4395 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4396 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4397 * Should be set for 26/30 length MAC headers
4398 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4789 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4790 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4791 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4792 * Otherwise, use rate_n_flags from the TX command
4793 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4794 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4795 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4796 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection

--- 8 unchanged lines hidden (view full) ---

4805 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4806 * Should be set for beacons and probe responses
4807 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4808 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4809 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4810 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4811 * Should be set for 26/30 length MAC headers
4812 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4813 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4399 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4400 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4401 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4402 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4403 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4404 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4405 */
4814 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4815 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4816 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4817 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4818 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4819 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4820 */
4406enum iwm_tx_flags {
4407 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4408 IWM_TX_CMD_FLG_ACK = (1 << 3),
4409 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4410 IWM_TX_CMD_FLG_BA = (1 << 5),
4411 IWM_TX_CMD_FLG_BAR = (1 << 6),
4412 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4413 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4414 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4415 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4416 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4417 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4418 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4419 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4420 IWM_TX_CMD_FLG_TSF = (1 << 16),
4421 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4422 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4423 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4424 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4425 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4426 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4427 IWM_TX_CMD_FLG_DUR = (1 << 25),
4428 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4429 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4430 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4431 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4432}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4821#define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0)
4822#define IWM_TX_CMD_FLG_ACK (1 << 3)
4823#define IWM_TX_CMD_FLG_STA_RATE (1 << 4)
4824#define IWM_TX_CMD_FLG_BA (1 << 5)
4825#define IWM_TX_CMD_FLG_BAR (1 << 6)
4826#define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7)
4827#define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8)
4828#define IWM_TX_CMD_FLG_HT_NDPA (1 << 9)
4829#define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10)
4830#define IWM_TX_CMD_FLG_BT_DIS (1 << 12)
4831#define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13)
4832#define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14)
4833#define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15)
4834#define IWM_TX_CMD_FLG_TSF (1 << 16)
4835#define IWM_TX_CMD_FLG_CALIB (1 << 17)
4836#define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18)
4837#define IWM_TX_CMD_FLG_AGG_START (1 << 19)
4838#define IWM_TX_CMD_FLG_MH_PAD (1 << 20)
4839#define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21)
4840#define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22)
4841#define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23)
4842#define IWM_TX_CMD_FLG_DUR (1 << 25)
4843#define IWM_TX_CMD_FLG_FW_DROP (1 << 26)
4844#define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27)
4845#define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28)
4846#define IWM_TX_CMD_FLG_HCCA_CHUNK (1U << 31)
4847/* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4433
4434/**
4435 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4436 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4437 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4438 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4439 */
4440enum iwm_tx_pm_timeouts {
4848
4849/**
4850 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4851 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4852 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4853 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4854 */
4855enum iwm_tx_pm_timeouts {
4441 IWM_PM_FRAME_NONE = 0,
4442 IWM_PM_FRAME_MGMT = 2,
4443 IWM_PM_FRAME_ASSOC = 3,
4856 IWM_PM_FRAME_NONE = 0,
4857 IWM_PM_FRAME_MGMT = 2,
4858 IWM_PM_FRAME_ASSOC = 3,
4444};
4445
4446/*
4447 * TX command security control
4448 */
4449#define IWM_TX_CMD_SEC_WEP 0x01
4450#define IWM_TX_CMD_SEC_CCM 0x02
4451#define IWM_TX_CMD_SEC_TKIP 0x03
4452#define IWM_TX_CMD_SEC_EXT 0x04
4453#define IWM_TX_CMD_SEC_MSK 0x07
4454#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4455#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4456#define IWM_TX_CMD_SEC_KEY128 0x08
4457
4859};
4860
4861/*
4862 * TX command security control
4863 */
4864#define IWM_TX_CMD_SEC_WEP 0x01
4865#define IWM_TX_CMD_SEC_CCM 0x02
4866#define IWM_TX_CMD_SEC_TKIP 0x03
4867#define IWM_TX_CMD_SEC_EXT 0x04
4868#define IWM_TX_CMD_SEC_MSK 0x07
4869#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4870#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4871#define IWM_TX_CMD_SEC_KEY128 0x08
4872
4873/* TODO: how does these values are OK with only 16 bit variable??? */
4458/*
4874/*
4875 * TX command next frame info
4876 *
4877 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4878 * bit 3 - immediate ACK required
4879 * bit 4 - rate is taken from STA table
4880 * bit 5 - frame belongs to BA stream
4881 * bit 6 - immediate BA response expected
4882 * bit 7 - unused
4883 * bits 8:15 - Station ID
4884 * bits 16:31 - rate
4885 */
4886#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4887#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4888#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4889#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4890#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4891#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4892#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4893#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4894#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4895
4896/*
4459 * TX command Frame life time in us - to be written in pm_frame_timeout
4460 */
4461#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4462#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4463#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4464#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4465
4466/*
4467 * TID for non QoS frames - to be written in tid_tspec
4468 */
4897 * TX command Frame life time in us - to be written in pm_frame_timeout
4898 */
4899#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4900#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4901#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4902#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4903
4904/*
4905 * TID for non QoS frames - to be written in tid_tspec
4906 */
4469#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4907#define IWM_MAX_TID_COUNT 8
4908#define IWM_TID_NON_QOS 0
4909#define IWM_TID_MGMT 15
4470
4471/*
4472 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4473 */
4474#define IWM_DEFAULT_TX_RETRY 15
4475#define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4910
4911/*
4912 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4913 */
4914#define IWM_DEFAULT_TX_RETRY 15
4915#define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4476#define IWM_RTS_DFAULT_RETRY_LIMIT 60
4916#define IWM_RTS_DFAULT_RETRY_LIMIT 3
4477#define IWM_BAR_DFAULT_RETRY_LIMIT 60
4478#define IWM_LOW_RETRY_LIMIT 7
4479
4480/**
4481 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values
4917#define IWM_BAR_DFAULT_RETRY_LIMIT 60
4918#define IWM_LOW_RETRY_LIMIT 7
4919
4920/**
4921 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values
4482 * @IWM_TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words)
4922 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words)
4483 * from mac header end. For normal case it is 4 words for SNAP.
4484 * note: tx_cmd, mac header and pad are not counted in the offset.
4485 * This is used to help the offload in case there is tunneling such as
4486 * IPv6 in IPv4, in such case the ip header offset should point to the
4487 * inner ip header and IPv4 checksum of the external header should be
4488 * calculated by driver.
4923 * from mac header end. For normal case it is 4 words for SNAP.
4924 * note: tx_cmd, mac header and pad are not counted in the offset.
4925 * This is used to help the offload in case there is tunneling such as
4926 * IPv6 in IPv4, in such case the ip header offset should point to the
4927 * inner ip header and IPv4 checksum of the external header should be
4928 * calculated by driver.
4489 * @IWM_TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
4490 * @IWM_TX_CMD_OFFLD_L3_EN: enable IP header checksum
4491 * @IWM_TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV
4929 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
4930 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum
4931 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV
4492 * field. Doesn't include the pad.
4932 * field. Doesn't include the pad.
4493 * @IWM_TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
4933 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
4494 * alignment
4934 * alignment
4495 * @IWM_TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
4935 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
4496 */
4936 */
4497enum iwm_tx_offload_assist_flags_pos {
4498 IWM_TX_CMD_OFFLD_IP_HDR = 0,
4499 IWM_TX_CMD_OFFLD_L4_EN = 6,
4500 IWM_TX_CMD_OFFLD_L3_EN = 7,
4501 IWM_TX_CMD_OFFLD_MH_SIZE = 8,
4502 IWM_TX_CMD_OFFLD_PAD = 13,
4503 IWM_TX_CMD_OFFLD_AMSDU = 14,
4504};
4937#define IWM_TX_CMD_OFFLD_IP_HDR (1 << 0)
4938#define IWM_TX_CMD_OFFLD_L4_EN (1 << 6)
4939#define IWM_TX_CMD_OFFLD_L3_EN (1 << 7)
4940#define IWM_TX_CMD_OFFLD_MH_SIZE (1 << 8)
4941#define IWM_TX_CMD_OFFLD_PAD (1 << 13)
4942#define IWM_TX_CMD_OFFLD_AMSDU (1 << 14)
4505
4943
4506#define IWM_TX_CMD_OFFLD_MH_MASK 0x1f
4507#define IWM_TX_CMD_OFFLD_IP_HDR_MASK 0x3f
4508
4509/* TODO: complete documentation for try_cnt and btkill_cnt */
4510/**
4511 * struct iwm_tx_cmd - TX command struct to FW
4512 * ( IWM_TX_CMD = 0x1c )
4513 * @len: in bytes of the payload, see below for details
4514 * @offload_assist: TX offload configuration
4515 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4516 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4517 * cleared. Combination of IWM_RATE_MCS_*
4518 * @sta_id: index of destination station in FW station table
4519 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4520 * @initial_rate_index: index into the rate table for initial TX attempt.
4521 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4522 * @key: security key
4944/* TODO: complete documentation for try_cnt and btkill_cnt */
4945/**
4946 * struct iwm_tx_cmd - TX command struct to FW
4947 * ( IWM_TX_CMD = 0x1c )
4948 * @len: in bytes of the payload, see below for details
4949 * @offload_assist: TX offload configuration
4950 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4951 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4952 * cleared. Combination of IWM_RATE_MCS_*
4953 * @sta_id: index of destination station in FW station table
4954 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4955 * @initial_rate_index: index into the rate table for initial TX attempt.
4956 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4957 * @key: security key
4523 * @reserved3: reserved
4958 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4524 * @life_time: frame life time (usecs??)
4525 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4526 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4527 * @dram_msb_ptr: upper bits of the scratch physical address
4528 * @rts_retry_limit: max attempts for RTS
4529 * @data_retry_limit: max attempts to send the data packet
4530 * @tid_spec: TID/tspec
4531 * @pm_frame_timeout: PM TX frame timeout

--- 34 unchanged lines hidden (view full) ---

4566 uint8_t dram_msb_ptr;
4567 uint8_t rts_retry_limit;
4568 uint8_t data_retry_limit;
4569 uint8_t tid_tspec;
4570 uint16_t pm_frame_timeout;
4571 uint16_t reserved4;
4572 uint8_t payload[0];
4573 struct ieee80211_frame hdr[0];
4959 * @life_time: frame life time (usecs??)
4960 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4961 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4962 * @dram_msb_ptr: upper bits of the scratch physical address
4963 * @rts_retry_limit: max attempts for RTS
4964 * @data_retry_limit: max attempts to send the data packet
4965 * @tid_spec: TID/tspec
4966 * @pm_frame_timeout: PM TX frame timeout

--- 34 unchanged lines hidden (view full) ---

5001 uint8_t dram_msb_ptr;
5002 uint8_t rts_retry_limit;
5003 uint8_t data_retry_limit;
5004 uint8_t tid_tspec;
5005 uint16_t pm_frame_timeout;
5006 uint16_t reserved4;
5007 uint8_t payload[0];
5008 struct ieee80211_frame hdr[0];
4574} __packed; /* IWM_TX_CMD_API_S_VER_3 */
5009} __packed; /* IWM_TX_CMD_API_S_VER_6 */
4575
4576/*
4577 * TX response related data
4578 */
4579
4580/*
5010
5011/*
5012 * TX response related data
5013 */
5014
5015/*
4581 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4582 * @IWM_TX_STATUS_SUCCESS:
4583 * @IWM_TX_STATUS_DIRECT_DONE:
4584 * @IWM_TX_STATUS_POSTPONE_DELAY:
4585 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4586 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4587 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4588 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4589 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4590 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4591 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4592 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4593 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4594 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4595 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4596 * @IWM_TX_STATUS_FAIL_DEST_PS:
4597 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4598 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4599 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4600 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4601 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4602 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4603 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4604 * @IWM_TX_STATUS_FAIL_FW_DROP:
5016 * status that is returned by the fw after attempts to Tx
4605 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4606 * STA table
5017 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
5018 * STA table
4607 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4608 * @IWM_TX_MODE_MSK:
4609 * @IWM_TX_MODE_NO_BURST:
4610 * @IWM_TX_MODE_IN_BURST_SEQ:
4611 * @IWM_TX_MODE_FIRST_IN_BURST:
4612 * @IWM_TX_QUEUE_NUM_MSK:
4613 *
4614 * Valid only if frame_count =1
5019 * Valid only if frame_count =1
4615 * TODO: complete documentation
4616 */
5020 */
4617enum iwm_tx_status {
4618 IWM_TX_STATUS_MSK = 0x000000ff,
4619 IWM_TX_STATUS_SUCCESS = 0x01,
4620 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4621 /* postpone TX */
4622 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4623 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4624 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4625 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4626 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4627 /* abort TX */
4628 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4629 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4630 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4631 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4632 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4633 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4634 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4635 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4636 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4637 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4638 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4639 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4640 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4641 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4642 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4643 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4644 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4645 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4646 IWM_TX_MODE_MSK = 0x00000f00,
4647 IWM_TX_MODE_NO_BURST = 0x00000000,
4648 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4649 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4650 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4651 IWM_TX_NARROW_BW_MSK = 0x00060000,
4652 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4653 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4654 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4655};
5021#define IWM_TX_STATUS_MSK 0x000000ff
5022#define IWM_TX_STATUS_SUCCESS 0x01
5023#define IWM_TX_STATUS_DIRECT_DONE 0x02
5024/* postpone TX */
5025#define IWM_TX_STATUS_POSTPONE_DELAY 0x40
5026#define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41
5027#define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42
5028#define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
5029#define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44
5030/* abort TX */
5031#define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
5032#define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82
5033#define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83
5034#define IWM_TX_STATUS_FAIL_UNDERRUN 0x84
5035#define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85
5036#define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
5037#define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
5038#define IWM_TX_STATUS_FAIL_DEST_PS 0x88
5039#define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89
5040#define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a
5041#define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b
5042#define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
5043#define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d
5044#define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
5045#define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f
5046#define IWM_TX_STATUS_FAIL_FW_DROP 0x90
5047#define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91
5048#define IWM_TX_STATUS_INTERNAL_ABORT 0x92
5049#define IWM_TX_MODE_MSK 0x00000f00
5050#define IWM_TX_MODE_NO_BURST 0x00000000
5051#define IWM_TX_MODE_IN_BURST_SEQ 0x00000100
5052#define IWM_TX_MODE_FIRST_IN_BURST 0x00000200
5053#define IWM_TX_QUEUE_NUM_MSK 0x0001f000
5054#define IWM_TX_NARROW_BW_MSK 0x00060000
5055#define IWM_TX_NARROW_BW_1DIV2 0x00020000
5056#define IWM_TX_NARROW_BW_1DIV4 0x00040000
5057#define IWM_TX_NARROW_BW_1DIV8 0x00060000
4656
4657/*
5058
5059/*
4658 * enum iwm_tx_agg_status - TX aggregation status
4659 * @IWM_AGG_TX_STATE_STATUS_MSK:
4660 * @IWM_AGG_TX_STATE_TRANSMITTED:
4661 * @IWM_AGG_TX_STATE_UNDERRUN:
4662 * @IWM_AGG_TX_STATE_BT_PRIO:
4663 * @IWM_AGG_TX_STATE_FEW_BYTES:
4664 * @IWM_AGG_TX_STATE_ABORT:
4665 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4666 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4667 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4668 * @IWM_AGG_TX_STATE_SCD_QUERY:
4669 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4670 * @IWM_AGG_TX_STATE_RESPONSE:
4671 * @IWM_AGG_TX_STATE_DUMP_TX:
4672 * @IWM_AGG_TX_STATE_DELAY_TX:
5060 * TX aggregation status
4673 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4674 * occur if tx failed for this frame when it was a member of a previous
4675 * aggregation block). If rate scaling is used, retry count indicates the
4676 * rate table entry used for all frames in the new agg.
5061 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
5062 * occur if tx failed for this frame when it was a member of a previous
5063 * aggregation block). If rate scaling is used, retry count indicates the
5064 * rate table entry used for all frames in the new agg.
4677 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4678 * this frame
4679 *
4680 * TODO: complete documentation
4681 */
5065 */
4682enum iwm_tx_agg_status {
4683 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4684 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4685 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4686 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4687 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4688 IWM_AGG_TX_STATE_ABORT = 0x008,
4689 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4690 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4691 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4692 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4693 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4694 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4695 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4696 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4697 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4698 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4699};
5066#define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff
5067#define IWM_AGG_TX_STATE_TRANSMITTED 0x0000
5068#define IWM_AGG_TX_STATE_UNDERRUN 0x0001
5069#define IWM_AGG_TX_STATE_BT_PRIO 0x0002
5070#define IWM_AGG_TX_STATE_FEW_BYTES 0x0004
5071#define IWM_AGG_TX_STATE_ABORT 0x0008
5072#define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010
5073#define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020
5074#define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040
5075#define IWM_AGG_TX_STATE_SCD_QUERY 0x0080
5076#define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100
5077#define IWM_AGG_TX_STATE_RESPONSE 0x01ff
5078#define IWM_AGG_TX_STATE_DUMP_TX 0x0200
5079#define IWM_AGG_TX_STATE_DELAY_TX 0x0400
5080#define IWM_AGG_TX_STATE_TRY_CNT_POS 12
5081#define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS)
4700
4701#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4702 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4703 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4704
4705/*
4706 * The mask below describes a status where we are absolutely sure that the MPDU
4707 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've

--- 23 unchanged lines hidden (view full) ---

4731 * this status.
4732 * This status relates to reasons the tx might have been blocked or aborted
4733 * within the device, rather than whether it was received successfully by
4734 * the destination station.
4735 */
4736
4737/**
4738 * struct iwm_agg_tx_status - per packet TX aggregation status
5082
5083#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
5084 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
5085 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
5086
5087/*
5088 * The mask below describes a status where we are absolutely sure that the MPDU
5089 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've

--- 23 unchanged lines hidden (view full) ---

5113 * this status.
5114 * This status relates to reasons the tx might have been blocked or aborted
5115 * within the device, rather than whether it was received successfully by
5116 * the destination station.
5117 */
5118
5119/**
5120 * struct iwm_agg_tx_status - per packet TX aggregation status
4739 * @status: enum iwm_tx_agg_status
4740 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
5121 * @status: IWM_AGG_TX_STATE_*
5122 * @idx: Tx queue index of this frame
5123 * @qid: Tx queue ID of this frame
4741 */
4742struct iwm_agg_tx_status {
4743 uint16_t status;
5124 */
5125struct iwm_agg_tx_status {
5126 uint16_t status;
5127#if 0
5128 /* OpenBSD update - convert code to use this */
5129 uint8_t idx;
5130 uint8_t qid;
5131#else
4744 uint16_t sequence;
5132 uint16_t sequence;
5133#endif
4745} __packed;
4746
4747/*
4748 * definitions for initial rate index field
4749 * bits [3:0] initial rate index
4750 * bits [6:4] rate table color, used for the initial rate
4751 * bit-7 invalid rate indication
4752 */

--- 17 unchanged lines hidden (view full) ---

4770 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4771 * in usec.
4772 * @pa_status: tx power info
4773 * @pa_integ_res_a: tx power info
4774 * @pa_integ_res_b: tx power info
4775 * @pa_integ_res_c: tx power info
4776 * @measurement_req_id: tx power info
4777 * @tfd_info: TFD information set by the FH
5134} __packed;
5135
5136/*
5137 * definitions for initial rate index field
5138 * bits [3:0] initial rate index
5139 * bits [6:4] rate table color, used for the initial rate
5140 * bit-7 invalid rate indication
5141 */

--- 17 unchanged lines hidden (view full) ---

5159 * for agg: RTS + CTS + aggregation tx time + block-ack time.
5160 * in usec.
5161 * @pa_status: tx power info
5162 * @pa_integ_res_a: tx power info
5163 * @pa_integ_res_b: tx power info
5164 * @pa_integ_res_c: tx power info
5165 * @measurement_req_id: tx power info
5166 * @tfd_info: TFD information set by the FH
4778 * @seq_ctl: sequence control from the Tx cmd
5167 * @seq_ctl: sequence control field from IEEE80211 frame header
4779 * @byte_cnt: byte count from the Tx cmd
4780 * @tlc_info: TLC rate info
4781 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4782 * @frame_ctrl: frame control
4783 * @status: for non-agg: frame status IWM_TX_STATUS_*
4784 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4785 * follow this one, up to frame_count.
4786 *

--- 8 unchanged lines hidden (view full) ---

4795 uint32_t initial_rate;
4796 uint16_t wireless_media_time;
4797
4798 uint8_t pa_status;
4799 uint8_t pa_integ_res_a[3];
4800 uint8_t pa_integ_res_b[3];
4801 uint8_t pa_integ_res_c[3];
4802 uint16_t measurement_req_id;
5168 * @byte_cnt: byte count from the Tx cmd
5169 * @tlc_info: TLC rate info
5170 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
5171 * @frame_ctrl: frame control
5172 * @status: for non-agg: frame status IWM_TX_STATUS_*
5173 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
5174 * follow this one, up to frame_count.
5175 *

--- 8 unchanged lines hidden (view full) ---

5184 uint32_t initial_rate;
5185 uint16_t wireless_media_time;
5186
5187 uint8_t pa_status;
5188 uint8_t pa_integ_res_a[3];
5189 uint8_t pa_integ_res_b[3];
5190 uint8_t pa_integ_res_c[3];
5191 uint16_t measurement_req_id;
4803 uint8_t reduced_tpc;
4804 uint8_t reserved;
5192 uint16_t reserved;
4805
4806 uint32_t tfd_info;
4807 uint16_t seq_ctl;
4808 uint16_t byte_cnt;
4809 uint8_t tlc_info;
4810 uint8_t ra_tid;
4811 uint16_t frame_ctrl;
4812
4813 struct iwm_agg_tx_status status;
4814} __packed; /* IWM_TX_RSP_API_S_VER_3 */
4815
4816/**
4817 * struct iwm_ba_notif - notifies about reception of BA
4818 * ( IWM_BA_NOTIF = 0xc5 )
5193
5194 uint32_t tfd_info;
5195 uint16_t seq_ctl;
5196 uint16_t byte_cnt;
5197 uint8_t tlc_info;
5198 uint8_t ra_tid;
5199 uint16_t frame_ctrl;
5200
5201 struct iwm_agg_tx_status status;
5202} __packed; /* IWM_TX_RSP_API_S_VER_3 */
5203
5204/**
5205 * struct iwm_ba_notif - notifies about reception of BA
5206 * ( IWM_BA_NOTIF = 0xc5 )
4819 * @sta_addr_lo32: lower 32 bits of the MAC address
4820 * @sta_addr_hi16: upper 16 bits of the MAC address
5207 * @sta_addr: MAC address
4821 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4822 * @tid: tid of the session
5208 * @sta_id: Index of recipient (BA-sending) station in fw's station table
5209 * @tid: tid of the session
4823 * @seq_ctl:
5210 * @seq_ctl: sequence control field from IEEE80211 frame header (the first
5211 * bit in @bitmap corresponds to the sequence number stored here)
4824 * @bitmap: the bitmap of the BA notification as seen in the air
4825 * @scd_flow: the tx queue this BA relates to
4826 * @scd_ssn: the index of the last contiguously sent packet
4827 * @txed: number of Txed frames in this batch
4828 * @txed_2_done: number of Acked frames in this batch
5212 * @bitmap: the bitmap of the BA notification as seen in the air
5213 * @scd_flow: the tx queue this BA relates to
5214 * @scd_ssn: the index of the last contiguously sent packet
5215 * @txed: number of Txed frames in this batch
5216 * @txed_2_done: number of Acked frames in this batch
5217 * @reduced_txp: power reduced according to TPC. This is the actual value and
5218 * not a copy from the LQ command. Thus, if not the first rate was used
5219 * for Tx-ing then this value will be set to 0 by FW.
5220 * @reserved1: reserved
4829 */
4830struct iwm_ba_notif {
5221 */
5222struct iwm_ba_notif {
4831 uint32_t sta_addr_lo32;
4832 uint16_t sta_addr_hi16;
5223 uint8_t sta_addr[ETHER_ADDR_LEN];
4833 uint16_t reserved;
4834
4835 uint8_t sta_id;
4836 uint8_t tid;
4837 uint16_t seq_ctl;
4838 uint64_t bitmap;
4839 uint16_t scd_flow;
4840 uint16_t scd_ssn;
4841 uint8_t txed;
4842 uint8_t txed_2_done;
5224 uint16_t reserved;
5225
5226 uint8_t sta_id;
5227 uint8_t tid;
5228 uint16_t seq_ctl;
5229 uint64_t bitmap;
5230 uint16_t scd_flow;
5231 uint16_t scd_ssn;
5232 uint8_t txed;
5233 uint8_t txed_2_done;
4843 uint16_t reserved1;
5234 uint8_t reduced_txp;
5235 uint8_t reserved1;
4844} __packed;
4845
4846/*
4847 * struct iwm_mac_beacon_cmd - beacon template command
4848 * @tx: the tx commands associated with the beacon frame
4849 * @template_id: currently equal to the mac context id of the coresponding
4850 * mac.
4851 * @tim_idx: the offset of the tim IE in the beacon

--- 10 unchanged lines hidden (view full) ---

4862
4863struct iwm_beacon_notif {
4864 struct iwm_tx_resp beacon_notify_hdr;
4865 uint64_t tsf;
4866 uint32_t ibss_mgr_status;
4867} __packed;
4868
4869/**
5236} __packed;
5237
5238/*
5239 * struct iwm_mac_beacon_cmd - beacon template command
5240 * @tx: the tx commands associated with the beacon frame
5241 * @template_id: currently equal to the mac context id of the coresponding
5242 * mac.
5243 * @tim_idx: the offset of the tim IE in the beacon

--- 10 unchanged lines hidden (view full) ---

5254
5255struct iwm_beacon_notif {
5256 struct iwm_tx_resp beacon_notify_hdr;
5257 uint64_t tsf;
5258 uint32_t ibss_mgr_status;
5259} __packed;
5260
5261/**
4870 * enum iwm_dump_control - dump (flush) control flags
5262 * dump (flush) control flags
4871 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4872 * and the TFD queues are empty.
4873 */
5263 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
5264 * and the TFD queues are empty.
5265 */
4874enum iwm_dump_control {
4875 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4876};
5266#define IWM_DUMP_TX_FIFO_FLUSH (1 << 1)
4877
4878/**
4879 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4880 * @queues_ctl: bitmap of queues to flush
4881 * @flush_ctl: control flags
4882 * @reserved: reserved
4883 */
5267
5268/**
5269 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
5270 * @queues_ctl: bitmap of queues to flush
5271 * @flush_ctl: control flags
5272 * @reserved: reserved
5273 */
4884struct iwm_tx_path_flush_cmd {
5274struct iwm_tx_path_flush_cmd_v1 {
4885 uint32_t queues_ctl;
4886 uint16_t flush_ctl;
4887 uint16_t reserved;
4888} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4889
4890/**
5275 uint32_t queues_ctl;
5276 uint16_t flush_ctl;
5277 uint16_t reserved;
5278} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
5279
5280/**
5281 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command
5282 * @sta_id: station ID to flush
5283 * @tid_mask: TID mask to flush
5284 * @reserved: reserved
5285 */
5286struct iwm_tx_path_flush_cmd {
5287 uint32_t sta_id;
5288 uint16_t tid_mask;
5289 uint16_t reserved;
5290} __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */
5291
5292/**
4891 * iwm_get_scd_ssn - returns the SSN of the SCD
4892 * @tx_resp: the Tx response from the fw (agg or non-agg)
4893 *
4894 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4895 * it can't know that everything will go well until the end of the AMPDU, it
4896 * can't know in advance the number of MPDUs that will be sent in the current
4897 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4898 * Hence, it can't know in advance what the SSN of the SCD will be at the end

--- 116 unchanged lines hidden (view full) ---

5015 */
5016struct iwm_scan_req_tx_cmd {
5017 uint32_t tx_flags;
5018 uint32_t rate_n_flags;
5019 uint8_t sta_id;
5020 uint8_t reserved[3];
5021} __packed;
5022
5293 * iwm_get_scd_ssn - returns the SSN of the SCD
5294 * @tx_resp: the Tx response from the fw (agg or non-agg)
5295 *
5296 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
5297 * it can't know that everything will go well until the end of the AMPDU, it
5298 * can't know in advance the number of MPDUs that will be sent in the current
5299 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
5300 * Hence, it can't know in advance what the SSN of the SCD will be at the end

--- 116 unchanged lines hidden (view full) ---

5417 */
5418struct iwm_scan_req_tx_cmd {
5419 uint32_t tx_flags;
5420 uint32_t rate_n_flags;
5421 uint8_t sta_id;
5422 uint8_t reserved[3];
5423} __packed;
5424
5023enum iwm_scan_channel_flags_lmac {
5024 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
5025 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
5026};
5425#define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)
5426#define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)
5027
5028/**
5029 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
5030 * @flags: bits 1-20: directed scan to i'th ssid
5031 * other bits &enum iwm_scan_channel_flags_lmac
5032 * @channel_number: channel number 1-13 etc
5033 * @iter_count: scan iteration on this channel
5034 * @iter_interval: interval in seconds between iterations on one channel

--- 16 unchanged lines hidden (view full) ---

5051} __packed;
5052
5053/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
5054 * @mac_header: first (and common) part of the probe
5055 * @band_data: band specific data
5056 * @common_data: last (and common) part of the probe
5057 * @buf: raw data block
5058 */
5427
5428/**
5429 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
5430 * @flags: bits 1-20: directed scan to i'th ssid
5431 * other bits &enum iwm_scan_channel_flags_lmac
5432 * @channel_number: channel number 1-13 etc
5433 * @iter_count: scan iteration on this channel
5434 * @iter_interval: interval in seconds between iterations on one channel

--- 16 unchanged lines hidden (view full) ---

5451} __packed;
5452
5453/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
5454 * @mac_header: first (and common) part of the probe
5455 * @band_data: band specific data
5456 * @common_data: last (and common) part of the probe
5457 * @buf: raw data block
5458 */
5059struct iwm_scan_probe_req {
5459struct iwm_scan_probe_req_v1 {
5060 struct iwm_scan_probe_segment mac_header;
5061 struct iwm_scan_probe_segment band_data[2];
5062 struct iwm_scan_probe_segment common_data;
5063 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
5064} __packed;
5065
5460 struct iwm_scan_probe_segment mac_header;
5461 struct iwm_scan_probe_segment band_data[2];
5462 struct iwm_scan_probe_segment common_data;
5463 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
5464} __packed;
5465
5066enum iwm_scan_channel_flags {
5067 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
5068 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
5069 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
5070};
5466/* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2
5467 * @mac_header: first (and common) part of the probe
5468 * @band_data: band specific data
5469 * @common_data: last (and common) part of the probe
5470 * @buf: raw data block
5471 */
5472struct iwm_scan_probe_req {
5473 struct iwm_scan_probe_segment mac_header;
5474 struct iwm_scan_probe_segment band_data[3];
5475 struct iwm_scan_probe_segment common_data;
5476 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
5477} __packed;
5071
5478
5479
5480#define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0)
5481#define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)
5482#define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)
5483
5072/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
5073 * @flags: enum iwm_scan_channel_flags
5074 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
5075 * involved.
5076 * 1 - EBS is disabled.
5077 * 2 - every second scan will be full scan(and so on).
5078 */
5079struct iwm_scan_channel_opt {
5080 uint16_t flags;
5081 uint16_t non_ebs_ratio;
5082} __packed;
5083
5084/**
5484/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
5485 * @flags: enum iwm_scan_channel_flags
5486 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
5487 * involved.
5488 * 1 - EBS is disabled.
5489 * 2 - every second scan will be full scan(and so on).
5490 */
5491struct iwm_scan_channel_opt {
5492 uint16_t flags;
5493 uint16_t non_ebs_ratio;
5494} __packed;
5495
5496/**
5085 * iwm_lmac_scan_flags
5497 * LMAC scan flags
5086 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
5087 * without filtering.
5088 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
5089 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
5090 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
5091 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
5092 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
5093 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
5094 * and DS parameter set IEs into probe requests.
5095 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
5096 * 1, 6 and 11.
5097 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
5098 */
5498 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
5499 * without filtering.
5500 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
5501 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
5502 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
5503 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
5504 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
5505 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
5506 * and DS parameter set IEs into probe requests.
5507 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
5508 * 1, 6 and 11.
5509 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
5510 */
5099enum iwm_lmac_scan_flags {
5100 IWM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
5101 IWM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
5102 IWM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
5103 IWM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
5104 IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
5105 IWM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
5106 IWM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
5107 IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
5108 IWM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
5109};
5511#define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0)
5512#define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1)
5513#define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2)
5514#define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3)
5515#define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4)
5516#define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5)
5517#define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6)
5518#define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7)
5519#define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9)
5110
5520
5111enum iwm_scan_priority {
5112 IWM_SCAN_PRIORITY_LOW,
5113 IWM_SCAN_PRIORITY_MEDIUM,
5114 IWM_SCAN_PRIORITY_HIGH,
5115};
5521#define IWM_SCAN_PRIORITY_LOW 0
5522#define IWM_SCAN_PRIORITY_MEDIUM 1
5523#define IWM_SCAN_PRIORITY_HIGH 2
5116
5117/**
5118 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
5119 * @reserved1: for alignment and future use
5120 * @channel_num: num of channels to scan
5121 * @active-dwell: dwell time for active channels
5122 * @passive-dwell: dwell time for passive channels
5123 * @fragmented-dwell: dwell time for fragmented passive scan

--- 71 unchanged lines hidden (view full) ---

5195struct iwm_scan_results_notif {
5196 uint8_t channel;
5197 uint8_t band;
5198 uint8_t probe_status;
5199 uint8_t num_probe_not_sent;
5200 uint32_t duration;
5201} __packed;
5202
5524
5525/**
5526 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
5527 * @reserved1: for alignment and future use
5528 * @channel_num: num of channels to scan
5529 * @active-dwell: dwell time for active channels
5530 * @passive-dwell: dwell time for passive channels
5531 * @fragmented-dwell: dwell time for fragmented passive scan

--- 71 unchanged lines hidden (view full) ---

5603struct iwm_scan_results_notif {
5604 uint8_t channel;
5605 uint8_t band;
5606 uint8_t probe_status;
5607 uint8_t num_probe_not_sent;
5608 uint32_t duration;
5609} __packed;
5610
5203enum iwm_scan_framework_client {
5204 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
5205 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
5206 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
5207};
5611#define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0)
5612#define IWM_SCAN_CLIENT_NETDETECT (1 << 1)
5613#define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2)
5208
5209/**
5210 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5211 * @ssid: MAC address to filter out
5212 * @reported_rssi: AP rssi reported to the host
5213 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5214 */
5215struct iwm_scan_offload_blacklist {
5614
5615/**
5616 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5617 * @ssid: MAC address to filter out
5618 * @reported_rssi: AP rssi reported to the host
5619 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5620 */
5621struct iwm_scan_offload_blacklist {
5216 uint8_t ssid[IEEE80211_ADDR_LEN];
5622 uint8_t ssid[ETHER_ADDR_LEN];
5217 uint8_t reported_rssi;
5218 uint8_t client_bitmap;
5219} __packed;
5220
5623 uint8_t reported_rssi;
5624 uint8_t client_bitmap;
5625} __packed;
5626
5221enum iwm_scan_offload_network_type {
5222 IWM_NETWORK_TYPE_BSS = 1,
5223 IWM_NETWORK_TYPE_IBSS = 2,
5224 IWM_NETWORK_TYPE_ANY = 3,
5225};
5627#define IWM_NETWORK_TYPE_BSS 1
5628#define IWM_NETWORK_TYPE_IBSS 2
5629#define IWM_NETWORK_TYPE_ANY 3
5226
5630
5227enum iwm_scan_offload_band_selection {
5228 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
5229 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
5230 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
5231};
5631#define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4
5632#define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8
5633#define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc
5232
5233/**
5234 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5235 * @ssid_index: index to ssid list in fixed part
5236 * @unicast_cipher: encryption olgorithm to match - bitmap
5237 * @aut_alg: authentication olgorithm to match - bitmap
5238 * @network_type: enum iwm_scan_offload_network_type
5239 * @band_selection: enum iwm_scan_offload_band_selection

--- 60 unchanged lines hidden (view full) ---

5300 uint8_t bt_status;
5301 uint8_t last_channel;
5302 uint32_t tsf_low;
5303 uint32_t tsf_high;
5304 struct iwm_scan_results_notif results[];
5305} __packed;
5306
5307
5634
5635/**
5636 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5637 * @ssid_index: index to ssid list in fixed part
5638 * @unicast_cipher: encryption olgorithm to match - bitmap
5639 * @aut_alg: authentication olgorithm to match - bitmap
5640 * @network_type: enum iwm_scan_offload_network_type
5641 * @band_selection: enum iwm_scan_offload_band_selection

--- 60 unchanged lines hidden (view full) ---

5702 uint8_t bt_status;
5703 uint8_t last_channel;
5704 uint32_t tsf_low;
5705 uint32_t tsf_high;
5706 struct iwm_scan_results_notif results[];
5707} __packed;
5708
5709
5308/*
5309 * END mvm/fw-api-scan.h
5310 */
5311
5312/*
5313 * BEGIN mvm/fw-api-sta.h
5314 */
5315
5316/* UMAC Scan API */
5317
5318/* The maximum of either of these cannot exceed 8, because we use an
5319 * 8-bit mask (see IWM_SCAN_MASK).
5320 */
5321#define IWM_MAX_UMAC_SCANS 8
5322#define IWM_MAX_LMAC_SCANS 1
5323
5710/* UMAC Scan API */
5711
5712/* The maximum of either of these cannot exceed 8, because we use an
5713 * 8-bit mask (see IWM_SCAN_MASK).
5714 */
5715#define IWM_MAX_UMAC_SCANS 8
5716#define IWM_MAX_LMAC_SCANS 1
5717
5324enum iwm_scan_config_flags {
5325 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5326 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5327 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5328 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5329 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5330 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5331 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5332 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5333 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5334 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5335 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5336 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5337 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5338 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5339 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5340 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5341 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5342 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5718#define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)
5719#define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)
5720#define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)
5721#define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)
5722#define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)
5723#define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)
5724#define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)
5725#define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)
5726#define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)
5727#define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)
5728#define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)
5729#define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)
5730#define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)
5731#define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)
5732#define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)
5733#define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)
5734#define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)
5735#define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)
5343
5736
5344 /* Bits 26-31 are for num of channels in channel_array */
5737/* Bits 26-31 are for num of channels in channel_array */
5345#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5738#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5346};
5347
5739
5348enum iwm_scan_config_rates {
5349 /* OFDM basic rates */
5350 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5351 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5352 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5353 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5354 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5355 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5356 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5357 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5358 /* CCK basic rates */
5359 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5360 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5361 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5362 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5740/* OFDM basic rates */
5741#define IWM_SCAN_CONFIG_RATE_6M (1 << 0)
5742#define IWM_SCAN_CONFIG_RATE_9M (1 << 1)
5743#define IWM_SCAN_CONFIG_RATE_12M (1 << 2)
5744#define IWM_SCAN_CONFIG_RATE_18M (1 << 3)
5745#define IWM_SCAN_CONFIG_RATE_24M (1 << 4)
5746#define IWM_SCAN_CONFIG_RATE_36M (1 << 5)
5747#define IWM_SCAN_CONFIG_RATE_48M (1 << 6)
5748#define IWM_SCAN_CONFIG_RATE_54M (1 << 7)
5749/* CCK basic rates */
5750#define IWM_SCAN_CONFIG_RATE_1M (1 << 8)
5751#define IWM_SCAN_CONFIG_RATE_2M (1 << 9)
5752#define IWM_SCAN_CONFIG_RATE_5M (1 << 10)
5753#define IWM_SCAN_CONFIG_RATE_11M (1 << 11)
5363
5754
5364 /* Bits 16-27 are for supported rates */
5755/* Bits 16-27 are for supported rates */
5365#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5756#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5366};
5367
5757
5368enum iwm_channel_flags {
5369 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5370 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5371 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5372 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5373};
5758#define IWM_CHANNEL_FLAG_EBS (1 << 0)
5759#define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)
5760#define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2)
5761#define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)
5374
5375/**
5376 * struct iwm_scan_config
5377 * @flags: enum scan_config_flags
5378 * @tx_chains: valid_tx antenna - ANT_* definitions
5379 * @rx_chains: valid_rx antenna - ANT_* definitions
5380 * @legacy_rates: default legacy rates - enum scan_config_rates
5381 * @out_of_channel_time: default max out of serving channel time

--- 14 unchanged lines hidden (view full) ---

5396 uint32_t rx_chains;
5397 uint32_t legacy_rates;
5398 uint32_t out_of_channel_time;
5399 uint32_t suspend_time;
5400 uint8_t dwell_active;
5401 uint8_t dwell_passive;
5402 uint8_t dwell_fragmented;
5403 uint8_t dwell_extended;
5762
5763/**
5764 * struct iwm_scan_config
5765 * @flags: enum scan_config_flags
5766 * @tx_chains: valid_tx antenna - ANT_* definitions
5767 * @rx_chains: valid_rx antenna - ANT_* definitions
5768 * @legacy_rates: default legacy rates - enum scan_config_rates
5769 * @out_of_channel_time: default max out of serving channel time

--- 14 unchanged lines hidden (view full) ---

5784 uint32_t rx_chains;
5785 uint32_t legacy_rates;
5786 uint32_t out_of_channel_time;
5787 uint32_t suspend_time;
5788 uint8_t dwell_active;
5789 uint8_t dwell_passive;
5790 uint8_t dwell_fragmented;
5791 uint8_t dwell_extended;
5404 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5792 uint8_t mac_addr[ETHER_ADDR_LEN];
5405 uint8_t bcast_sta_id;
5406 uint8_t channel_flags;
5407 uint8_t channel_array[];
5408} __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5409
5410/**
5411 * iwm_umac_scan_flags
5412 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5413 * can be preempted by other scan requests with higher priority.
5414 * The low priority scan will be resumed when the higher proirity scan is
5415 * completed.
5416 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5417 * when scan starts.
5418 */
5793 uint8_t bcast_sta_id;
5794 uint8_t channel_flags;
5795 uint8_t channel_array[];
5796} __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5797
5798/**
5799 * iwm_umac_scan_flags
5800 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5801 * can be preempted by other scan requests with higher priority.
5802 * The low priority scan will be resumed when the higher proirity scan is
5803 * completed.
5804 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5805 * when scan starts.
5806 */
5419enum iwm_umac_scan_flags {
5420 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5421 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5422};
5807#define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)
5808#define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)
5423
5809
5424enum iwm_umac_scan_uid_offsets {
5425 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5426 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5427};
5810#define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0
5811#define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8
5428
5812
5429enum iwm_umac_scan_general_flags {
5430 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5431 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5432 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5433 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5434 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5435 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5436 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5437 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5438 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5439 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5440 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5441};
5813#define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)
5814#define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)
5815#define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)
5816#define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)
5817#define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)
5818#define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)
5819#define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)
5820#define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)
5821#define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)
5822#define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)
5823#define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)
5824/* Extended dwell is obselete when adaptive dwell is used, making this
5825 * bit reusable. Hence, probe request defer is used only when adaptive
5826 * dwell is supported. */
5827#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10)
5828#define IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11)
5829#define IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13)
5830#define IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14)
5831#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15)
5442
5443/**
5832
5833/**
5834 * UMAC scan general flags #2
5835 * @IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete
5836 * notification per channel or not.
5837 * @IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel
5838 * reorder optimization or not.
5839 */
5840#define IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)
5841#define IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1)
5842
5843/**
5444 * struct iwm_scan_channel_cfg_umac
5445 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5446 * @channel_num: channel number 1-13 etc.
5447 * @iter_count: repetition count for the channel.
5448 * @iter_interval: interval between two scan iterations on one channel.
5449 */
5450struct iwm_scan_channel_cfg_umac {
5451 uint32_t flags;
5844 * struct iwm_scan_channel_cfg_umac
5845 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5846 * @channel_num: channel number 1-13 etc.
5847 * @iter_count: repetition count for the channel.
5848 * @iter_interval: interval between two scan iterations on one channel.
5849 */
5850struct iwm_scan_channel_cfg_umac {
5851 uint32_t flags;
5452#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5453
5852#define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5454 uint8_t channel_num;
5455 uint8_t iter_count;
5456 uint16_t iter_interval;
5853 uint8_t channel_num;
5854 uint8_t iter_count;
5855 uint16_t iter_interval;
5457} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5856} __packed; /* SCAN_CHANNEL_CFG_S_VER1 */
5458
5459/**
5460 * struct iwm_scan_umac_schedule
5461 * @interval: interval in seconds between scan iterations
5462 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5463 * @reserved: for alignment and future use
5464 */
5465struct iwm_scan_umac_schedule {

--- 6 unchanged lines hidden (view full) ---

5472 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5473 * parameters following channels configuration array.
5474 * @schedule: two scheduling plans.
5475 * @delay: delay in TUs before starting the first scan iteration
5476 * @reserved: for future use and alignment
5477 * @preq: probe request with IEs blocks
5478 * @direct_scan: list of SSIDs for directed active scan
5479 */
5857
5858/**
5859 * struct iwm_scan_umac_schedule
5860 * @interval: interval in seconds between scan iterations
5861 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5862 * @reserved: for alignment and future use
5863 */
5864struct iwm_scan_umac_schedule {

--- 6 unchanged lines hidden (view full) ---

5871 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5872 * parameters following channels configuration array.
5873 * @schedule: two scheduling plans.
5874 * @delay: delay in TUs before starting the first scan iteration
5875 * @reserved: for future use and alignment
5876 * @preq: probe request with IEs blocks
5877 * @direct_scan: list of SSIDs for directed active scan
5878 */
5480struct iwm_scan_req_umac_tail {
5879struct iwm_scan_req_umac_tail_v1 {
5481 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5482 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5483 uint16_t delay;
5484 uint16_t reserved;
5485 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5880 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5881 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5882 uint16_t delay;
5883 uint16_t reserved;
5884 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5885 struct iwm_scan_probe_req_v1 preq;
5886 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5887} __packed;
5888
5889/**
5890 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5891 * parameters following channels configuration array.
5892 * @schedule: two scheduling plans.
5893 * @delay: delay in TUs before starting the first scan iteration
5894 * @reserved: for future use and alignment
5895 * @preq: probe request with IEs blocks
5896 * @direct_scan: list of SSIDs for directed active scan
5897 */
5898struct iwm_scan_req_umac_tail_v2 {
5899 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5900 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5901 uint16_t delay;
5902 uint16_t reserved;
5903 /* SCAN_PROBE_PARAMS_API_S_VER_2 */
5486 struct iwm_scan_probe_req preq;
5487 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5488} __packed;
5489
5490/**
5904 struct iwm_scan_probe_req preq;
5905 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5906} __packed;
5907
5908/**
5491 * struct iwm_scan_uma_chan_param
5492 * @flags: channel flags &enum iwm_scan_channel_flags
5909 * struct iwm_scan_umac_chan_param
5910 * @flags: channel flags &enum iwl_scan_channel_flags
5493 * @count: num of channels in scan request
5494 * @reserved: for future use and alignment
5495 */
5496struct iwm_scan_umac_chan_param {
5497 uint8_t flags;
5498 uint8_t count;
5499 uint16_t reserved;
5911 * @count: num of channels in scan request
5912 * @reserved: for future use and alignment
5913 */
5914struct iwm_scan_umac_chan_param {
5915 uint8_t flags;
5916 uint8_t count;
5917 uint16_t reserved;
5500} __packed;
5918} __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5501
5919
5920#define IWM_SCAN_LB_LMAC_IDX 0
5921#define IWM_SCAN_HB_LMAC_IDX 1
5922
5502/**
5503 * struct iwm_scan_req_umac
5923/**
5924 * struct iwm_scan_req_umac
5504 * @flags: &enum iwm_umac_scan_flags
5505 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5506 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5507 * @general_flags: &enum iwm_umac_scan_general_flags
5925 * @flags: &enum iwl_umac_scan_flags
5926 * @uid: scan id, &enum iwl_umac_scan_uid_offsets
5927 * @ooc_priority: out of channel priority - &enum iwl_scan_priority
5928 * @general_flags: &enum iwl_umac_scan_general_flags
5508 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
5509 * @extended_dwell: dwell time for channels 1, 6 and 11
5510 * @active_dwell: dwell time for active scan per LMAC
5511 * @passive_dwell: dwell time for passive scan per LMAC
5512 * @fragmented_dwell: dwell time for fragmented passive scan
5513 * @adwell_default_n_aps: for adaptive dwell the default number of APs
5514 * per channel
5515 * @adwell_default_n_aps_social: for adaptive dwell the default
5516 * number of APs per social (1,6,11) channel
5517 * @general_flags2: &enum iwl_umac_scan_general_flags2
5518 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added
5519 * to total scan time
5520 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
5929 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
5930 * @extended_dwell: dwell time for channels 1, 6 and 11
5931 * @active_dwell: dwell time for active scan per LMAC
5932 * @passive_dwell: dwell time for passive scan per LMAC
5933 * @fragmented_dwell: dwell time for fragmented passive scan
5934 * @adwell_default_n_aps: for adaptive dwell the default number of APs
5935 * per channel
5936 * @adwell_default_n_aps_social: for adaptive dwell the default
5937 * number of APs per social (1,6,11) channel
5938 * @general_flags2: &enum iwl_umac_scan_general_flags2
5939 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added
5940 * to total scan time
5941 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
5521 * are 2 LMACs
5942 * are 2 LMACs (high band and low band)
5522 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
5523 * @scan_priority: scan internal prioritization &enum iwl_scan_priority
5524 * @num_of_fragments: Number of fragments needed for full coverage per band.
5525 * Relevant only for fragmented scan.
5943 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
5944 * @scan_priority: scan internal prioritization &enum iwl_scan_priority
5945 * @num_of_fragments: Number of fragments needed for full coverage per band.
5946 * Relevant only for fragmented scan.
5526 * @channel: &struct iwl_scan_umac_chan_param
5947 * @channel: &struct iwm_scan_umac_chan_param
5527 * @reserved: for future use and alignment
5528 * @reserved3: for future use and alignment
5529 * @data: &struct iwm_scan_channel_cfg_umac and
5530 * &struct iwm_scan_req_umac_tail
5531 */
5532struct iwm_scan_req_umac {
5533 uint32_t flags;
5534 uint32_t uid;
5535 uint32_t ooc_priority;
5948 * @reserved: for future use and alignment
5949 * @reserved3: for future use and alignment
5950 * @data: &struct iwm_scan_channel_cfg_umac and
5951 * &struct iwm_scan_req_umac_tail
5952 */
5953struct iwm_scan_req_umac {
5954 uint32_t flags;
5955 uint32_t uid;
5956 uint32_t ooc_priority;
5957 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5536 uint16_t general_flags;
5537 uint8_t reserved;
5538 uint8_t scan_start_mac_id;
5539 union {
5540 struct {
5541 uint8_t extended_dwell;
5542 uint8_t active_dwell;
5543 uint8_t passive_dwell;
5544 uint8_t fragmented_dwell;
5545 uint32_t max_out_time;
5546 uint32_t suspend_time;
5547 uint32_t scan_priority;
5548 struct iwm_scan_umac_chan_param channel;
5549 uint8_t data[];
5958 uint16_t general_flags;
5959 uint8_t reserved;
5960 uint8_t scan_start_mac_id;
5961 union {
5962 struct {
5963 uint8_t extended_dwell;
5964 uint8_t active_dwell;
5965 uint8_t passive_dwell;
5966 uint8_t fragmented_dwell;
5967 uint32_t max_out_time;
5968 uint32_t suspend_time;
5969 uint32_t scan_priority;
5970 struct iwm_scan_umac_chan_param channel;
5971 uint8_t data[];
5550 } v1;
5972 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5551 struct {
5973 struct {
5974 uint8_t extended_dwell;
5552 uint8_t active_dwell;
5553 uint8_t passive_dwell;
5554 uint8_t fragmented_dwell;
5975 uint8_t active_dwell;
5976 uint8_t passive_dwell;
5977 uint8_t fragmented_dwell;
5978 uint32_t max_out_time[2];
5979 uint32_t suspend_time[2];
5980 uint32_t scan_priority;
5981 struct iwm_scan_umac_chan_param channel;
5982 uint8_t data[];
5983 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */
5984 struct {
5985 uint8_t active_dwell;
5986 uint8_t passive_dwell;
5987 uint8_t fragmented_dwell;
5555 uint8_t adwell_default_n_aps;
5556 uint8_t adwell_default_n_aps_social;
5557 uint8_t reserved3;
5558 uint16_t adwell_max_budget;
5559 uint32_t max_out_time[2];
5560 uint32_t suspend_time[2];
5561 uint32_t scan_priority;
5562 struct iwm_scan_umac_chan_param channel;
5563 uint8_t data[];
5988 uint8_t adwell_default_n_aps;
5989 uint8_t adwell_default_n_aps_social;
5990 uint8_t reserved3;
5991 uint16_t adwell_max_budget;
5992 uint32_t max_out_time[2];
5993 uint32_t suspend_time[2];
5994 uint32_t scan_priority;
5995 struct iwm_scan_umac_chan_param channel;
5996 uint8_t data[];
5564 } v7;
5997 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */
5998 struct {
5999 uint8_t active_dwell[2];
6000 uint8_t reserved2;
6001 uint8_t adwell_default_n_aps;
6002 uint8_t adwell_default_n_aps_social;
6003 uint8_t general_flags2;
6004 uint16_t adwell_max_budget;
6005 uint32_t max_out_time[2];
6006 uint32_t suspend_time[2];
6007 uint32_t scan_priority;
6008 uint8_t passive_dwell[2];
6009 uint8_t num_of_fragments[2];
6010 struct iwm_scan_umac_chan_param channel;
6011 uint8_t data[];
6012 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */
6013 struct {
6014 uint8_t active_dwell[2];
6015 uint8_t adwell_default_hb_n_aps;
6016 uint8_t adwell_default_lb_n_aps;
6017 uint8_t adwell_default_n_aps_social;
6018 uint8_t general_flags2;
6019 uint16_t adwell_max_budget;
6020 uint32_t max_out_time[2];
6021 uint32_t suspend_time[2];
6022 uint32_t scan_priority;
6023 uint8_t passive_dwell[2];
6024 uint8_t num_of_fragments[2];
6025 struct iwm_scan_umac_chan_param channel;
6026 uint8_t data[];
6027 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */
5565 };
5566} __packed;
5567
6028 };
6029} __packed;
6030
6031#define IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac)
5568#define IWM_SCAN_REQ_UMAC_SIZE_V7 48
6032#define IWM_SCAN_REQ_UMAC_SIZE_V7 48
6033#define IWM_SCAN_REQ_UMAC_SIZE_V6 44
5569#define IWM_SCAN_REQ_UMAC_SIZE_V1 36
5570
5571/**
5572 * struct iwm_umac_scan_abort
5573 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5574 * @flags: reserved
5575 */
5576struct iwm_umac_scan_abort {

--- 27 unchanged lines hidden (view full) ---

5604 * @bssid: matched bssid
5605 * @channel: channel where the match occurred
5606 * @energy:
5607 * @matching_feature:
5608 * @matching_channels: bitmap of channels that matched, referencing
5609 * the channels passed in tue scan offload request
5610 */
5611struct iwm_scan_offload_profile_match {
6034#define IWM_SCAN_REQ_UMAC_SIZE_V1 36
6035
6036/**
6037 * struct iwm_umac_scan_abort
6038 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
6039 * @flags: reserved
6040 */
6041struct iwm_umac_scan_abort {

--- 27 unchanged lines hidden (view full) ---

6069 * @bssid: matched bssid
6070 * @channel: channel where the match occurred
6071 * @energy:
6072 * @matching_feature:
6073 * @matching_channels: bitmap of channels that matched, referencing
6074 * the channels passed in tue scan offload request
6075 */
6076struct iwm_scan_offload_profile_match {
5612 uint8_t bssid[IEEE80211_ADDR_LEN];
6077 uint8_t bssid[ETHER_ADDR_LEN];
5613 uint16_t reserved;
5614 uint8_t channel;
5615 uint8_t energy;
5616 uint8_t matching_feature;
5617 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5618} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5619
5620/**

--- 39 unchanged lines hidden (view full) ---

5660 uint8_t status;
5661 uint8_t bt_status;
5662 uint8_t last_channel;
5663 uint32_t tsf_low;
5664 uint32_t tsf_high;
5665 struct iwm_scan_results_notif results[];
5666} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5667
6078 uint16_t reserved;
6079 uint8_t channel;
6080 uint8_t energy;
6081 uint8_t matching_feature;
6082 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
6083} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
6084
6085/**

--- 39 unchanged lines hidden (view full) ---

6125 uint8_t status;
6126 uint8_t bt_status;
6127 uint8_t last_channel;
6128 uint32_t tsf_low;
6129 uint32_t tsf_high;
6130 struct iwm_scan_results_notif results[];
6131} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
6132
5668/* Please keep this enum *SORTED* by hex value.
5669 * Needed for binary search, otherwise a warning will be triggered.
6133#define IWM_GSCAN_START_CMD 0x0
6134#define IWM_GSCAN_STOP_CMD 0x1
6135#define IWM_GSCAN_SET_HOTLIST_CMD 0x2
6136#define IWM_GSCAN_RESET_HOTLIST_CMD 0x3
6137#define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4
6138#define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5
6139#define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD
6140#define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE
6141#define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF
6142
6143/*
6144 * END mvm/fw-api-scan.h
5670 */
6145 */
5671enum iwm_scan_subcmd_ids {
5672 IWM_GSCAN_START_CMD = 0x0,
5673 IWM_GSCAN_STOP_CMD = 0x1,
5674 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5675 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5676 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5677 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5678 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5679 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5680 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5681};
5682
6146
6147/*
6148 * BEGIN mvm/fw-api-sta.h
6149 */
6150
5683/* STA API */
5684
5685/**
6151/* STA API */
6152
6153/**
5686 * enum iwm_sta_flags - flags for the ADD_STA host command
6154 * flags for the ADD_STA host command
5687 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5688 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5689 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5690 * @IWM_STA_FLG_PS: set if STA is in Power Save
5691 * @IWM_STA_FLG_INVALID: set if STA is invalid
5692 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5693 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5694 * @IWM_STA_FLG_DRAIN_FLOW: drain flow

--- 6 unchanged lines hidden (view full) ---

5701 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5702 * initialised by driver and can be updated by fw upon reception of
5703 * action frames that can change the channel width. When cleared the fw
5704 * will send all the frames in 20MHz even when FAT channel is requested.
5705 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5706 * driver and can be updated by fw upon reception of action frames.
5707 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5708 */
6155 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
6156 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
6157 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
6158 * @IWM_STA_FLG_PS: set if STA is in Power Save
6159 * @IWM_STA_FLG_INVALID: set if STA is invalid
6160 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
6161 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
6162 * @IWM_STA_FLG_DRAIN_FLOW: drain flow

--- 6 unchanged lines hidden (view full) ---

6169 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
6170 * initialised by driver and can be updated by fw upon reception of
6171 * action frames that can change the channel width. When cleared the fw
6172 * will send all the frames in 20MHz even when FAT channel is requested.
6173 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
6174 * driver and can be updated by fw upon reception of action frames.
6175 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
6176 */
5709enum iwm_sta_flags {
5710 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5711 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
6177#define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)
6178#define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)
5712
6179
5713 IWM_STA_FLG_DISABLE_TX = (1 << 4),
6180#define IWM_STA_FLG_DISABLE_TX (1 << 4)
5714
6181
5715 IWM_STA_FLG_PS = (1 << 8),
5716 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5717 IWM_STA_FLG_PAN = (1 << 13),
5718 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5719 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5720 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
6182#define IWM_STA_FLG_PS (1 << 8)
6183#define IWM_STA_FLG_DRAIN_FLOW (1 << 12)
6184#define IWM_STA_FLG_PAN (1 << 13)
6185#define IWM_STA_FLG_CLASS_AUTH (1 << 14)
6186#define IWM_STA_FLG_CLASS_ASSOC (1 << 15)
6187#define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17)
5721
6188
5722 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5723 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5724 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5725 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5726 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5727 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5728 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5729 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5730 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5731 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
6189#define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19
6190#define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6191#define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6192#define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6193#define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6194#define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6195#define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6196#define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6197#define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6198#define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
5732
6199
5733 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5734 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5735 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5736 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5737 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5738 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
6200#define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23
6201#define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
6202#define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
6203#define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
6204#define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
6205#define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)
5739
6206
5740 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5741 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5742 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5743 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5744 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
6207#define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26)
6208#define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26)
6209#define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26)
6210#define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26)
6211#define IWM_STA_FLG_FAT_EN_MSK (3 << 26)
5745
6212
5746 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5747 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5748 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5749 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5750};
6213#define IWM_STA_FLG_MIMO_EN_SISO (0 << 28)
6214#define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28)
6215#define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28)
6216#define IWM_STA_FLG_MIMO_EN_MSK (3 << 28)
5751
5752/**
6217
6218/**
5753 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
6219 * key flags for the ADD_STA host command
5754 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5755 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5756 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5757 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5758 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5759 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5760 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5761 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5762 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5763 * station info array (1 - n 1X mode)
5764 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5765 * @IWM_STA_KEY_NOT_VALID: key is invalid
5766 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
6220 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
6221 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
6222 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
6223 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
6224 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
6225 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
6226 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
6227 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
6228 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
6229 * station info array (1 - n 1X mode)
6230 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
6231 * @IWM_STA_KEY_NOT_VALID: key is invalid
6232 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5767 * @IWM_STA_KEY_MULTICAST: set for multical key
6233 * @IWM_STA_KEY_MULTICAST: set for multicast key
5768 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5769 */
6234 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
6235 */
5770enum iwm_sta_key_flag {
5771 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5772 IWM_STA_KEY_FLG_WEP = (1 << 0),
5773 IWM_STA_KEY_FLG_CCM = (2 << 0),
5774 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5775 IWM_STA_KEY_FLG_EXT = (4 << 0),
5776 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5777 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5778 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
6236#define IWM_STA_KEY_FLG_NO_ENC (0 << 0)
6237#define IWM_STA_KEY_FLG_WEP (1 << 0)
6238#define IWM_STA_KEY_FLG_CCM (2 << 0)
6239#define IWM_STA_KEY_FLG_TKIP (3 << 0)
6240#define IWM_STA_KEY_FLG_EXT (4 << 0)
6241#define IWM_STA_KEY_FLG_CMAC (6 << 0)
6242#define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)
6243#define IWM_STA_KEY_FLG_EN_MSK (7 << 0)
6244#define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)
6245#define IWM_STA_KEY_FLG_KEYID_POS 8
6246#define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS)
6247#define IWM_STA_KEY_NOT_VALID (1 << 11)
6248#define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12)
6249#define IWM_STA_KEY_MULTICAST (1 << 14)
6250#define IWM_STA_KEY_MFP (1 << 15)
5779
6251
5780 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5781 IWM_STA_KEY_FLG_KEYID_POS = 8,
5782 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5783 IWM_STA_KEY_NOT_VALID = (1 << 11),
5784 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5785 IWM_STA_KEY_MULTICAST = (1 << 14),
5786 IWM_STA_KEY_MFP = (1 << 15),
5787};
5788
5789/**
6252/**
5790 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
6253 * indicate to the fw what flag are being changed
5791 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5792 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5793 * @IWM_STA_MODIFY_TX_RATE: unused
5794 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5795 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5796 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5797 * @IWM_STA_MODIFY_PROT_TH:
5798 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5799 */
6254 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
6255 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
6256 * @IWM_STA_MODIFY_TX_RATE: unused
6257 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
6258 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
6259 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
6260 * @IWM_STA_MODIFY_PROT_TH:
6261 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
6262 */
5800enum iwm_sta_modify_flag {
5801 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5802 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5803 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5804 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5805 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5806 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5807 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5808 IWM_STA_MODIFY_QUEUES = (1 << 7),
5809};
6263#define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0)
6264#define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1)
6265#define IWM_STA_MODIFY_TX_RATE (1 << 2)
6266#define IWM_STA_MODIFY_ADD_BA_TID (1 << 3)
6267#define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4)
6268#define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)
6269#define IWM_STA_MODIFY_PROT_TH (1 << 6)
6270#define IWM_STA_MODIFY_QUEUES (1 << 7)
5810
5811#define IWM_STA_MODE_MODIFY 1
5812
5813/**
6271
6272#define IWM_STA_MODE_MODIFY 1
6273
6274/**
5814 * enum iwm_sta_sleep_flag - type of sleep of the station
6275 * type of sleep of the station
5815 * @IWM_STA_SLEEP_STATE_AWAKE:
5816 * @IWM_STA_SLEEP_STATE_PS_POLL:
5817 * @IWM_STA_SLEEP_STATE_UAPSD:
5818 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5819 * (last) released frame
5820 */
6276 * @IWM_STA_SLEEP_STATE_AWAKE:
6277 * @IWM_STA_SLEEP_STATE_PS_POLL:
6278 * @IWM_STA_SLEEP_STATE_UAPSD:
6279 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
6280 * (last) released frame
6281 */
5821enum iwm_sta_sleep_flag {
5822 IWM_STA_SLEEP_STATE_AWAKE = 0,
5823 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5824 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5825 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5826};
6282#define IWM_STA_SLEEP_STATE_AWAKE 0
6283#define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0)
6284#define IWM_STA_SLEEP_STATE_UAPSD (1 << 1)
6285#define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2)
5827
5828/* STA ID and color bits definitions */
5829#define IWM_STA_ID_SEED (0x0f)
5830#define IWM_STA_ID_POS (0)
5831#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5832
5833#define IWM_STA_COLOR_SEED (0x7)
5834#define IWM_STA_COLOR_POS (4)

--- 36 unchanged lines hidden (view full) ---

5871} __packed;
5872
5873#define IWM_ADD_STA_STATUS_MASK 0xFF
5874#define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5875#define IWM_ADD_STA_BAID_MASK 0x7F00
5876#define IWM_ADD_STA_BAID_SHIFT 8
5877
5878/**
6286
6287/* STA ID and color bits definitions */
6288#define IWM_STA_ID_SEED (0x0f)
6289#define IWM_STA_ID_POS (0)
6290#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
6291
6292#define IWM_STA_COLOR_SEED (0x7)
6293#define IWM_STA_COLOR_POS (4)

--- 36 unchanged lines hidden (view full) ---

6330} __packed;
6331
6332#define IWM_ADD_STA_STATUS_MASK 0xFF
6333#define IWM_ADD_STA_BAID_VALID_MASK 0x8000
6334#define IWM_ADD_STA_BAID_MASK 0x7F00
6335#define IWM_ADD_STA_BAID_SHIFT 8
6336
6337/**
5879 * struct iwl_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
6338 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5880 * ( REPLY_ADD_STA = 0x18 )
6339 * ( REPLY_ADD_STA = 0x18 )
5881 * @add_modify: see &enum iwl_sta_mode
5882 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
6340 * @add_modify: 1: modify existing, 0: add new station
6341 * @awake_acs:
5883 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
6342 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5884 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
5885 * @mac_id_n_color: the Mac context this station belongs to,
5886 * see &enum iwl_ctxt_id_and_color
5887 * @addr: station's MAC address
5888 * @reserved2: reserved
6343 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
6344 * @mac_id_n_color: the Mac context this station belongs to
6345 * @addr[ETHER_ADDR_LEN]: station's MAC address
5889 * @sta_id: index of station in uCode's station table
6346 * @sta_id: index of station in uCode's station table
5890 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
6347 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5891 * alone. 1 - modify, 0 - don't change.
6348 * alone. 1 - modify, 0 - don't change.
5892 * @reserved3: reserved
5893 * @station_flags: look at &enum iwl_sta_flags
5894 * @station_flags_msk: what of %station_flags have changed,
5895 * also &enum iwl_sta_flags
6349 * @station_flags: look at %iwm_sta_flags
6350 * @station_flags_msk: what of %station_flags have changed
5896 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
6351 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5897 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
6352 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5898 * add_immediate_ba_ssn.
5899 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
6353 * add_immediate_ba_ssn.
6354 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5900 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
6355 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5901 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5902 * add_immediate_ba_tid.
5903 * @sleep_tx_count: number of packets to transmit to station even though it is
5904 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5905 * keeps track of STA sleep state.
6356 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
6357 * add_immediate_ba_tid.
6358 * @sleep_tx_count: number of packets to transmit to station even though it is
6359 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
6360 * keeps track of STA sleep state.
5906 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag.
6361 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5907 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5908 * mac-addr.
5909 * @beamform_flags: beam forming controls
5910 * @tfd_queue_msk: tfd queues used by this station
5911 *
5912 * The device contains an internal table of per-station information, with info
5913 * on security keys, aggregation parameters, and Tx rates for initial Tx
6362 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
6363 * mac-addr.
6364 * @beamform_flags: beam forming controls
6365 * @tfd_queue_msk: tfd queues used by this station
6366 *
6367 * The device contains an internal table of per-station information, with info
6368 * on security keys, aggregation parameters, and Tx rates for initial Tx
5914 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD).
6369 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5915 *
5916 * ADD_STA sets up the table entry for one station, either creating a new
5917 * entry, or modifying a pre-existing one.
5918 */
5919struct iwm_add_sta_cmd_v7 {
5920 uint8_t add_modify;
5921 uint8_t awake_acs;
5922 uint16_t tid_disable_tx;
5923 uint32_t mac_id_n_color;
6370 *
6371 * ADD_STA sets up the table entry for one station, either creating a new
6372 * entry, or modifying a pre-existing one.
6373 */
6374struct iwm_add_sta_cmd_v7 {
6375 uint8_t add_modify;
6376 uint8_t awake_acs;
6377 uint16_t tid_disable_tx;
6378 uint32_t mac_id_n_color;
5924 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
6379 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5925 uint16_t reserved2;
5926 uint8_t sta_id;
5927 uint8_t modify_mask;
5928 uint16_t reserved3;
5929 uint32_t station_flags;
5930 uint32_t station_flags_msk;
5931 uint8_t add_immediate_ba_tid;
5932 uint8_t remove_immediate_ba_tid;
5933 uint16_t add_immediate_ba_ssn;
5934 uint16_t sleep_tx_count;
5935 uint16_t sleep_state_flags;
5936 uint16_t assoc_id;
5937 uint16_t beamform_flags;
5938 uint32_t tfd_queue_msk;
5939} __packed; /* ADD_STA_CMD_API_S_VER_7 */
5940
5941/**
6380 uint16_t reserved2;
6381 uint8_t sta_id;
6382 uint8_t modify_mask;
6383 uint16_t reserved3;
6384 uint32_t station_flags;
6385 uint32_t station_flags_msk;
6386 uint8_t add_immediate_ba_tid;
6387 uint8_t remove_immediate_ba_tid;
6388 uint16_t add_immediate_ba_ssn;
6389 uint16_t sleep_tx_count;
6390 uint16_t sleep_state_flags;
6391 uint16_t assoc_id;
6392 uint16_t beamform_flags;
6393 uint32_t tfd_queue_msk;
6394} __packed; /* ADD_STA_CMD_API_S_VER_7 */
6395
6396/**
5942 * enum iwm_sta_type - FW station types
5943 * ( REPLY_ADD_STA = 0x18 )
5944 * @IWM_STA_LINK: Link station - normal RX and TX traffic.
5945 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons
5946 * and probe responses.
5947 * @IWM_STA_MULTICAST: multicast traffic,
5948 * @IWM_STA_TDLS_LINK: TDLS link station
5949 * @IWM_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on).
5950 */
5951enum iwm_sta_type {
5952 IWM_STA_LINK,
5953 IWM_STA_GENERAL_PURPOSE,
5954 IWM_STA_MULTICAST,
5955 IWM_STA_TDLS_LINK,
5956 IWM_STA_AUX_ACTIVITY,
5957};
5958
5959/**
5960 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table.
5961 * ( REPLY_ADD_STA = 0x18 )
6397 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table.
6398 * ( REPLY_ADD_STA = 0x18 )
5962 * @add_modify: see &enum iwm_sta_mode
6399 * @add_modify: see &enum iwl_sta_mode
5963 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
5964 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5965 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
5966 * @mac_id_n_color: the Mac context this station belongs to,
5967 * see &enum iwl_ctxt_id_and_color
5968 * @addr: station's MAC address
5969 * @reserved2: reserved
5970 * @sta_id: index of station in uCode's station table
5971 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
5972 * alone. 1 - modify, 0 - don't change.
5973 * @reserved3: reserved
6400 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
6401 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
6402 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
6403 * @mac_id_n_color: the Mac context this station belongs to,
6404 * see &enum iwl_ctxt_id_and_color
6405 * @addr: station's MAC address
6406 * @reserved2: reserved
6407 * @sta_id: index of station in uCode's station table
6408 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
6409 * alone. 1 - modify, 0 - don't change.
6410 * @reserved3: reserved
5974 * @station_flags: look at &enum iwm_sta_flags
6411 * @station_flags: look at &enum iwl_sta_flags
5975 * @station_flags_msk: what of %station_flags have changed,
6412 * @station_flags_msk: what of %station_flags have changed,
5976 * also &enum iwm_sta_flags
6413 * also &enum iwl_sta_flags
5977 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5978 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
5979 * add_immediate_ba_ssn.
5980 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5981 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
5982 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5983 * add_immediate_ba_tid.
5984 * @sleep_tx_count: number of packets to transmit to station even though it is

--- 18 unchanged lines hidden (view full) ---

6003 * ADD_STA sets up the table entry for one station, either creating a new
6004 * entry, or modifying a pre-existing one.
6005 */
6006struct iwm_add_sta_cmd {
6007 uint8_t add_modify;
6008 uint8_t awake_acs;
6009 uint16_t tid_disable_tx;
6010 uint32_t mac_id_n_color;
6414 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
6415 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
6416 * add_immediate_ba_ssn.
6417 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
6418 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
6419 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
6420 * add_immediate_ba_tid.
6421 * @sleep_tx_count: number of packets to transmit to station even though it is

--- 18 unchanged lines hidden (view full) ---

6440 * ADD_STA sets up the table entry for one station, either creating a new
6441 * entry, or modifying a pre-existing one.
6442 */
6443struct iwm_add_sta_cmd {
6444 uint8_t add_modify;
6445 uint8_t awake_acs;
6446 uint16_t tid_disable_tx;
6447 uint32_t mac_id_n_color;
6011 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
6448 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
6012 uint16_t reserved2;
6013 uint8_t sta_id;
6014 uint8_t modify_mask;
6015 uint16_t reserved3;
6016 uint32_t station_flags;
6017 uint32_t station_flags_msk;
6018 uint8_t add_immediate_ba_tid;
6019 uint8_t remove_immediate_ba_tid;

--- 5 unchanged lines hidden (view full) ---

6025 uint16_t beamform_flags;
6026 uint32_t tfd_queue_msk;
6027 uint16_t rx_ba_window;
6028 uint8_t sp_length;
6029 uint8_t uapsd_acs;
6030} __packed; /* ADD_STA_CMD_API_S_VER_10 */
6031
6032/**
6449 uint16_t reserved2;
6450 uint8_t sta_id;
6451 uint8_t modify_mask;
6452 uint16_t reserved3;
6453 uint32_t station_flags;
6454 uint32_t station_flags_msk;
6455 uint8_t add_immediate_ba_tid;
6456 uint8_t remove_immediate_ba_tid;

--- 5 unchanged lines hidden (view full) ---

6462 uint16_t beamform_flags;
6463 uint32_t tfd_queue_msk;
6464 uint16_t rx_ba_window;
6465 uint8_t sp_length;
6466 uint8_t uapsd_acs;
6467} __packed; /* ADD_STA_CMD_API_S_VER_10 */
6468
6469/**
6033 * struct iwm_add_sta_key_cmd - add/modify sta key
6034 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
6470 * FW station types
6471 * ( REPLY_ADD_STA = 0x18 )
6472 * @IWM_STA_LINK: Link station - normal RX and TX traffic.
6473 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons
6474 * and probe responses.
6475 * @IWM_STA_MULTICAST: multicast traffic,
6476 * @IWM_STA_TDLS_LINK: TDLS link station
6477 * @IWM_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on).
6478 */
6479#define IWM_STA_LINK 0
6480#define IWM_STA_GENERAL_PURPOSE 1
6481#define IWM_STA_MULTICAST 2
6482#define IWM_STA_TDLS_LINK 3
6483#define IWM_STA_AUX_ACTIVITY 4
6484
6485/**
6486 * struct iwm_add_sta_key_common - add/modify sta key common part
6487 * ( REPLY_ADD_STA_KEY = 0x17 )
6035 * @sta_id: index of station in uCode's station table
6036 * @key_offset: key offset in key storage
6488 * @sta_id: index of station in uCode's station table
6489 * @key_offset: key offset in key storage
6037 * @key_flags: type %iwm_sta_key_flag
6490 * @key_flags: IWM_STA_KEY_FLG_*
6038 * @key: key material data
6491 * @key: key material data
6039 * @key2: key material data
6040 * @rx_secur_seq_cnt: RX security sequence counter for the key
6492 * @rx_secur_seq_cnt: RX security sequence counter for the key
6041 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
6042 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
6043 */
6493 */
6044struct iwm_add_sta_key_cmd {
6494struct iwm_add_sta_key_common {
6045 uint8_t sta_id;
6046 uint8_t key_offset;
6047 uint16_t key_flags;
6495 uint8_t sta_id;
6496 uint8_t key_offset;
6497 uint16_t key_flags;
6048 uint8_t key[16];
6049 uint8_t key2[16];
6498 uint8_t key[32];
6050 uint8_t rx_secur_seq_cnt[16];
6499 uint8_t rx_secur_seq_cnt[16];
6500} __packed;
6501
6502/**
6503 * struct iwm_add_sta_key_cmd_v1 - add/modify sta key
6504 * @common: see &struct iwm_add_sta_key_common
6505 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
6506 * @reserved: reserved
6507 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
6508 */
6509struct iwm_add_sta_key_cmd_v1 {
6510 struct iwm_add_sta_key_common common;
6051 uint8_t tkip_rx_tsc_byte2;
6052 uint8_t reserved;
6053 uint16_t tkip_rx_ttak[5];
6511 uint8_t tkip_rx_tsc_byte2;
6512 uint8_t reserved;
6513 uint16_t tkip_rx_ttak[5];
6054} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
6514} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */
6055
6056/**
6515
6516/**
6057 * enum iwm_add_sta_rsp_status - status in the response to ADD_STA command
6517 * struct iwm_add_sta_key_cmd - add/modify sta key
6518 * @common: see &struct iwm_add_sta_key_common
6519 * @rx_mic_key: TKIP RX unicast or multicast key
6520 * @tx_mic_key: TKIP TX key
6521 * @transmit_seq_cnt: TSC, transmit packet number
6522 */
6523struct iwm_add_sta_key_cmd {
6524 struct iwm_add_sta_key_common common;
6525 uint64_t rx_mic_key;
6526 uint64_t tx_mic_key;
6527 uint64_t transmit_seq_cnt;
6528} __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */
6529
6530/**
6531 * status in the response to ADD_STA command
6058 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
6059 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
6060 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
6061 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
6062 * that doesn't exist.
6063 */
6532 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
6533 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
6534 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
6535 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
6536 * that doesn't exist.
6537 */
6064enum iwm_add_sta_rsp_status {
6065 IWM_ADD_STA_SUCCESS = 0x1,
6066 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
6067 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
6068 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
6069};
6538#define IWM_ADD_STA_SUCCESS 0x1
6539#define IWM_ADD_STA_STATIONS_OVERLOAD 0x2
6540#define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4
6541#define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8
6070
6071/**
6072 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table
6073 * ( IWM_REMOVE_STA = 0x19 )
6074 * @sta_id: the station id of the station to be removed
6075 */
6076struct iwm_rm_sta_cmd {
6077 uint8_t sta_id;

--- 34 unchanged lines hidden (view full) ---

6112 uint32_t mac_id_n_color;
6113 uint8_t num_keys;
6114 uint8_t decryption_type;
6115 uint8_t flags;
6116 uint8_t reserved;
6117 struct iwm_wep_key wep_key[0];
6118} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
6119
6542
6543/**
6544 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table
6545 * ( IWM_REMOVE_STA = 0x19 )
6546 * @sta_id: the station id of the station to be removed
6547 */
6548struct iwm_rm_sta_cmd {
6549 uint8_t sta_id;

--- 34 unchanged lines hidden (view full) ---

6584 uint32_t mac_id_n_color;
6585 uint8_t num_keys;
6586 uint8_t decryption_type;
6587 uint8_t flags;
6588 uint8_t reserved;
6589 struct iwm_wep_key wep_key[0];
6590} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
6591
6120/*
6121 * END mvm/fw-api-sta.h
6122 */
6123
6124/*
6592/*
6125 * BT coex
6126 */
6127
6593 * BT coex
6594 */
6595
6128enum iwm_bt_coex_mode {
6129 IWM_BT_COEX_DISABLE = 0x0,
6130 IWM_BT_COEX_NW = 0x1,
6131 IWM_BT_COEX_BT = 0x2,
6132 IWM_BT_COEX_WIFI = 0x3,
6133}; /* BT_COEX_MODES_E */
6596#define IWM_BT_COEX_DISABLE 0x0
6597#define IWM_BT_COEX_NW 0x1
6598#define IWM_BT_COEX_BT 0x2
6599#define IWM_BT_COEX_WIFI 0x3
6600/* BT_COEX_MODES_E */
6134
6601
6135enum iwm_bt_coex_enabled_modules {
6136 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
6137 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
6138 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
6139 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
6140 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
6141}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
6602#define IWM_BT_COEX_MPLUT_ENABLED (1 << 0)
6603#define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)
6604#define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2)
6605#define IWM_BT_COEX_CORUN_ENABLED (1 << 3)
6606#define IWM_BT_COEX_HIGH_BAND_RET (1 << 4)
6607/* BT_COEX_MODULES_ENABLE_E_VER_1 */
6142
6143/**
6144 * struct iwm_bt_coex_cmd - bt coex configuration command
6145 * @mode: enum %iwm_bt_coex_mode
6146 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
6147 *
6148 * The structure is used for the BT_COEX command.
6149 */

--- 62 unchanged lines hidden (view full) ---

6212 uint16_t mcc;
6213 uint8_t cap;
6214 uint8_t source_id;
6215 uint32_t n_channels;
6216 uint32_t channels[0];
6217} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
6218
6219/**
6608
6609/**
6610 * struct iwm_bt_coex_cmd - bt coex configuration command
6611 * @mode: enum %iwm_bt_coex_mode
6612 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
6613 *
6614 * The structure is used for the BT_COEX command.
6615 */

--- 62 unchanged lines hidden (view full) ---

6678 uint16_t mcc;
6679 uint8_t cap;
6680 uint8_t source_id;
6681 uint32_t n_channels;
6682 uint32_t channels[0];
6683} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
6684
6685/**
6220 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
6686 * iwm_mcc_update_resp_v2 - response to MCC_UPDATE_CMD.
6221 * Contains the new channel control profile map, if changed, and the new MCC
6222 * (mobile country code).
6223 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
6224 * @status: see &enum iwm_mcc_update_status
6225 * @mcc: the new applied MCC
6226 * @cap: capabilities for all channels which matches the MCC
6227 * @source_id: the MCC source, see iwm_mcc_source
6228 * @time: time elapsed from the MCC test start (in 30 seconds TU)
6229 * @reserved: reserved.
6230 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6231 * channels, depending on platform)
6232 * @channels: channel control data map, DWORD for each channel. Only the first
6233 * 16bits are used.
6234 */
6687 * Contains the new channel control profile map, if changed, and the new MCC
6688 * (mobile country code).
6689 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
6690 * @status: see &enum iwm_mcc_update_status
6691 * @mcc: the new applied MCC
6692 * @cap: capabilities for all channels which matches the MCC
6693 * @source_id: the MCC source, see iwm_mcc_source
6694 * @time: time elapsed from the MCC test start (in 30 seconds TU)
6695 * @reserved: reserved.
6696 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6697 * channels, depending on platform)
6698 * @channels: channel control data map, DWORD for each channel. Only the first
6699 * 16bits are used.
6700 */
6235struct iwm_mcc_update_resp {
6701struct iwm_mcc_update_resp_v2 {
6236 uint32_t status;
6237 uint16_t mcc;
6238 uint8_t cap;
6239 uint8_t source_id;
6240 uint16_t time;
6241 uint16_t reserved;
6242 uint32_t n_channels;
6243 uint32_t channels[0];
6244} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
6245
6702 uint32_t status;
6703 uint16_t mcc;
6704 uint8_t cap;
6705 uint8_t source_id;
6706 uint16_t time;
6707 uint16_t reserved;
6708 uint32_t n_channels;
6709 uint32_t channels[0];
6710} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
6711
6712#define IWM_GEO_NO_INFO 0
6713#define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)
6714
6246/**
6715/**
6716 * iwm_mcc_update_resp_v3 - response to MCC_UPDATE_CMD.
6717 * Contains the new channel control profile map, if changed, and the new MCC
6718 * (mobile country code).
6719 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
6720 * @status: see &enum iwm_mcc_update_status
6721 * @mcc: the new applied MCC
6722 * @cap: capabilities for all channels which matches the MCC
6723 * @source_id: the MCC source, see IWM_MCC_SOURCE_*
6724 * @time: time elapsed from the MCC test start (in 30 seconds TU)
6725 * @geo_info: geographic specific profile information
6726 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6727 * channels, depending on platform)
6728 * @channels: channel control data map, DWORD for each channel. Only the first
6729 * 16bits are used.
6730 */
6731struct iwm_mcc_update_resp_v3 {
6732 uint32_t status;
6733 uint16_t mcc;
6734 uint8_t cap;
6735 uint8_t source_id;
6736 uint16_t time;
6737 uint16_t geo_info;
6738 uint32_t n_channels;
6739 uint32_t channels[0];
6740} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */
6741
6742/**
6247 * struct iwm_mcc_chub_notif - chub notifies of mcc change
6248 * (MCC_CHUB_UPDATE_CMD = 0xc9)
6249 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
6250 * the cellular and connectivity cores that gets updates of the mcc, and
6251 * notifies the ucode directly of any mcc change.
6252 * The ucode requests the driver to request the device to update geographic
6253 * regulatory profile according to the given MCC (Mobile Country Code).
6254 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.

--- 4 unchanged lines hidden (view full) ---

6259 * @reserved1: reserved for alignment
6260 */
6261struct iwm_mcc_chub_notif {
6262 uint16_t mcc;
6263 uint8_t source_id;
6264 uint8_t reserved1;
6265} __packed; /* LAR_MCC_NOTIFY_S */
6266
6743 * struct iwm_mcc_chub_notif - chub notifies of mcc change
6744 * (MCC_CHUB_UPDATE_CMD = 0xc9)
6745 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
6746 * the cellular and connectivity cores that gets updates of the mcc, and
6747 * notifies the ucode directly of any mcc change.
6748 * The ucode requests the driver to request the device to update geographic
6749 * regulatory profile according to the given MCC (Mobile Country Code).
6750 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.

--- 4 unchanged lines hidden (view full) ---

6755 * @reserved1: reserved for alignment
6756 */
6757struct iwm_mcc_chub_notif {
6758 uint16_t mcc;
6759 uint8_t source_id;
6760 uint8_t reserved1;
6761} __packed; /* LAR_MCC_NOTIFY_S */
6762
6267enum iwm_mcc_update_status {
6268 IWM_MCC_RESP_NEW_CHAN_PROFILE,
6269 IWM_MCC_RESP_SAME_CHAN_PROFILE,
6270 IWM_MCC_RESP_INVALID,
6271 IWM_MCC_RESP_NVM_DISABLED,
6272 IWM_MCC_RESP_ILLEGAL,
6273 IWM_MCC_RESP_LOW_PRIORITY,
6274 IWM_MCC_RESP_TEST_MODE_ACTIVE,
6275 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
6276 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
6277};
6763#define IWM_MCC_RESP_NEW_CHAN_PROFILE 0
6764#define IWM_MCC_RESP_SAME_CHAN_PROFILE 1
6765#define IWM_MCC_RESP_INVALID 2
6766#define IWM_MCC_RESP_NVM_DISABLED 3
6767#define IWM_MCC_RESP_ILLEGAL 4
6768#define IWM_MCC_RESP_LOW_PRIORITY 5
6769#define IWM_MCC_RESP_TEST_MODE_ACTIVE 6
6770#define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7
6771#define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8
6278
6772
6279enum iwm_mcc_source {
6280 IWM_MCC_SOURCE_OLD_FW = 0,
6281 IWM_MCC_SOURCE_ME = 1,
6282 IWM_MCC_SOURCE_BIOS = 2,
6283 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
6284 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
6285 IWM_MCC_SOURCE_WIFI = 5,
6286 IWM_MCC_SOURCE_RESERVED = 6,
6287 IWM_MCC_SOURCE_DEFAULT = 7,
6288 IWM_MCC_SOURCE_UNINITIALIZED = 8,
6289 IWM_MCC_SOURCE_MCC_API = 9,
6290 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
6291 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
6292};
6773#define IWM_MCC_SOURCE_OLD_FW 0
6774#define IWM_MCC_SOURCE_ME 1
6775#define IWM_MCC_SOURCE_BIOS 2
6776#define IWM_MCC_SOURCE_3G_LTE_HOST 3
6777#define IWM_MCC_SOURCE_3G_LTE_DEVICE 4
6778#define IWM_MCC_SOURCE_WIFI 5
6779#define IWM_MCC_SOURCE_RESERVED 6
6780#define IWM_MCC_SOURCE_DEFAULT 7
6781#define IWM_MCC_SOURCE_UNINITIALIZED 8
6782#define IWM_MCC_SOURCE_MCC_API 9
6783#define IWM_MCC_SOURCE_GET_CURRENT 0x10
6784#define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11
6293
6294/**
6295 * struct iwm_dts_measurement_notif_v1 - measurements notification
6296 *
6297 * @temp: the measured temperature
6298 * @voltage: the measured voltage
6299 */
6300struct iwm_dts_measurement_notif_v1 {

--- 9 unchanged lines hidden (view full) ---

6310 * @threshold_idx: the trip index that was crossed
6311 */
6312struct iwm_dts_measurement_notif_v2 {
6313 int32_t temp;
6314 int32_t voltage;
6315 int32_t threshold_idx;
6316} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
6317
6785
6786/**
6787 * struct iwm_dts_measurement_notif_v1 - measurements notification
6788 *
6789 * @temp: the measured temperature
6790 * @voltage: the measured voltage
6791 */
6792struct iwm_dts_measurement_notif_v1 {

--- 9 unchanged lines hidden (view full) ---

6802 * @threshold_idx: the trip index that was crossed
6803 */
6804struct iwm_dts_measurement_notif_v2 {
6805 int32_t temp;
6806 int32_t voltage;
6807 int32_t threshold_idx;
6808} __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
6809
6810
6318/*
6319 * Some cherry-picked definitions
6320 */
6321
6322#define IWM_FRAME_LIMIT 64
6323
6324/*
6811/*
6812 * Some cherry-picked definitions
6813 */
6814
6815#define IWM_FRAME_LIMIT 64
6816
6817/*
6818 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
6819 * As the firmware is slowly running out of command IDs and grouping of
6820 * commands is desirable anyway, the firmware is extending the command
6821 * header from 4 bytes to 8 bytes to introduce a group (in place of the
6822 * former flags field, since that's always 0 on commands and thus can
6823 * be easily used to distinguish between the two).
6824 *
6325 * These functions retrieve specific information from the id field in
6326 * the iwm_host_cmd struct which contains the command id, the group id,
6825 * These functions retrieve specific information from the id field in
6826 * the iwm_host_cmd struct which contains the command id, the group id,
6327 * and the version of the command and vice versa.
6827 * and the version of the command.
6328*/
6329static inline uint8_t
6330iwm_cmd_opcode(uint32_t cmdid)
6331{
6332 return cmdid & 0xff;
6333}
6334
6335static inline uint8_t

--- 13 unchanged lines hidden (view full) ---

6349{
6350 return opcode + (groupid << 8) + (version << 16);
6351}
6352
6353/* make uint16_t wide id out of uint8_t group and opcode */
6354#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
6355
6356/* due to the conversion, this group is special */
6828*/
6829static inline uint8_t
6830iwm_cmd_opcode(uint32_t cmdid)
6831{
6832 return cmdid & 0xff;
6833}
6834
6835static inline uint8_t

--- 13 unchanged lines hidden (view full) ---

6849{
6850 return opcode + (groupid << 8) + (version << 16);
6851}
6852
6853/* make uint16_t wide id out of uint8_t group and opcode */
6854#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
6855
6856/* due to the conversion, this group is special */
6357#define IWM_ALWAYS_LONG_GROUP 1
6857#define IWM_ALWAYS_LONG_GROUP 1
6358
6359struct iwm_cmd_header {
6360 uint8_t code;
6361 uint8_t flags;
6362 uint8_t idx;
6363 uint8_t qid;
6364} __packed;
6365
6366struct iwm_cmd_header_wide {
6367 uint8_t opcode;
6368 uint8_t group_id;
6369 uint8_t idx;
6370 uint8_t qid;
6371 uint16_t length;
6372 uint8_t reserved;
6373 uint8_t version;
6374} __packed;
6375
6858
6859struct iwm_cmd_header {
6860 uint8_t code;
6861 uint8_t flags;
6862 uint8_t idx;
6863 uint8_t qid;
6864} __packed;
6865
6866struct iwm_cmd_header_wide {
6867 uint8_t opcode;
6868 uint8_t group_id;
6869 uint8_t idx;
6870 uint8_t qid;
6871 uint16_t length;
6872 uint8_t reserved;
6873 uint8_t version;
6874} __packed;
6875
6376/**
6377 * enum iwm_power_scheme
6378 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode
6379 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default)
6380 * @IWM_POWER_LEVEL_LP - Low Power
6381 */
6382enum iwm_power_scheme {
6383 IWM_POWER_SCHEME_CAM = 1,
6384 IWM_POWER_SCHEME_BPS,
6385 IWM_POWER_SCHEME_LP
6386};
6876#define IWM_POWER_SCHEME_CAM 1
6877#define IWM_POWER_SCHEME_BPS 2
6878#define IWM_POWER_SCHEME_LP 3
6387
6388#define IWM_DEF_CMD_PAYLOAD_SIZE 320
6389#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6390#define IWM_CMD_FAILED_MSK 0x40
6391
6392/**
6393 * struct iwm_device_cmd
6394 *

--- 19 unchanged lines hidden (view full) ---

6414struct iwm_rx_packet {
6415 /*
6416 * The first 4 bytes of the RX frame header contain both the RX frame
6417 * size and some flags.
6418 * Bit fields:
6419 * 31: flag flush RB request
6420 * 30: flag ignore TC (terminal counter) request
6421 * 29: flag fast IRQ request
6879
6880#define IWM_DEF_CMD_PAYLOAD_SIZE 320
6881#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6882#define IWM_CMD_FAILED_MSK 0x40
6883
6884/**
6885 * struct iwm_device_cmd
6886 *

--- 19 unchanged lines hidden (view full) ---

6906struct iwm_rx_packet {
6907 /*
6908 * The first 4 bytes of the RX frame header contain both the RX frame
6909 * size and some flags.
6910 * Bit fields:
6911 * 31: flag flush RB request
6912 * 30: flag ignore TC (terminal counter) request
6913 * 29: flag fast IRQ request
6422 * 28-14: Reserved
6914 * 28-26: Reserved
6915 * 25: Offload enabled
6916 * 24: RPF enabled
6917 * 23: RSS enabled
6918 * 22: Checksum enabled
6919 * 21-16: RX queue
6920 * 15-14: Reserved
6423 * 13-00: RX frame size
6424 */
6425 uint32_t len_n_flags;
6426 struct iwm_cmd_header hdr;
6427 uint8_t data[];
6428} __packed;
6429
6430#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6921 * 13-00: RX frame size
6922 */
6923 uint32_t len_n_flags;
6924 struct iwm_cmd_header hdr;
6925 uint8_t data[];
6926} __packed;
6927
6928#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6431#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
6432#define IWM_FH_RSCSR_FRAME_ALIGN 0x40
6929#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
6930#define IWM_FH_RSCSR_FRAME_ALIGN 0x40
6931#define IWM_FH_RSCSR_RPA_EN (1 << 25)
6932#define IWM_FH_RSCSR_RADA_EN (1 << 26)
6933#define IWM_FH_RSCSR_RXQ_POS 16
6934#define IWM_FH_RSCSR_RXQ_MASK 0x3F0000
6433
6434static inline uint32_t
6435iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6436{
6437
6438 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6439}
6440

--- 35 unchanged lines hidden --- 		6935
6936static inline uint32_t
6937iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6938{
6939
6940 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6941}
6942

--- 35 unchanged lines hidden ---