isp.c (bff85e290f75b18f0492f70859257d854b162095) isp.c (cbf57b472d00c6dee3735ddd9d5ce53edea1a5cf)
1/* $Id: isp.c,v 1.10 1999/01/10 02:55:10 mjacob Exp $ */
2/* release_12_28_98_A+ */
1/* $Id: isp.c,v 1.11 1999/01/10 11:15:22 mjacob Exp $ */
2/* release_01_29_99 */
3/*
4 * Machine and OS Independent (well, as best as possible)
5 * code for the Qlogic ISP SCSI adapters.
6 *
7 *---------------------------------------
8 * Copyright (c) 1997, 1998 by Matthew Jacob
9 * NASA/Ames Research Center
10 * All rights reserved.

--- 102 unchanged lines hidden (view full) ---

113static void isp_update __P((struct ispsoftc *));
114static void isp_setdfltparm __P((struct ispsoftc *));
115static int isp_read_nvram __P((struct ispsoftc *));
116static void isp_rdnvram_word __P((struct ispsoftc *, int, u_int16_t *));
117
118/*
119 * Reset Hardware.
120 *
3/*
4 * Machine and OS Independent (well, as best as possible)
5 * code for the Qlogic ISP SCSI adapters.
6 *
7 *---------------------------------------
8 * Copyright (c) 1997, 1998 by Matthew Jacob
9 * NASA/Ames Research Center
10 * All rights reserved.

--- 102 unchanged lines hidden (view full) ---

113static void isp_update __P((struct ispsoftc *));
114static void isp_setdfltparm __P((struct ispsoftc *));
115static int isp_read_nvram __P((struct ispsoftc *));
116static void isp_rdnvram_word __P((struct ispsoftc *, int, u_int16_t *));
117
118/*
119 * Reset Hardware.
120 *
121 * Hit the chip over the head, download new f/w.
121 * Hit the chip over the head, download new f/w and set it running.
122 *
123 * Locking done elsewhere.
124 */
125void
126isp_reset(isp)
127 struct ispsoftc *isp;
128{
129 static char once = 1;
130 mbreg_t mbs;
122 *
123 * Locking done elsewhere.
124 */
125void
126isp_reset(isp)
127 struct ispsoftc *isp;
128{
129 static char once = 1;
130 mbreg_t mbs;
131 int loops, i, dodnld = 1, deadchip;
131 int loops, i, dodnld = 1;
132 char *revname;
133
134 isp->isp_state = ISP_NILSTATE;
135
136 /*
137 * Basic types (SCSI, FibreChannel and PCI or SBus)
138 * have been set in the MD code. We figure out more
139 * here.
140 */
141 isp->isp_dblev = DFLT_DBLEVEL;
132 char *revname;
133
134 isp->isp_state = ISP_NILSTATE;
135
136 /*
137 * Basic types (SCSI, FibreChannel and PCI or SBus)
138 * have been set in the MD code. We figure out more
139 * here.
140 */
141 isp->isp_dblev = DFLT_DBLEVEL;
142 deadchip = ISP_READ(isp, HCCR) & HCCR_RESET;
143 if (deadchip) {
142
143 /*
144 * Get the current running firmware revision out of the
145 * chip before we hit it over the head (if this is our
146 * first time through). Note that we store this as the
147 * 'ROM' firmware revision- which it may not be. In any
148 * case, we don't really use this yet, but we may in
149 * the future.
150 */
151 if (once == 1) {
152 /*
153 * Just in case it was paused...
154 */
144 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
155 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
145 if (ISP_READ(isp, HCCR) & HCCR_RESET) {
146 isp_dumpregs(isp, "still reset after release");
147 SYS_DELAY(1000);
156 once = 0;
157 mbs.param[0] = MBOX_ABOUT_FIRMWARE;
158 isp_mboxcmd(isp, &mbs);
159 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
160 /*
161 * If this fails, it probably means we're running
162 * an old prom, if anything at all...
163 */
164 isp->isp_romfw_rev = 0;
148 } else {
165 } else {
149 deadchip = 1;
166 isp->isp_romfw_rev =
167 (((u_int16_t) mbs.param[1]) << 10) + mbs.param[2];
150 }
151 }
152
168 }
169 }
170
171 /*
172 * Put it into PAUSE mode.
173 */
174 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
175
153 if (isp->isp_type & ISP_HA_FC) {
154 revname = "2100";
155 } else {
156 sdparam *sdp = isp->isp_param;
157 i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK;
158 switch (i) {
159 default:
160 PRINTF("%s: unknown chip rev. 0x%x- assuming a 1020\n",

--- 26 unchanged lines hidden (view full) ---

187 break;
188 case 5:
189 revname = "1040B";
190 isp->isp_type = ISP_HA_SCSI_1040B;
191 sdp->isp_clock = 60;
192 break;
193 }
194 /*
176 if (isp->isp_type & ISP_HA_FC) {
177 revname = "2100";
178 } else {
179 sdparam *sdp = isp->isp_param;
180 i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK;
181 switch (i) {
182 default:
183 PRINTF("%s: unknown chip rev. 0x%x- assuming a 1020\n",

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210 break;
211 case 5:
212 revname = "1040B";
213 isp->isp_type = ISP_HA_SCSI_1040B;
214 sdp->isp_clock = 60;
215 break;
216 }
217 /*
195 * Try and figure out if we're connected to a differential bus.
196 * You have to pause the RISC processor to read SXP registers.
218 * Now, while we're at it, gather info about ultra
219 * and/or differential mode.
197 */
220 */
198 if (deadchip == 0) {
199 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
200 i = 100;
201 while ((ISP_READ(isp, HCCR) & HCCR_PAUSE) == 0) {
202 SYS_DELAY(20);
203 if (--i == 0) {
204 isp_dumpregs(isp,
205 "cannot stop RISC processor");
206 i = -1;
207 break;
208 }
209 }
221 if (isp->isp_bustype != ISP_BT_SBUS) {
222 ISP_SETBITS(isp, BIU_CONF1, BIU_PCI_CONF1_SXP);
223 }
224 if (ISP_READ(isp, SXP_PINS_DIFF) & SXP_PINS_DIFF_MODE) {
225 PRINTF("%s: Differential Mode\n", isp->isp_name);
226 sdp->isp_diffmode = 1;
210 } else {
227 } else {
211 i = 0;
228 sdp->isp_diffmode = 0;
212 }
229 }
213 if (i > 0) {
214 if (isp->isp_bustype != ISP_BT_SBUS) {
215 ISP_SETBITS(isp, BIU_CONF1, BIU_PCI_CONF1_SXP);
216 }
217 if (ISP_READ(isp, SXP_PINS_DIFF) & SXP_PINS_DIFF_MODE) {
218 IDPRINTF(2, ("%s: Differential Mode Set\n",
219 isp->isp_name));
220 sdp->isp_diffmode = 1;
221 } else {
222 sdp->isp_diffmode = 0;
223 }
224
225 if (isp->isp_bustype != ISP_BT_SBUS) {
226 ISP_CLRBITS(isp, BIU_CONF1, BIU_PCI_CONF1_SXP);
227 }
228
229 /*
230 * Figure out whether we're ultra capable.
231 */
232 i = ISP_READ(isp, RISC_PSR);
233 if (isp->isp_bustype != ISP_BT_SBUS) {
234 i &= RISC_PSR_PCI_ULTRA;
235 } else {
236 i &= RISC_PSR_SBUS_ULTRA;
237 }
238 if (i) {
239 IDPRINTF(2, ("%s: Ultra Mode Capable\n",
240 isp->isp_name));
241 sdp->isp_clock = 60;
242 } else {
243 sdp->isp_clock = 40;
244 }
245 /*
246 * Restart processor, if necessary.
247 */
248 if (deadchip == 0)
249 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
230 i = ISP_READ(isp, RISC_PSR);
231 if (isp->isp_bustype == ISP_BT_SBUS) {
232 i &= RISC_PSR_SBUS_ULTRA;
233 } else {
234 i &= RISC_PSR_PCI_ULTRA;
250 }
235 }
236 if (isp->isp_bustype != ISP_BT_SBUS) {
237 ISP_CLRBITS(isp, BIU_CONF1, BIU_PCI_CONF1_SXP);
238 }
239 if (i != 0) {
240 PRINTF("%s: Ultra Mode Capable\n", isp->isp_name);
241 sdp->isp_ultramode = 1;
242 sdp->isp_clock = 60;
243 } else {
244 sdp->isp_ultramode = 0;
245 sdp->isp_clock = 40;
246 }
247
251 /*
252 * Machine dependent clock (if set) overrides
253 * our generic determinations.
254 */
255 if (isp->isp_mdvec->dv_clock) {
256 if (isp->isp_mdvec->dv_clock < sdp->isp_clock) {
257 sdp->isp_clock = isp->isp_mdvec->dv_clock;
258 }
259 }
248 /*
249 * Machine dependent clock (if set) overrides
250 * our generic determinations.
251 */
252 if (isp->isp_mdvec->dv_clock) {
253 if (isp->isp_mdvec->dv_clock < sdp->isp_clock) {
254 sdp->isp_clock = isp->isp_mdvec->dv_clock;
255 }
256 }
257
260 }
261
262 /*
263 * Do MD specific pre initialization
264 */
265 ISP_RESET0(isp);
266
258 }
259
260 /*
261 * Do MD specific pre initialization
262 */
263 ISP_RESET0(isp);
264
267 if (once == 1 && deadchip == 0) {
268 once = 0;
269 /*
270 * Get the current running firmware revision out of the
271 * chip before we hit it over the head (if this is our
272 * first time through). Note that we store this as the
273 * 'ROM' firmware revision- which it may not be. In any
274 * case, we don't really use this yet, but we may in
275 * the future.
276 */
277 mbs.param[0] = MBOX_ABOUT_FIRMWARE;
278 isp_mboxcmd(isp, &mbs);
279 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
280 IDPRINTF(3, ("%s: initial ABOUT FIRMWARE command "
281 "failed\n", isp->isp_name));
282 } else {
283 isp->isp_romfw_rev =
284 (((u_int16_t) mbs.param[1]) << 10) + mbs.param[2];
285 }
286 }
265again:
287
266
288
289 /*
290 * Hit the chip over the head with hammer,
291 * and give the ISP a chance to recover.
292 */
293
294 if (isp->isp_type & ISP_HA_SCSI) {
295 ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET);
296 /*

--- 9 unchanged lines hidden (view full) ---

306 ISP_WRITE(isp, DDMA_CONTROL,
307 DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
308 } else {
309 ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET);
310 /*
311 * A slight delay...
312 */
313 SYS_DELAY(100);
267 /*
268 * Hit the chip over the head with hammer,
269 * and give the ISP a chance to recover.
270 */
271
272 if (isp->isp_type & ISP_HA_SCSI) {
273 ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET);
274 /*

--- 9 unchanged lines hidden (view full) ---

284 ISP_WRITE(isp, DDMA_CONTROL,
285 DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
286 } else {
287 ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET);
288 /*
289 * A slight delay...
290 */
291 SYS_DELAY(100);
292
293 /*
294 * Clear data && control DMA engines.
295 */
314 ISP_WRITE(isp, CDMA2100_CONTROL,
315 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
316 ISP_WRITE(isp, TDMA2100_CONTROL,
317 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
318 ISP_WRITE(isp, RDMA2100_CONTROL,
319 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
320 }
321

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332 break;
333 }
334 SYS_DELAY(100);
335 if (--loops < 0) {
336 isp_dumpregs(isp, "chip reset timed out");
337 return;
338 }
339 }
296 ISP_WRITE(isp, CDMA2100_CONTROL,
297 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
298 ISP_WRITE(isp, TDMA2100_CONTROL,
299 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
300 ISP_WRITE(isp, RDMA2100_CONTROL,
301 DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
302 }
303

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314 break;
315 }
316 SYS_DELAY(100);
317 if (--loops < 0) {
318 isp_dumpregs(isp, "chip reset timed out");
319 return;
320 }
321 }
322
340 /*
323 /*
341 * More initialization
324 * After we've fired this chip up, zero out the conf1 register
325 * for SCSI adapters and other settings for the 2100.
342 */
326 */
343 if (isp->isp_type & ISP_HA_SCSI) {
327
328 if (isp->isp_type & ISP_HA_SCSI) {
344 ISP_WRITE(isp, BIU_CONF1, 0);
345 } else {
346 ISP_WRITE(isp, BIU2100_CSR, 0);
329 ISP_WRITE(isp, BIU_CONF1, 0);
330 } else {
331 ISP_WRITE(isp, BIU2100_CSR, 0);
347 /*
348 * All 2100's are 60Mhz with fast rams onboard.
349 */
350 ISP_WRITE(isp, RISC_MTR2100, 0x1212);
351 }
352
332 }
333
334 /*
335 * Reset RISC Processor
336 */
353 ISP_WRITE(isp, HCCR, HCCR_CMD_RESET);
354 SYS_DELAY(100);
355
356 /*
337 ISP_WRITE(isp, HCCR, HCCR_CMD_RESET);
338 SYS_DELAY(100);
339
340 /*
357 * Establish some initial burst rate thingies
341 * Establish some initial burst rate stuff.
358 * (only for the 1XX0 boards). This really should
359 * be done later after fetching from NVRAM.
360 */
361 if (isp->isp_type & ISP_HA_SCSI) {
342 * (only for the 1XX0 boards). This really should
343 * be done later after fetching from NVRAM.
344 */
345 if (isp->isp_type & ISP_HA_SCSI) {
362 u_int16_t conf1 = isp->isp_mdvec->dv_conf1;
346 u_int16_t tmp = isp->isp_mdvec->dv_conf1;
363 /*
364 * Busted FIFO. Turn off all but burst enables.
365 */
366 if (isp->isp_type == ISP_HA_SCSI_1040A) {
347 /*
348 * Busted FIFO. Turn off all but burst enables.
349 */
350 if (isp->isp_type == ISP_HA_SCSI_1040A) {
367 conf1 &= BIU_BURST_ENABLE;
351 tmp &= BIU_BURST_ENABLE;
368 }
352 }
369 ISP_SETBITS(isp, BIU_CONF1, conf1);
370 if (conf1 & BIU_BURST_ENABLE) {
353 ISP_SETBITS(isp, BIU_CONF1, tmp);
354 if (tmp & BIU_BURST_ENABLE) {
371 ISP_SETBITS(isp, CDMA_CONF, DMA_ENABLE_BURST);
372 ISP_SETBITS(isp, DDMA_CONF, DMA_ENABLE_BURST);
373 }
355 ISP_SETBITS(isp, CDMA_CONF, DMA_ENABLE_BURST);
356 ISP_SETBITS(isp, DDMA_CONF, DMA_ENABLE_BURST);
357 }
358#ifdef PTI_CARDS
359 if (((sdparam *) isp->isp_param)->isp_ultramode) {
360 while(ISP_READ(isp, RISC_MTR) != 0x1313) {
361 ISP_WRITE(isp, RISC_MTR, 0x1313);
362 ISP_WRITE(isp, HCCR, HCCR_CMD_STEP);
363 }
364 } else {
365 ISP_WRITE(isp, RISC_MTR, 0x1212);
366 }
367 /*
368 * PTI specific register
369 */
370 ISP_WRITE(isp, RISC_EMB, DUAL_BANK)
371#else
372 ISP_WRITE(isp, RISC_MTR, 0x1212);
373#endif
374 } else {
375 ISP_WRITE(isp, RISC_MTR2100, 0x1212);
374 }
376 }
377
375 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); /* release paused processor */
376
377 /*
378 * Do MD specific post initialization
379 */
380 ISP_RESET1(isp);
381
382 /*
383 * Enable interrupts
384 */
385 ENABLE_INTS(isp);
386
387 /*
378 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); /* release paused processor */
379
380 /*
381 * Do MD specific post initialization
382 */
383 ISP_RESET1(isp);
384
385 /*
386 * Enable interrupts
387 */
388 ENABLE_INTS(isp);
389
390 /*
391 * Wait for everything to finish firing up...
392 */
393 loops = MBOX_DELAY_COUNT;
394 while (ISP_READ(isp, OUTMAILBOX0) == MBOX_BUSY) {
395 SYS_DELAY(100);
396 if (--loops < 0) {
397 PRINTF("%s: MBOX_BUSY never cleared on reset\n",
398 isp->isp_name);
399 return;
400 }
401 }
402
403 /*
404 * Up until this point we've done everything by just reading or
405 * setting registers. From this point on we rely on at least *some*
406 * kind of firmware running in the card.
407 */
408
409 /*
388 * Do some sanity checking.
389 */
390 mbs.param[0] = MBOX_NO_OP;
391 isp_mboxcmd(isp, &mbs);
392 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
393 isp_dumpregs(isp, "NOP test failed");
394 return;
395 }

--- 29 unchanged lines hidden (view full) ---

425 * whether we have f/w at all and whether a config flag
426 * has disabled our download.
427 */
428 if ((isp->isp_mdvec->dv_fwlen == 0) ||
429 (isp->isp_confopts & ISP_CFG_NORELOAD)) {
430 dodnld = 0;
431 }
432
410 * Do some sanity checking.
411 */
412 mbs.param[0] = MBOX_NO_OP;
413 isp_mboxcmd(isp, &mbs);
414 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
415 isp_dumpregs(isp, "NOP test failed");
416 return;
417 }

--- 29 unchanged lines hidden (view full) ---

447 * whether we have f/w at all and whether a config flag
448 * has disabled our download.
449 */
450 if ((isp->isp_mdvec->dv_fwlen == 0) ||
451 (isp->isp_confopts & ISP_CFG_NORELOAD)) {
452 dodnld = 0;
453 }
454
433 if (dodnld) {
455 if (dodnld && isp->isp_mdvec->dv_fwlen) {
434 for (i = 0; i < isp->isp_mdvec->dv_fwlen; i++) {
435 mbs.param[0] = MBOX_WRITE_RAM_WORD;
436 mbs.param[1] = isp->isp_mdvec->dv_codeorg + i;
437 mbs.param[2] = isp->isp_mdvec->dv_ispfw[i];
438 isp_mboxcmd(isp, &mbs);
439 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
456 for (i = 0; i < isp->isp_mdvec->dv_fwlen; i++) {
457 mbs.param[0] = MBOX_WRITE_RAM_WORD;
458 mbs.param[1] = isp->isp_mdvec->dv_codeorg + i;
459 mbs.param[2] = isp->isp_mdvec->dv_ispfw[i];
460 isp_mboxcmd(isp, &mbs);
461 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
440 isp_dumpregs(isp, "f/w download failed");
441 return;
462 PRINTF("%s: F/W download failed at word %d\n",
463 isp->isp_name, i);
464 dodnld = 0;
465 goto again;
442 }
443 }
444
466 }
467 }
468
445 if (isp->isp_mdvec->dv_fwlen) {
446 /*
447 * Verify that it downloaded correctly.
448 */
449 mbs.param[0] = MBOX_VERIFY_CHECKSUM;
450 mbs.param[1] = isp->isp_mdvec->dv_codeorg;
451 isp_mboxcmd(isp, &mbs);
452 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
453 isp_dumpregs(isp, "ram checksum failure");
454 return;
455 }
469 /*
470 * Verify that it downloaded correctly.
471 */
472 mbs.param[0] = MBOX_VERIFY_CHECKSUM;
473 mbs.param[1] = isp->isp_mdvec->dv_codeorg;
474 isp_mboxcmd(isp, &mbs);
475 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
476 isp_dumpregs(isp, "ram checksum failure");
477 return;
456 }
457 } else {
458 IDPRINTF(3, ("%s: skipping f/w download\n", isp->isp_name));
459 }
460
461 /*
462 * Now start it rolling.
463 *
464 * If we didn't actually download f/w,
465 * we still need to (re)start it.
466 */
467
468 mbs.param[0] = MBOX_EXEC_FIRMWARE;
478 }
479 } else {
480 IDPRINTF(3, ("%s: skipping f/w download\n", isp->isp_name));
481 }
482
483 /*
484 * Now start it rolling.
485 *
486 * If we didn't actually download f/w,
487 * we still need to (re)start it.
488 */
489
490 mbs.param[0] = MBOX_EXEC_FIRMWARE;
469 mbs.param[1] = isp->isp_mdvec->dv_codeorg;
491 if (isp->isp_mdvec->dv_codeorg)
492 mbs.param[1] = isp->isp_mdvec->dv_codeorg;
493 else
494 mbs.param[1] = 0x1000;
470 isp_mboxcmd(isp, &mbs);
471
472 if (isp->isp_type & ISP_HA_SCSI) {
473 sdparam *sdp = isp->isp_param;
474 /*
475 * Set CLOCK RATE, but only if asked to.
476 */
477 if (sdp->isp_clock) {

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501 PRINTF("%s: Last F/W revision was %d.%d\n", isp->isp_name,
502 isp->isp_romfw_rev >> 10, isp->isp_romfw_rev & 0x3ff);
503 }
504 isp_fw_state(isp);
505 isp->isp_state = ISP_RESETSTATE;
506}
507
508/*
495 isp_mboxcmd(isp, &mbs);
496
497 if (isp->isp_type & ISP_HA_SCSI) {
498 sdparam *sdp = isp->isp_param;
499 /*
500 * Set CLOCK RATE, but only if asked to.
501 */
502 if (sdp->isp_clock) {

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526 PRINTF("%s: Last F/W revision was %d.%d\n", isp->isp_name,
527 isp->isp_romfw_rev >> 10, isp->isp_romfw_rev & 0x3ff);
528 }
529 isp_fw_state(isp);
530 isp->isp_state = ISP_RESETSTATE;
531}
532
533/*
509 * Initialize Hardware to known state
534 * Initialize Parameters of Hardware to a known state.
510 *
511 * Locks are held before coming here.
512 */
513
514void
515isp_init(isp)
516 struct ispsoftc *isp;
517{

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669 isp_mboxcmd(isp, &mbs);
670 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
671 PRINTF("%s: failed to set device queue "
672 "parameters for target %d, lun %d\n",
673 isp->isp_name, tgt, lun);
674 break;
675 }
676 }
535 *
536 * Locks are held before coming here.
537 */
538
539void
540isp_init(isp)
541 struct ispsoftc *isp;
542{

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694 isp_mboxcmd(isp, &mbs);
695 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
696 PRINTF("%s: failed to set device queue "
697 "parameters for target %d, lun %d\n",
698 isp->isp_name, tgt, lun);
699 break;
700 }
701 }
702 /*
703 * And mark this as an unannounced device
704 */
705 sdp->isp_devparam[tgt].dev_announced = 0;
677 }
678
679 /*
680 * Set up DMA for the request and result mailboxes.
681 */
682 if (ISP_MBOXDMASETUP(isp) != 0) {
683 PRINTF("%s: can't setup dma mailboxes\n", isp->isp_name);
684 return;

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705 mbs.param[5] = 0;
706 isp_mboxcmd(isp, &mbs);
707 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
708 isp_dumpregs(isp, "set of request queue failed");
709 return;
710 }
711 isp->isp_reqidx = isp->isp_reqodx = 0;
712
706 }
707
708 /*
709 * Set up DMA for the request and result mailboxes.
710 */
711 if (ISP_MBOXDMASETUP(isp) != 0) {
712 PRINTF("%s: can't setup dma mailboxes\n", isp->isp_name);
713 return;

--- 20 unchanged lines hidden (view full) ---

734 mbs.param[5] = 0;
735 isp_mboxcmd(isp, &mbs);
736 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
737 isp_dumpregs(isp, "set of request queue failed");
738 return;
739 }
740 isp->isp_reqidx = isp->isp_reqodx = 0;
741
742 /*
743 * Turn on Fast Posting
744 */
745 if (isp->isp_fwrev >= ISP_FW_REV(7, 55)) {
746 mbs.param[0] = MBOX_SET_FW_FEATURES;
747 mbs.param[1] = FW_FEATURE_FAST_POST;
748 isp_mboxcmd(isp, &mbs);
749 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
750 PRINTF("%s: unable to enable FAST Posting\n",
751 isp->isp_name);
752 }
753 }
754
713 /*
714 * XXX: See whether or not for 7.55 F/W or later we
715 * XXX: can do without this, and see whether we should
716 * XXX: honor the NVRAM SCSI_RESET_DISABLE token.
717 */
718 mbs.param[0] = MBOX_BUS_RESET;
719 mbs.param[1] = 3;
720 isp_mboxcmd(isp, &mbs);

--- 37 unchanged lines hidden (view full) ---

758 * best way to figure this out XXX
759 */
760#ifndef __i386__
761 loopid = DEFAULT_LOOPID;
762#else
763 loopid = fcp->isp_loopid;
764#endif
765
755 /*
756 * XXX: See whether or not for 7.55 F/W or later we
757 * XXX: can do without this, and see whether we should
758 * XXX: honor the NVRAM SCSI_RESET_DISABLE token.
759 */
760 mbs.param[0] = MBOX_BUS_RESET;
761 mbs.param[1] = 3;
762 isp_mboxcmd(isp, &mbs);

--- 37 unchanged lines hidden (view full) ---

800 * best way to figure this out XXX
801 */
802#ifndef __i386__
803 loopid = DEFAULT_LOOPID;
804#else
805 loopid = fcp->isp_loopid;
806#endif
807
808#if defined(ISP2100_FABRIC) && defined(ISP2100_SCCLUN)
809 PRINTF("%s: Fabric Support, Expanded Lun Support\n", isp->isp_name);
810#endif
811#if defined(ISP2100_FABRIC) && !defined(ISP2100_SCCLUN)
812 PRINTF("%s: Fabric Support\n", isp->isp_name);
813#endif
814#if !defined(ISP2100_FABRIC) && defined(ISP2100_SCCLUN)
815 PRINTF("%s: Expanded Lun Support\n", isp->isp_name);
816#endif
766
767 icbp = (isp_icb_t *) fcp->isp_scratch;
768 MEMZERO(icbp, sizeof (*icbp));
769
770 icbp->icb_version = ICB_VERSION1;
771#ifdef ISP_TARGET_MODE
772 fcp->isp_fwoptions = ICBOPT_TGT_ENABLE|ICBOPT_INI_TGTTYPE;
773#else
774 fcp->isp_fwoptions = 0;
775#endif
817
818 icbp = (isp_icb_t *) fcp->isp_scratch;
819 MEMZERO(icbp, sizeof (*icbp));
820
821 icbp->icb_version = ICB_VERSION1;
822#ifdef ISP_TARGET_MODE
823 fcp->isp_fwoptions = ICBOPT_TGT_ENABLE|ICBOPT_INI_TGTTYPE;
824#else
825 fcp->isp_fwoptions = 0;
826#endif
776 fcp->isp_fwoptions |= ICBOPT_INI_ADISC|ICBOPT_FAIRNESS;
827 fcp->isp_fwoptions |= ICBOPT_INI_ADISC|ICBOPT_FAIRNESS|ICBOPT_FAST_POST;
777 fcp->isp_fwoptions |= ICBOPT_PDBCHANGE_AE;
778 fcp->isp_fwoptions |= ICBOPT_HARD_ADDRESS;
779#ifdef CHECKME
780 fcp->isp_fwoptions |= ICBOPT_USE_PORTNAME;
781#endif
782#ifdef THIS_WORKED
783 /*
784 * This has unhappiness in target mode
785 */
786 fcp->isp_fwoptions |= ICBOPT_FULL_LOGIN;
787#endif
828 fcp->isp_fwoptions |= ICBOPT_PDBCHANGE_AE;
829 fcp->isp_fwoptions |= ICBOPT_HARD_ADDRESS;
830#ifdef CHECKME
831 fcp->isp_fwoptions |= ICBOPT_USE_PORTNAME;
832#endif
833#ifdef THIS_WORKED
834 /*
835 * This has unhappiness in target mode
836 */
837 fcp->isp_fwoptions |= ICBOPT_FULL_LOGIN;
838#endif
839
788 icbp->icb_fwoptions = fcp->isp_fwoptions;
789 icbp->icb_maxfrmlen = fcp->isp_maxfrmlen;
790 if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN ||
791 icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {
792 PRINTF("%s: bad frame length (%d) from NVRAM- using %d\n",
793 isp->isp_name, fcp->isp_maxfrmlen, ICB_DFLT_FRMLEN);
794 }
795 icbp->icb_maxalloc = fcp->isp_maxalloc;

--- 426 unchanged lines hidden (view full) ---

1222 isp->isp_name, isr));
1223 }
1224 return (0);
1225 }
1226 }
1227
1228 if (ISP_READ(isp, BIU_SEMA) & 1) {
1229 u_int16_t mbox = ISP_READ(isp, OUTMAILBOX0);
840 icbp->icb_fwoptions = fcp->isp_fwoptions;
841 icbp->icb_maxfrmlen = fcp->isp_maxfrmlen;
842 if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN ||
843 icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {
844 PRINTF("%s: bad frame length (%d) from NVRAM- using %d\n",
845 isp->isp_name, fcp->isp_maxfrmlen, ICB_DFLT_FRMLEN);
846 }
847 icbp->icb_maxalloc = fcp->isp_maxalloc;

--- 426 unchanged lines hidden (view full) ---

1274 isp->isp_name, isr));
1275 }
1276 return (0);
1277 }
1278 }
1279
1280 if (ISP_READ(isp, BIU_SEMA) & 1) {
1281 u_int16_t mbox = ISP_READ(isp, OUTMAILBOX0);
1230 if (isp_parse_async(isp, (int) mbox))
1231 return (1);
1282 u_int32_t fast_post_handle = isp_parse_async(isp, (int) mbox);
1232 ISP_WRITE(isp, BIU_SEMA, 0);
1283 ISP_WRITE(isp, BIU_SEMA, 0);
1284 if (fast_post_handle < 0) {
1285 return (1);
1286 } else if (fast_post_handle > 0) {
1287 xs = (ISP_SCSI_XFER_T *)
1288 isp->isp_xflist[fast_post_handle - 1];
1289 isp->isp_xflist[fast_post_handle - 1] = NULL;
1290 /*
1291 * Since we don't have a result queue entry item,
1292 * we must believe that SCSI status is zero and
1293 * that all data transferred.
1294 */
1295 XS_RESID(xs) = 0;
1296 XS_STS(xs) = 0;
1297 if (XS_XFRLEN(xs)) {
1298 ISP_DMAFREE(isp, xs, fast_post_handle - 1);
1299 }
1300 if (isp->isp_nactive > 0)
1301 isp->isp_nactive--;
1302 complist[ndone++] = xs;
1303 }
1233 }
1234
1235 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
1236
1237 optr = isp->isp_residx;
1238 iptr = ISP_READ(isp, OUTMAILBOX5);
1239
1240 if (optr == iptr) {

--- 77 unchanged lines hidden (view full) ---

1318 }
1319 XS_STS(xs) = sp->req_scsi_status & 0xff;
1320 if (isp->isp_type & ISP_HA_SCSI) {
1321 if (sp->req_state_flags & RQSF_GOT_SENSE) {
1322 MEMCPY(XS_SNSP(xs), sp->req_sense_data,
1323 XS_SNSLEN(xs));
1324 XS_SNS_IS_VALID(xs);
1325 }
1304 }
1305
1306 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
1307
1308 optr = isp->isp_residx;
1309 iptr = ISP_READ(isp, OUTMAILBOX5);
1310
1311 if (optr == iptr) {

--- 77 unchanged lines hidden (view full) ---

1389 }
1390 XS_STS(xs) = sp->req_scsi_status & 0xff;
1391 if (isp->isp_type & ISP_HA_SCSI) {
1392 if (sp->req_state_flags & RQSF_GOT_SENSE) {
1393 MEMCPY(XS_SNSP(xs), sp->req_sense_data,
1394 XS_SNSLEN(xs));
1395 XS_SNS_IS_VALID(xs);
1396 }
1397 /*
1398 * A new synchronous rate was negotiated for this
1399 * target. Mark state such that we'll go look up
1400 * that which has changed later.
1401 */
1402 if (sp->req_status_flags & RQSTF_NEGOTIATION) {
1403 sdparam *sdp = isp->isp_param;
1404 isp->isp_update = 1;
1405 sdp->isp_devparam[XS_TGT(xs)].dev_refresh = 1;
1406 }
1326 } else {
1327 if (XS_STS(xs) == SCSI_CHECK) {
1328 XS_SNS_IS_VALID(xs);
1329 MEMCPY(XS_SNSP(xs), sp->req_sense_data,
1330 XS_SNSLEN(xs));
1331 sp->req_state_flags |= RQSF_GOT_SENSE;
1332 }
1333 }

--- 80 unchanged lines hidden (view full) ---

1414 * Support routines.
1415 */
1416
1417static int
1418isp_parse_async(isp, mbox)
1419 struct ispsoftc *isp;
1420 int mbox;
1421{
1407 } else {
1408 if (XS_STS(xs) == SCSI_CHECK) {
1409 XS_SNS_IS_VALID(xs);
1410 MEMCPY(XS_SNSP(xs), sp->req_sense_data,
1411 XS_SNSLEN(xs));
1412 sp->req_state_flags |= RQSF_GOT_SENSE;
1413 }
1414 }

--- 80 unchanged lines hidden (view full) ---

1495 * Support routines.
1496 */
1497
1498static int
1499isp_parse_async(isp, mbox)
1500 struct ispsoftc *isp;
1501 int mbox;
1502{
1503 u_int32_t fast_post_handle = 0;
1504
1422 switch (mbox) {
1423 case ASYNC_BUS_RESET:
1424 PRINTF("%s: SCSI bus reset detected\n", isp->isp_name);
1425 isp->isp_sendmarker = 1;
1426#ifdef ISP_TARGET_MODE
1427 isp_notify_ack(isp, NULL);
1428#endif
1429 break;
1430
1431 case ASYNC_SYSTEM_ERROR:
1432 mbox = ISP_READ(isp, OUTMAILBOX1);
1433 PRINTF("%s: Internal FW Error @ RISC Addr 0x%x\n",
1434 isp->isp_name, mbox);
1435 isp_restart(isp);
1436 /* no point continuing after this */
1505 switch (mbox) {
1506 case ASYNC_BUS_RESET:
1507 PRINTF("%s: SCSI bus reset detected\n", isp->isp_name);
1508 isp->isp_sendmarker = 1;
1509#ifdef ISP_TARGET_MODE
1510 isp_notify_ack(isp, NULL);
1511#endif
1512 break;
1513
1514 case ASYNC_SYSTEM_ERROR:
1515 mbox = ISP_READ(isp, OUTMAILBOX1);
1516 PRINTF("%s: Internal FW Error @ RISC Addr 0x%x\n",
1517 isp->isp_name, mbox);
1518 isp_restart(isp);
1519 /* no point continuing after this */
1437 return (1);
1520 return (-1);
1438
1439 case ASYNC_RQS_XFER_ERR:
1440 PRINTF("%s: Request Queue Transfer Error\n", isp->isp_name);
1441 break;
1442
1443 case ASYNC_RSP_XFER_ERR:
1444 PRINTF("%s: Response Queue Transfer Error\n", isp->isp_name);
1445 break;

--- 38 unchanged lines hidden (view full) ---

1484 break;
1485
1486 case ASYNC_BUS_TRANSIT:
1487 PRINTF("%s: LBD->HVD Transition 0x%x\n",
1488 isp->isp_name, ISP_READ(isp, OUTMAILBOX1));
1489 break;
1490
1491 case ASYNC_CMD_CMPLT:
1521
1522 case ASYNC_RQS_XFER_ERR:
1523 PRINTF("%s: Request Queue Transfer Error\n", isp->isp_name);
1524 break;
1525
1526 case ASYNC_RSP_XFER_ERR:
1527 PRINTF("%s: Response Queue Transfer Error\n", isp->isp_name);
1528 break;

--- 38 unchanged lines hidden (view full) ---

1567 break;
1568
1569 case ASYNC_BUS_TRANSIT:
1570 PRINTF("%s: LBD->HVD Transition 0x%x\n",
1571 isp->isp_name, ISP_READ(isp, OUTMAILBOX1));
1572 break;
1573
1574 case ASYNC_CMD_CMPLT:
1492 PRINTF("%s: fast post completion\n", isp->isp_name);
1493#if 0
1494 fast_post_handle = (ISP_READ(isp, OUTMAILBOX1) << 16) |
1495 ISP_READ(isp, OUTMAILBOX2);
1496#endif
1575 fast_post_handle = (ISP_READ(isp, OUTMAILBOX2) << 16) |
1576 ISP_READ(isp, OUTMAILBOX1);
1577 IDPRINTF(3, ("%s: fast post completion of %u\n", isp->isp_name,
1578 fast_post_handle));
1497 break;
1498
1499 case ASYNC_CTIO_DONE:
1500 /* Should only occur when Fast Posting Set for 2100s */
1501 PRINTF("%s: CTIO done\n", isp->isp_name);
1502 break;
1503
1504 case ASYNC_LIP_OCCURRED:

--- 22 unchanged lines hidden (view full) ---

1527 case ASYNC_CHANGE_NOTIFY:
1528 PRINTF("%s: Name Server Database Changed\n", isp->isp_name);
1529 break;
1530
1531 default:
1532 PRINTF("%s: async %x\n", isp->isp_name, mbox);
1533 break;
1534 }
1579 break;
1580
1581 case ASYNC_CTIO_DONE:
1582 /* Should only occur when Fast Posting Set for 2100s */
1583 PRINTF("%s: CTIO done\n", isp->isp_name);
1584 break;
1585
1586 case ASYNC_LIP_OCCURRED:

--- 22 unchanged lines hidden (view full) ---

1609 case ASYNC_CHANGE_NOTIFY:
1610 PRINTF("%s: Name Server Database Changed\n", isp->isp_name);
1611 break;
1612
1613 default:
1614 PRINTF("%s: async %x\n", isp->isp_name, mbox);
1615 break;
1616 }
1535 return (0);
1617 return (fast_post_handle);
1536}
1537
1538static int
1539isp_handle_other_response(isp, sp, optrp)
1540 struct ispsoftc *isp;
1541 ispstatusreq_t *sp;
1542 u_int8_t *optrp;
1543{

--- 805 unchanged lines hidden (view full) ---

2349 return;
2350
2351 case RQCS_WIDE_FAILED:
2352 PRINTF("%s: Wide Negotiation failed for target %d lun %d\n",
2353 isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2354 if (isp->isp_type & ISP_HA_SCSI) {
2355 sdparam *sdp = isp->isp_param;
2356 isp->isp_update = 1;
1618}
1619
1620static int
1621isp_handle_other_response(isp, sp, optrp)
1622 struct ispsoftc *isp;
1623 ispstatusreq_t *sp;
1624 u_int8_t *optrp;
1625{

--- 805 unchanged lines hidden (view full) ---

2431 return;
2432
2433 case RQCS_WIDE_FAILED:
2434 PRINTF("%s: Wide Negotiation failed for target %d lun %d\n",
2435 isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2436 if (isp->isp_type & ISP_HA_SCSI) {
2437 sdparam *sdp = isp->isp_param;
2438 isp->isp_update = 1;
2357 sdp->isp_devparam[XS_TGT(xs)].dev_update = 1;
2358 sdp->isp_devparam[XS_TGT(xs)].dev_flags &= ~DPARM_WIDE;
2439 sdp->isp_devparam[XS_TGT(xs)].dev_flags &= ~DPARM_WIDE;
2440 sdp->isp_devparam[XS_TGT(xs)].dev_update = 1;
2359 }
2360 XS_SETERR(xs, HBA_NOERROR);
2361 return;
2362
2363 case RQCS_SYNCXFER_FAILED:
2364 PRINTF("%s: SDTR Message failed for target %d lun %d\n",
2365 isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2366 if (isp->isp_type & ISP_HA_SCSI) {
2367 sdparam *sdp = isp->isp_param;
2368 isp->isp_update = 1;
2441 }
2442 XS_SETERR(xs, HBA_NOERROR);
2443 return;
2444
2445 case RQCS_SYNCXFER_FAILED:
2446 PRINTF("%s: SDTR Message failed for target %d lun %d\n",
2447 isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2448 if (isp->isp_type & ISP_HA_SCSI) {
2449 sdparam *sdp = isp->isp_param;
2450 isp->isp_update = 1;
2369 sdp->isp_devparam[XS_TGT(xs)].dev_update = 1;
2370 sdp->isp_devparam[XS_TGT(xs)].dev_flags &= ~DPARM_SYNC;
2451 sdp->isp_devparam[XS_TGT(xs)].dev_flags &= ~DPARM_SYNC;
2452 sdp->isp_devparam[XS_TGT(xs)].dev_update = 1;
2371 }
2372 break;
2373
2374 case RQCS_LVD_BUSERR:
2375 PRINTF("%s: Bad LVD Bus condition while talking to target %d "
2376 "lun %d\n", isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2377 break;
2378

--- 107 unchanged lines hidden (view full) ---

2486 MAKNIB(2, 3), /* 0x42: MBOX_EXEC_BIOS_IOCB */
2487 MAKNIB(0, 0), /* 0x43: */
2488 MAKNIB(0, 0), /* 0x44: */
2489 MAKNIB(0, 0), /* 0x45: */
2490 MAKNIB(0, 0), /* 0x46: */
2491 MAKNIB(0, 0), /* 0x47: */
2492 MAKNIB(0, 0), /* 0x48: */
2493 MAKNIB(0, 0), /* 0x49: */
2453 }
2454 break;
2455
2456 case RQCS_LVD_BUSERR:
2457 PRINTF("%s: Bad LVD Bus condition while talking to target %d "
2458 "lun %d\n", isp->isp_name, XS_TGT(xs), XS_LUN(xs));
2459 break;
2460

--- 107 unchanged lines hidden (view full) ---

2568 MAKNIB(2, 3), /* 0x42: MBOX_EXEC_BIOS_IOCB */
2569 MAKNIB(0, 0), /* 0x43: */
2570 MAKNIB(0, 0), /* 0x44: */
2571 MAKNIB(0, 0), /* 0x45: */
2572 MAKNIB(0, 0), /* 0x46: */
2573 MAKNIB(0, 0), /* 0x47: */
2574 MAKNIB(0, 0), /* 0x48: */
2575 MAKNIB(0, 0), /* 0x49: */
2494 MAKNIB(0, 0), /* 0x4a: */
2495 MAKNIB(0, 0), /* 0x4b: */
2576 MAKNIB(2, 1), /* 0x4a: MBOX_SET_FIRMWARE_FEATURES */
2577 MAKNIB(1, 2), /* 0x4b: MBOX_GET_FIRMWARE_FEATURES */
2496 MAKNIB(0, 0), /* 0x4c: */
2497 MAKNIB(0, 0), /* 0x4d: */
2498 MAKNIB(0, 0), /* 0x4e: */
2499 MAKNIB(0, 0), /* 0x4f: */
2500 MAKNIB(0, 0), /* 0x50: */
2501 MAKNIB(0, 0), /* 0x51: */
2502 MAKNIB(0, 0), /* 0x52: */
2503 MAKNIB(0, 0), /* 0x53: */

--- 370 unchanged lines hidden (view full) ---

2874 isp->isp_update = 0;
2875
2876 if (isp->isp_type & ISP_HA_FC) {
2877 return;
2878 }
2879
2880 sdp = isp->isp_param;
2881 for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
2578 MAKNIB(0, 0), /* 0x4c: */
2579 MAKNIB(0, 0), /* 0x4d: */
2580 MAKNIB(0, 0), /* 0x4e: */
2581 MAKNIB(0, 0), /* 0x4f: */
2582 MAKNIB(0, 0), /* 0x50: */
2583 MAKNIB(0, 0), /* 0x51: */
2584 MAKNIB(0, 0), /* 0x52: */
2585 MAKNIB(0, 0), /* 0x53: */

--- 370 unchanged lines hidden (view full) ---

2956 isp->isp_update = 0;
2957
2958 if (isp->isp_type & ISP_HA_FC) {
2959 return;
2960 }
2961
2962 sdp = isp->isp_param;
2963 for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
2964 u_int16_t flags, period, offset, changed;
2965 int get;
2966
2882 if (sdp->isp_devparam[tgt].dev_enable == 0) {
2883 continue;
2884 }
2967 if (sdp->isp_devparam[tgt].dev_enable == 0) {
2968 continue;
2969 }
2885 if (sdp->isp_devparam[tgt].dev_update == 0) {
2970
2971 if (sdp->isp_devparam[tgt].dev_update) {
2972 mbs.param[0] = MBOX_SET_TARGET_PARAMS;
2973 mbs.param[2] = sdp->isp_devparam[tgt].dev_flags;
2974 mbs.param[3] =
2975 (sdp->isp_devparam[tgt].sync_offset << 8) |
2976 (sdp->isp_devparam[tgt].sync_period);
2977 sdp->isp_devparam[tgt].dev_update = 0;
2978 sdp->isp_devparam[tgt].dev_refresh = 1;
2979 isp->isp_update = 1;
2980 get = 0;
2981 } else if (sdp->isp_devparam[tgt].dev_refresh) {
2982 mbs.param[0] = MBOX_GET_TARGET_PARAMS;
2983 sdp->isp_devparam[tgt].dev_refresh = 0;
2984 get = 1;
2985 } else {
2886 continue;
2887 }
2986 continue;
2987 }
2888
2889 mbs.param[0] = MBOX_SET_TARGET_PARAMS;
2890 mbs.param[1] = tgt << 8;
2988 mbs.param[1] = tgt << 8;
2891 mbs.param[2] = sdp->isp_devparam[tgt].dev_flags;
2892 mbs.param[3] =
2893 (sdp->isp_devparam[tgt].sync_offset << 8) |
2894 (sdp->isp_devparam[tgt].sync_period);
2895
2896 IDPRINTF(3, ("\n%s: tgt %d cflags %x offset %x period %x\n",
2897 isp->isp_name, tgt, mbs.param[2], mbs.param[3] >> 8,
2898 mbs.param[3] & 0xff));
2899
2900 isp_mboxcmd(isp, &mbs);
2901 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
2989 isp_mboxcmd(isp, &mbs);
2990 if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
2902 PRINTF("%s: failed to change SCSI parameters for "
2903 "target %d\n", isp->isp_name, tgt);
2904 } else {
2905 char *wt;
2906 int x, flags;
2991 PRINTF("%s: failed to %cet SCSI parameters for "
2992 "target %d\n", isp->isp_name, (get)? 'g' : 's',
2993 tgt);
2994 continue;
2995 }
2907
2996
2908 flags = sdp->isp_devparam[tgt].cur_dflags =
2997 if (get == 0) {
2998 sdp->isp_devparam[tgt].cur_dflags =
2909 sdp->isp_devparam[tgt].dev_flags;
2999 sdp->isp_devparam[tgt].dev_flags;
3000 continue;
3001 }
3002 flags = mbs.param[2];
3003 period = mbs.param[3] & 0xff;
3004 offset = mbs.param[3] >> 8;
3005 if (sdp->isp_devparam[tgt].cur_dflags != flags ||
3006 sdp->isp_devparam[tgt].sync_period != period ||
3007 sdp->isp_devparam[tgt].sync_offset != offset) {
3008 IDPRINTF(3, ("%s: tgt %d flags 0x%x period %d "
3009 "off %d\n", isp->isp_name, tgt, flags,
3010 period, offset));
3011 changed = 1;
3012 } else {
3013 changed = 0;
3014 }
2910
3015
2911 x = sdp->isp_devparam[tgt].sync_period & 0xff;
2912 if (flags & DPARM_SYNC) {
2913 if (x == (ISP_20M_SYNCPARMS & 0xff)) {
2914 x = 20;
2915 } else if (x == (ISP_10M_SYNCPARMS & 0xff)) {
2916 x = 10;
2917 } else if (x == (ISP_08M_SYNCPARMS & 0xff)) {
2918 x = 8;
2919 } else if (x == (ISP_05M_SYNCPARMS & 0xff)) {
2920 x = 5;
2921 } else if (x == (ISP_04M_SYNCPARMS & 0xff)) {
2922 x = 4;
2923 } else {
2924 x = 0;
2925 }
2926 } else {
2927 x = 0;
2928 }
2929 switch (flags & (DPARM_WIDE|DPARM_TQING)) {
2930 case DPARM_WIDE:
2931 wt = ", 16 bit wide\n";
2932 break;
2933 case DPARM_TQING:
2934 wt = ", Tagged Queueing Enabled\n";
2935 break;
2936 case DPARM_WIDE|DPARM_TQING:
2937 wt = ", 16 bit wide, Tagged Queueing Enabled\n";
2938 break;
2939
2940 default:
2941 wt = "\n";
2942 break;
2943 }
2944 if (x) {
2945 IDPRINTF(3, ("%s: Target %d maximum Sync Mode "
2946 "at %dMHz%s", isp->isp_name, tgt, x, wt));
2947 } else {
2948 IDPRINTF(3, ("%s: Target %d Async Mode%s",
2949 isp->isp_name, tgt, wt));
2950 }
3016 sdp->isp_devparam[tgt].cur_dflags = flags;
3017 sdp->isp_devparam[tgt].dev_flags = flags;
3018 sdp->isp_devparam[tgt].sync_period = period;
3019 sdp->isp_devparam[tgt].sync_offset = offset;
3020 if (sdp->isp_devparam[tgt].dev_announced == 0 || changed) {
3021 if (isp_async(isp, ISPASYNC_NEW_TGT_PARAMS, &tgt))
3022 sdp->isp_devparam[tgt].dev_announced = 0;
3023 else
3024 sdp->isp_devparam[tgt].dev_announced = 1;
2951 }
3025 }
2952 sdp->isp_devparam[tgt].dev_update = 0;
2953 }
2954}
2955
2956static void
2957isp_setdfltparm(isp)
2958 struct ispsoftc *isp;
2959{
2960 int i, use_nvram;

--- 317 unchanged lines hidden (view full) ---

3278
3279 sdp->isp_selection_timeout =
3280 ISP_NVRAM_SELECTION_TIMEOUT(nvram_data);
3281
3282 sdp->isp_max_queue_depth =
3283 ISP_NVRAM_MAX_QUEUE_DEPTH(nvram_data);
3284
3285 sdp->isp_fast_mttr = ISP_NVRAM_FAST_MTTR_ENABLE(nvram_data);
3026 }
3027}
3028
3029static void
3030isp_setdfltparm(isp)
3031 struct ispsoftc *isp;
3032{
3033 int i, use_nvram;

--- 317 unchanged lines hidden (view full) ---

3351
3352 sdp->isp_selection_timeout =
3353 ISP_NVRAM_SELECTION_TIMEOUT(nvram_data);
3354
3355 sdp->isp_max_queue_depth =
3356 ISP_NVRAM_MAX_QUEUE_DEPTH(nvram_data);
3357
3358 sdp->isp_fast_mttr = ISP_NVRAM_FAST_MTTR_ENABLE(nvram_data);
3286
3287#if 0
3288 PRINTF("%s: fifo_threshold = 0x%x cbena%d dbena%d\n",
3289 isp->isp_name, sdp->isp_fifo_threshold,
3290 sdp->isp_cmd_dma_burst_enable,
3291 sdp->isp_data_dma_burst_enabl);
3292#endif
3293 for (i = 0; i < 16; i++) {
3294 sdp->isp_devparam[i].dev_enable =

--- 155 unchanged lines hidden --- 		3359#if 0
3360 PRINTF("%s: fifo_threshold = 0x%x cbena%d dbena%d\n",
3361 isp->isp_name, sdp->isp_fifo_threshold,
3362 sdp->isp_cmd_dma_burst_enable,
3363 sdp->isp_data_dma_burst_enabl);
3364#endif
3365 for (i = 0; i < 16; i++) {
3366 sdp->isp_devparam[i].dev_enable =

--- 155 unchanged lines hidden ---