if_gem.c (9f012efb63cbe4fbcce1c58336d7fc97830650f8) if_gem.c (8defc88c1345f4c048a05e6f20f60ed59d204129)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3 *
4 * Copyright (C) 2001 Eduardo Horvath.
5 * Copyright (c) 2001-2003 Thomas Moestl
6 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
7 * All rights reserved.
8 *

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94 * the hardware doesn't compensate the checksum for UDP datagram which
95 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
96 * by default. It can be reactivated by setting special link option
97 * link0 with ifconfig(8).
98 */
99#define GEM_CSUM_FEATURES (CSUM_TCP)
100
101static int gem_add_rxbuf(struct gem_softc *sc, int idx);
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3 *
4 * Copyright (C) 2001 Eduardo Horvath.
5 * Copyright (c) 2001-2003 Thomas Moestl
6 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
7 * All rights reserved.
8 *

--- 85 unchanged lines hidden (view full) ---

94 * the hardware doesn't compensate the checksum for UDP datagram which
95 * can yield to 0x0. As a safe guard, UDP checksum offload is disabled
96 * by default. It can be reactivated by setting special link option
97 * link0 with ifconfig(8).
98 */
99#define GEM_CSUM_FEATURES (CSUM_TCP)
100
101static int gem_add_rxbuf(struct gem_softc *sc, int idx);
102static int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r,
103 uint32_t clr, uint32_t set);
102static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr,
103 uint32_t set);
104static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
105 int nsegs, int error);
106static int gem_disable_rx(struct gem_softc *sc);
107static int gem_disable_tx(struct gem_softc *sc);
108static void gem_eint(struct gem_softc *sc, u_int status);
109static void gem_init(void *xsc);
110static void gem_init_locked(struct gem_softc *sc);
111static void gem_init_regs(struct gem_softc *sc);

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136DRIVER_MODULE(miibus, gem, miibus_driver, 0, 0);
137MODULE_DEPEND(gem, miibus, 1, 1, 1);
138
139#ifdef GEM_DEBUG
140#include <sys/ktr.h>
141#define KTR_GEM KTR_SPARE2
142#endif
143
104static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs,
105 int nsegs, int error);
106static int gem_disable_rx(struct gem_softc *sc);
107static int gem_disable_tx(struct gem_softc *sc);
108static void gem_eint(struct gem_softc *sc, u_int status);
109static void gem_init(void *xsc);
110static void gem_init_locked(struct gem_softc *sc);
111static void gem_init_regs(struct gem_softc *sc);

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136DRIVER_MODULE(miibus, gem, miibus_driver, 0, 0);
137MODULE_DEPEND(gem, miibus, 1, 1, 1);
138
139#ifdef GEM_DEBUG
140#include <sys/ktr.h>
141#define KTR_GEM KTR_SPARE2
142#endif
143
144#define GEM_BANK1_BITWAIT(sc, r, clr, set) \
145 gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set))
146#define GEM_BANK2_BITWAIT(sc, r, clr, set) \
147 gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set))
148
149int
150gem_attach(struct gem_softc *sc)
151{
152 struct gem_txsoft *txs;
153 if_t ifp;
154 int error, i, phy;
155 uint32_t v;
156

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268 }
269 sc->sc_rxsoft[i].rxs_mbuf = NULL;
270 }
271
272 /* Bypass probing PHYs if we already know for sure to use a SERDES. */
273 if ((sc->sc_flags & GEM_SERDES) != 0)
274 goto serdes;
275
144int
145gem_attach(struct gem_softc *sc)
146{
147 struct gem_txsoft *txs;
148 if_t ifp;
149 int error, i, phy;
150 uint32_t v;
151

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263 }
264 sc->sc_rxsoft[i].rxs_mbuf = NULL;
265 }
266
267 /* Bypass probing PHYs if we already know for sure to use a SERDES. */
268 if ((sc->sc_flags & GEM_SERDES) != 0)
269 goto serdes;
270
276 /* Bad things will happen when touching this register on ERI. */
277 if (sc->sc_variant != GEM_SUN_ERI) {
278 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
279 GEM_MII_DATAPATH_MII);
280 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
281 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
282 }
271 GEM_WRITE_4(sc, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII);
272 GEM_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
273 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
283
284 gem_mifinit(sc);
285
286 /*
287 * Look for an external PHY.
288 */
289 error = ENXIO;
274
275 gem_mifinit(sc);
276
277 /*
278 * Look for an external PHY.
279 */
280 error = ENXIO;
290 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG);
281 v = GEM_READ_4(sc, GEM_MIF_CONFIG);
291 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
292 v |= GEM_MIF_CONFIG_PHY_SEL;
282 if ((v & GEM_MIF_CONFIG_MDI1) != 0) {
283 v |= GEM_MIF_CONFIG_PHY_SEL;
293 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
294 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
284 GEM_WRITE_4(sc, GEM_MIF_CONFIG, v);
285 GEM_BARRIER(sc, GEM_MIF_CONFIG, 4,
295 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
286 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
296 switch (sc->sc_variant) {
297 case GEM_SUN_ERI:
298 phy = GEM_PHYAD_EXTERNAL;
299 break;
300 default:
301 phy = MII_PHY_ANY;
302 break;
303 }
304 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
287 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
305 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy,
306 MII_OFFSET_ANY, MIIF_DOPAUSE);
288 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK,
289 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
307 }
308
309 /*
310 * Fall back on an internal PHY if no external PHY was found.
311 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be
312 * trusted when the firmware has powered down the chip.
313 */
314 if (error != 0 &&
315 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) {
316 v &= ~GEM_MIF_CONFIG_PHY_SEL;
290 }
291
292 /*
293 * Fall back on an internal PHY if no external PHY was found.
294 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be
295 * trusted when the firmware has powered down the chip.
296 */
297 if (error != 0 &&
298 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) {
299 v &= ~GEM_MIF_CONFIG_PHY_SEL;
317 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v);
318 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
300 GEM_WRITE_4(sc, GEM_MIF_CONFIG, v);
301 GEM_BARRIER(sc, GEM_MIF_CONFIG, 4,
319 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
320 switch (sc->sc_variant) {
302 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
303 switch (sc->sc_variant) {
321 case GEM_SUN_ERI:
322 case GEM_APPLE_K2_GMAC:
323 phy = GEM_PHYAD_INTERNAL;
324 break;
325 case GEM_APPLE_GMAC:
326 phy = GEM_PHYAD_EXTERNAL;
327 break;
328 default:
329 phy = MII_PHY_ANY;

--- 4 unchanged lines hidden (view full) ---

334 MII_OFFSET_ANY, MIIF_DOPAUSE);
335 }
336
337 /*
338 * Try the external PCS SERDES if we didn't find any PHYs.
339 */
340 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
341 serdes:
304 case GEM_APPLE_K2_GMAC:
305 phy = GEM_PHYAD_INTERNAL;
306 break;
307 case GEM_APPLE_GMAC:
308 phy = GEM_PHYAD_EXTERNAL;
309 break;
310 default:
311 phy = MII_PHY_ANY;

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316 MII_OFFSET_ANY, MIIF_DOPAUSE);
317 }
318
319 /*
320 * Try the external PCS SERDES if we didn't find any PHYs.
321 */
322 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) {
323 serdes:
342 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
324 GEM_WRITE_4(sc, GEM_MII_DATAPATH_MODE,
343 GEM_MII_DATAPATH_SERDES);
325 GEM_MII_DATAPATH_SERDES);
344 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
326 GEM_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4,
345 BUS_SPACE_BARRIER_WRITE);
327 BUS_SPACE_BARRIER_WRITE);
346 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
328 GEM_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
347 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
329 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
348 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
330 GEM_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
349 BUS_SPACE_BARRIER_WRITE);
331 BUS_SPACE_BARRIER_WRITE);
350 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
351 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
332 GEM_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
333 GEM_BARRIER(sc, GEM_MII_CONFIG, 4,
352 BUS_SPACE_BARRIER_WRITE);
353 sc->sc_flags |= GEM_SERDES;
354 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
355 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK,
356 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
357 }
358 if (error != 0) {
359 device_printf(sc->sc_dev, "attaching PHYs failed\n");

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364 /*
365 * From this point forward, the attachment cannot fail. A failure
366 * before this point releases all resources that may have been
367 * allocated.
368 */
369
370 /* Get RX FIFO size. */
371 sc->sc_rxfifosize = 64 *
334 BUS_SPACE_BARRIER_WRITE);
335 sc->sc_flags |= GEM_SERDES;
336 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
337 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK,
338 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
339 }
340 if (error != 0) {
341 device_printf(sc->sc_dev, "attaching PHYs failed\n");

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346 /*
347 * From this point forward, the attachment cannot fail. A failure
348 * before this point releases all resources that may have been
349 * allocated.
350 */
351
352 /* Get RX FIFO size. */
353 sc->sc_rxfifosize = 64 *
372 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE);
354 GEM_READ_4(sc, GEM_RX_FIFO_SIZE);
373
374 /* Get TX FIFO size. */
355
356 /* Get TX FIFO size. */
375 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE);
357 v = GEM_READ_4(sc, GEM_TX_FIFO_SIZE);
376 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
377 sc->sc_rxfifosize / 1024, v / 16);
378
379 /* Attach the interface. */
380 ether_ifattach(ifp, sc->sc_enaddr);
381
382 /*
383 * Tell the upper layer(s) we support long frames/checksum offloads.

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564 uint32_t v;
565
566 GEM_LOCK_ASSERT(sc, MA_OWNED);
567
568 /*
569 * Unload collision and error counters.
570 */
571 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
358 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
359 sc->sc_rxfifosize / 1024, v / 16);
360
361 /* Attach the interface. */
362 ether_ifattach(ifp, sc->sc_enaddr);
363
364 /*
365 * Tell the upper layer(s) we support long frames/checksum offloads.

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546 uint32_t v;
547
548 GEM_LOCK_ASSERT(sc, MA_OWNED);
549
550 /*
551 * Unload collision and error counters.
552 */
553 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
572 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) +
573 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT));
574 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) +
575 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT);
554 GEM_READ_4(sc, GEM_MAC_NORM_COLL_CNT) +
555 GEM_READ_4(sc, GEM_MAC_FIRST_COLL_CNT));
556 v = GEM_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) +
557 GEM_READ_4(sc, GEM_MAC_LATE_COLL_CNT);
576 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v);
577 if_inc_counter(ifp, IFCOUNTER_OERRORS, v);
578 if_inc_counter(ifp, IFCOUNTER_IERRORS,
558 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v);
559 if_inc_counter(ifp, IFCOUNTER_OERRORS, v);
560 if_inc_counter(ifp, IFCOUNTER_IERRORS,
579 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) +
580 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) +
581 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) +
582 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL));
561 GEM_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) +
562 GEM_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) +
563 GEM_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) +
564 GEM_READ_4(sc, GEM_MAC_RX_CODE_VIOL));
583
584 /*
585 * Then clear the hardware counters.
586 */
565
566 /*
567 * Then clear the hardware counters.
568 */
587 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
588 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
589 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
590 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
591 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
592 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
593 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
594 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
569 GEM_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
570 GEM_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
571 GEM_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
572 GEM_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
573 GEM_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
574 GEM_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
575 GEM_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
576 GEM_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
595
596 mii_tick(sc->sc_mii);
597
598 if (gem_watchdog(sc) == EJUSTRETURN)
599 return;
600
601 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
602}
603
604static int
577
578 mii_tick(sc->sc_mii);
579
580 if (gem_watchdog(sc) == EJUSTRETURN)
581 return;
582
583 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
584}
585
586static int
605gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr,
606 uint32_t set)
587gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
607{
608 int i;
609 uint32_t reg;
610
611 for (i = GEM_TRIES; i--; DELAY(100)) {
588{
589 int i;
590 uint32_t reg;
591
592 for (i = GEM_TRIES; i--; DELAY(100)) {
612 reg = GEM_BANKN_READ_M(bank, 4, sc, r);
593 reg = GEM_READ_4(sc, r);
613 if ((reg & clr) == 0 && (reg & set) == set)
614 return (1);
615 }
616 return (0);
617}
618
619static void
620gem_reset(struct gem_softc *sc)
621{
622
623#ifdef GEM_DEBUG
624 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
625#endif
626 gem_reset_rx(sc);
627 gem_reset_tx(sc);
628
629 /* Do a full reset. */
594 if ((reg & clr) == 0 && (reg & set) == set)
595 return (1);
596 }
597 return (0);
598}
599
600static void
601gem_reset(struct gem_softc *sc)
602{
603
604#ifdef GEM_DEBUG
605 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
606#endif
607 gem_reset_rx(sc);
608 gem_reset_tx(sc);
609
610 /* Do a full reset. */
630 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX |
631 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
632 GEM_RESET_CLSZ_SHFT : 0));
633 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
611 GEM_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
612 GEM_BARRIER(sc, GEM_RESET, 4,
634 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
613 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
635 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
614 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
636 device_printf(sc->sc_dev, "cannot reset device\n");
637}
638
639static void
640gem_rxdrain(struct gem_softc *sc)
641{
642 struct gem_rxsoft *rxs;
643 int i;

--- 60 unchanged lines hidden (view full) ---

704gem_reset_rx(struct gem_softc *sc)
705{
706
707 /*
708 * Resetting while DMA is in progress can cause a bus hang, so we
709 * disable DMA first.
710 */
711 (void)gem_disable_rx(sc);
615 device_printf(sc->sc_dev, "cannot reset device\n");
616}
617
618static void
619gem_rxdrain(struct gem_softc *sc)
620{
621 struct gem_rxsoft *rxs;
622 int i;

--- 60 unchanged lines hidden (view full) ---

683gem_reset_rx(struct gem_softc *sc)
684{
685
686 /*
687 * Resetting while DMA is in progress can cause a bus hang, so we
688 * disable DMA first.
689 */
690 (void)gem_disable_rx(sc);
712 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0);
713 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4,
691 GEM_WRITE_4(sc, GEM_RX_CONFIG, 0);
692 GEM_BARRIER(sc, GEM_RX_CONFIG, 4,
714 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
693 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
715 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
694 if (!gem_bitwait(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0))
716 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
717
718 /* Wait 5ms extra. */
719 DELAY(5000);
720
721 /* Reset the ERX. */
695 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
696
697 /* Wait 5ms extra. */
698 DELAY(5000);
699
700 /* Reset the ERX. */
722 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX |
723 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
724 GEM_RESET_CLSZ_SHFT : 0));
725 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
701 GEM_WRITE_4(sc, GEM_RESET, GEM_RESET_RX);
702 GEM_BARRIER(sc, GEM_RESET, 4,
726 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
703 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
727 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX, 0)) {
704 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX, 0)) {
728 device_printf(sc->sc_dev, "cannot reset receiver\n");
729 return (1);
730 }
731
732 /* Finally, reset RX MAC. */
705 device_printf(sc->sc_dev, "cannot reset receiver\n");
706 return (1);
707 }
708
709 /* Finally, reset RX MAC. */
733 GEM_BANK1_WRITE_4(sc, GEM_MAC_RXRESET, 1);
734 GEM_BANK1_BARRIER(sc, GEM_MAC_RXRESET, 4,
710 GEM_WRITE_4(sc, GEM_MAC_RXRESET, 1);
711 GEM_BARRIER(sc, GEM_MAC_RXRESET, 4,
735 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
712 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
736 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RXRESET, 1, 0)) {
713 if (!gem_bitwait(sc, GEM_MAC_RXRESET, 1, 0)) {
737 device_printf(sc->sc_dev, "cannot reset RX MAC\n");
738 return (1);
739 }
740
741 return (0);
742}
743
744/*

--- 14 unchanged lines hidden (view full) ---

759 }
760 for (i = 0; i < GEM_NRXDESC; i++)
761 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
762 GEM_UPDATE_RXDESC(sc, i);
763 sc->sc_rxptr = 0;
764 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
765
766 /* NOTE: we use only 32-bit DMA addresses here. */
714 device_printf(sc->sc_dev, "cannot reset RX MAC\n");
715 return (1);
716 }
717
718 return (0);
719}
720
721/*

--- 14 unchanged lines hidden (view full) ---

736 }
737 for (i = 0; i < GEM_NRXDESC; i++)
738 if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
739 GEM_UPDATE_RXDESC(sc, i);
740 sc->sc_rxptr = 0;
741 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
742
743 /* NOTE: we use only 32-bit DMA addresses here. */
767 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
768 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
769 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
770 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
744 GEM_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
745 GEM_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
746 GEM_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
747 GEM_WRITE_4(sc, GEM_RX_CONFIG,
771 gem_ringsize(GEM_NRXDESC /* XXX */) |
772 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
773 GEM_RX_CONFIG_CXM_START_SHFT) |
774 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
775 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT));
748 gem_ringsize(GEM_NRXDESC /* XXX */) |
749 ((ETHER_HDR_LEN + sizeof(struct ip)) <<
750 GEM_RX_CONFIG_CXM_START_SHFT) |
751 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
752 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT));
776 /* Adjusting for the SBus clock probably isn't worth the fuzz. */
777 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
753 GEM_WRITE_4(sc, GEM_RX_BLANKING,
778 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
779 GEM_RX_BLANKING_TIME_SHIFT) | 6);
754 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
755 GEM_RX_BLANKING_TIME_SHIFT) | 6);
780 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
756 GEM_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
781 (3 * sc->sc_rxfifosize / 256) |
782 ((sc->sc_rxfifosize / 256) << 12));
757 (3 * sc->sc_rxfifosize / 256) |
758 ((sc->sc_rxfifosize / 256) << 12));
783 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
784 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
785 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
759 GEM_WRITE_4(sc, GEM_RX_CONFIG,
760 GEM_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN);
761 GEM_WRITE_4(sc, GEM_MAC_RX_MASK,
786 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
787 /*
788 * Clear the RX filter and reprogram it. This will also set the
789 * current RX MAC configuration and enable it.
790 */
791 gem_setladrf(sc);
792}
793
794static int
795gem_reset_tx(struct gem_softc *sc)
796{
797
798 /*
799 * Resetting while DMA is in progress can cause a bus hang, so we
800 * disable DMA first.
801 */
802 (void)gem_disable_tx(sc);
762 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
763 /*
764 * Clear the RX filter and reprogram it. This will also set the
765 * current RX MAC configuration and enable it.
766 */
767 gem_setladrf(sc);
768}
769
770static int
771gem_reset_tx(struct gem_softc *sc)
772{
773
774 /*
775 * Resetting while DMA is in progress can cause a bus hang, so we
776 * disable DMA first.
777 */
778 (void)gem_disable_tx(sc);
803 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0);
804 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4,
779 GEM_WRITE_4(sc, GEM_TX_CONFIG, 0);
780 GEM_BARRIER(sc, GEM_TX_CONFIG, 4,
805 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
781 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
806 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
782 if (!gem_bitwait(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0))
807 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
808
809 /* Wait 5ms extra. */
810 DELAY(5000);
811
812 /* Finally, reset the ETX. */
783 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
784
785 /* Wait 5ms extra. */
786 DELAY(5000);
787
788 /* Finally, reset the ETX. */
813 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX |
814 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE <<
815 GEM_RESET_CLSZ_SHFT : 0));
816 GEM_BANK2_BARRIER(sc, GEM_RESET, 4,
789 GEM_WRITE_4(sc, GEM_RESET, GEM_RESET_TX);
790 GEM_BARRIER(sc, GEM_RESET, 4,
817 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
791 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
818 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_TX, 0)) {
792 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
819 device_printf(sc->sc_dev, "cannot reset transmitter\n");
820 return (1);
821 }
822 return (0);
823}
824
825static int
826gem_disable_rx(struct gem_softc *sc)
827{
828
793 device_printf(sc->sc_dev, "cannot reset transmitter\n");
794 return (1);
795 }
796 return (0);
797}
798
799static int
800gem_disable_rx(struct gem_softc *sc)
801{
802
829 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
830 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE);
831 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
803 GEM_WRITE_4(sc, GEM_MAC_RX_CONFIG,
804 GEM_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE);
805 GEM_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
832 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
806 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
833 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
807 if (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
834 return (1);
835 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
836 return (0);
837}
838
839static int
840gem_disable_tx(struct gem_softc *sc)
841{
842
808 return (1);
809 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
810 return (0);
811}
812
813static int
814gem_disable_tx(struct gem_softc *sc)
815{
816
843 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
844 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE);
845 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4,
817 GEM_WRITE_4(sc, GEM_MAC_TX_CONFIG,
818 GEM_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE);
819 GEM_BARRIER(sc, GEM_MAC_TX_CONFIG, 4,
846 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
820 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
847 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
821 if (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
848 return (1);
849 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
850 return (0);
851}
852
853static int
854gem_meminit(struct gem_softc *sc)
855{

--- 124 unchanged lines hidden (view full) ---

980
981 /* step 4. TX MAC registers & counters */
982 gem_init_regs(sc);
983
984 /* step 5. RX MAC registers & counters */
985
986 /* step 6 & 7. Program Descriptor Ring Base Addresses. */
987 /* NOTE: we use only 32-bit DMA addresses here. */
822 return (1);
823 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
824 return (0);
825}
826
827static int
828gem_meminit(struct gem_softc *sc)
829{

--- 124 unchanged lines hidden (view full) ---

954
955 /* step 4. TX MAC registers & counters */
956 gem_init_regs(sc);
957
958 /* step 5. RX MAC registers & counters */
959
960 /* step 6 & 7. Program Descriptor Ring Base Addresses. */
961 /* NOTE: we use only 32-bit DMA addresses here. */
988 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0);
989 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
962 GEM_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0);
963 GEM_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
990
964
991 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
992 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
965 GEM_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0);
966 GEM_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
993#ifdef GEM_DEBUG
994 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
995 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
996#endif
997
998 /* step 8. Global Configuration & Interrupt Mask */
999
1000 /*
1001 * Set the internal arbitration to "infinite" bursts of the
1002 * maximum length of 31 * 64 bytes so DMA transfers aren't
1003 * split up in cache line size chunks. This greatly improves
1004 * RX performance.
1005 * Enable silicon bug workarounds for the Apple variants.
1006 */
967#ifdef GEM_DEBUG
968 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx",
969 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
970#endif
971
972 /* step 8. Global Configuration & Interrupt Mask */
973
974 /*
975 * Set the internal arbitration to "infinite" bursts of the
976 * maximum length of 31 * 64 bytes so DMA transfers aren't
977 * split up in cache line size chunks. This greatly improves
978 * RX performance.
979 * Enable silicon bug workarounds for the Apple variants.
980 */
1007 GEM_BANK1_WRITE_4(sc, GEM_CONFIG,
981 GEM_WRITE_4(sc, GEM_CONFIG,
1008 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
982 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
1009 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF :
1010 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ?
983 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
1011 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
1012
984 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
985
1013 GEM_BANK1_WRITE_4(sc, GEM_INTMASK,
986 GEM_WRITE_4(sc, GEM_INTMASK,
1014 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
1015 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
1016 GEM_INTR_BERR
1017#ifdef GEM_DEBUG
1018 | GEM_INTR_PCS | GEM_INTR_MIF
1019#endif
1020 ));
987 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE |
988 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR |
989 GEM_INTR_BERR
990#ifdef GEM_DEBUG
991 | GEM_INTR_PCS | GEM_INTR_MIF
992#endif
993 ));
1021 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK,
994 GEM_WRITE_4(sc, GEM_MAC_RX_MASK,
1022 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
995 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
1023 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK,
996 GEM_WRITE_4(sc, GEM_MAC_TX_MASK,
1024 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
1025 GEM_MAC_TX_PEAK_EXP);
1026#ifdef GEM_DEBUG
997 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
998 GEM_MAC_TX_PEAK_EXP);
999#ifdef GEM_DEBUG
1027 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1000 GEM_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1028 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
1029#else
1001 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME));
1002#else
1030 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1003 GEM_WRITE_4(sc, GEM_MAC_CONTROL_MASK,
1031 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
1032#endif
1033
1034 /* step 9. ETX Configuration: use mostly default values. */
1035
1036 /* Enable DMA. */
1037 v = gem_ringsize(GEM_NTXDESC);
1038 /* Set TX FIFO threshold and enable DMA. */
1004 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
1005#endif
1006
1007 /* step 9. ETX Configuration: use mostly default values. */
1008
1009 /* Enable DMA. */
1010 v = gem_ringsize(GEM_NTXDESC);
1011 /* Set TX FIFO threshold and enable DMA. */
1039 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) &
1040 GEM_TX_CONFIG_TXFIFO_TH;
1041 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN);
1012 v |= (0x4ff << 10) & GEM_TX_CONFIG_TXFIFO_TH;
1013 GEM_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN);
1042
1043 /* step 10. ERX Configuration */
1044
1045 /* Encode Receive Descriptor ring size. */
1046 v = gem_ringsize(GEM_NRXDESC /* XXX */);
1047 /* RX TCP/UDP checksum offset */
1048 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1049 GEM_RX_CONFIG_CXM_START_SHFT);
1050 /* Set RX FIFO threshold, set first byte offset and enable DMA. */
1014
1015 /* step 10. ERX Configuration */
1016
1017 /* Encode Receive Descriptor ring size. */
1018 v = gem_ringsize(GEM_NRXDESC /* XXX */);
1019 /* RX TCP/UDP checksum offset */
1020 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) <<
1021 GEM_RX_CONFIG_CXM_START_SHFT);
1022 /* Set RX FIFO threshold, set first byte offset and enable DMA. */
1051 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG,
1023 GEM_WRITE_4(sc, GEM_RX_CONFIG,
1052 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
1053 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) |
1054 GEM_RX_CONFIG_RXDMA_EN);
1055
1024 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
1025 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) |
1026 GEM_RX_CONFIG_RXDMA_EN);
1027
1056 /* Adjusting for the SBus clock probably isn't worth the fuzz. */
1057 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING,
1028 GEM_WRITE_4(sc, GEM_RX_BLANKING,
1058 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
1059 GEM_RX_BLANKING_TIME_SHIFT) | 6);
1060
1061 /*
1062 * The following value is for an OFF Threshold of about 3/4 full
1063 * and an ON Threshold of 1/4 full.
1064 */
1029 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) <<
1030 GEM_RX_BLANKING_TIME_SHIFT) | 6);
1031
1032 /*
1033 * The following value is for an OFF Threshold of about 3/4 full
1034 * and an ON Threshold of 1/4 full.
1035 */
1065 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
1036 GEM_WRITE_4(sc, GEM_RX_PAUSE_THRESH,
1066 (3 * sc->sc_rxfifosize / 256) |
1067 ((sc->sc_rxfifosize / 256) << 12));
1068
1069 /* step 11. Configure Media. */
1070
1071 /* step 12. RX_MAC Configuration Register */
1037 (3 * sc->sc_rxfifosize / 256) |
1038 ((sc->sc_rxfifosize / 256) << 12));
1039
1040 /* step 11. Configure Media. */
1041
1042 /* step 12. RX_MAC Configuration Register */
1072 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG);
1043 v = GEM_READ_4(sc, GEM_MAC_RX_CONFIG);
1073 v &= ~GEM_MAC_RX_ENABLE;
1074 v |= GEM_MAC_RX_STRIP_CRC;
1075 sc->sc_mac_rxcfg = v;
1076 /*
1077 * Clear the RX filter and reprogram it. This will also set the
1078 * current RX MAC configuration and enable it.
1079 */
1080 gem_setladrf(sc);
1081
1082 /* step 13. TX_MAC Configuration Register */
1044 v &= ~GEM_MAC_RX_ENABLE;
1045 v |= GEM_MAC_RX_STRIP_CRC;
1046 sc->sc_mac_rxcfg = v;
1047 /*
1048 * Clear the RX filter and reprogram it. This will also set the
1049 * current RX MAC configuration and enable it.
1050 */
1051 gem_setladrf(sc);
1052
1053 /* step 13. TX_MAC Configuration Register */
1083 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG);
1054 v = GEM_READ_4(sc, GEM_MAC_TX_CONFIG);
1084 v |= GEM_MAC_TX_ENABLE;
1085 (void)gem_disable_tx(sc);
1055 v |= GEM_MAC_TX_ENABLE;
1056 (void)gem_disable_tx(sc);
1086 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v);
1057 GEM_WRITE_4(sc, GEM_MAC_TX_CONFIG, v);
1087
1088 /* step 14. Issue Transmit Pending command. */
1089
1090 /* step 15. Give the receiver a swift kick. */
1058
1059 /* step 14. Issue Transmit Pending command. */
1060
1061 /* step 15. Give the receiver a swift kick. */
1091 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
1062 GEM_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4);
1092
1093 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1094 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1095
1096 mii_mediachg(sc->sc_mii);
1097
1098 /* Start the one second timer. */
1099 sc->sc_wdog_timer = 0;

--- 85 unchanged lines hidden (view full) ---

1185 txs->txs_ndescs = nsegs;
1186 txs->txs_firstdesc = sc->sc_txnext;
1187 nexttx = txs->txs_firstdesc;
1188 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) {
1189#ifdef GEM_DEBUG
1190 CTR6(KTR_GEM,
1191 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1192 __func__, seg, nexttx, txsegs[seg].ds_len,
1063
1064 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1065 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1066
1067 mii_mediachg(sc->sc_mii);
1068
1069 /* Start the one second timer. */
1070 sc->sc_wdog_timer = 0;

--- 85 unchanged lines hidden (view full) ---

1156 txs->txs_ndescs = nsegs;
1157 txs->txs_firstdesc = sc->sc_txnext;
1158 nexttx = txs->txs_firstdesc;
1159 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) {
1160#ifdef GEM_DEBUG
1161 CTR6(KTR_GEM,
1162 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1163 __func__, seg, nexttx, txsegs[seg].ds_len,
1193 txsegs[seg].ds_addr,
1194 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr));
1164 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr));
1195#endif
1165#endif
1196 sc->sc_txdescs[nexttx].gd_addr =
1197 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr);
1166 sc->sc_txdescs[nexttx].gd_addr = htole64(txsegs[seg].ds_addr);
1198 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE,
1199 ("%s: segment size too large!", __func__));
1200 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE;
1167 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE,
1168 ("%s: segment size too large!", __func__));
1169 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE;
1201 sc->sc_txdescs[nexttx].gd_flags =
1202 GEM_DMA_WRITE(sc, flags | cflags);
1170 sc->sc_txdescs[nexttx].gd_flags = htole64(flags | cflags);
1203 txs->txs_lastdesc = nexttx;
1204 }
1205
1206 /* Set EOP on the last descriptor. */
1207#ifdef GEM_DEBUG
1208 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d",
1209 __func__, seg, nexttx);
1210#endif
1211 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |=
1171 txs->txs_lastdesc = nexttx;
1172 }
1173
1174 /* Set EOP on the last descriptor. */
1175#ifdef GEM_DEBUG
1176 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d",
1177 __func__, seg, nexttx);
1178#endif
1179 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |=
1212 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET);
1180 htole64(GEM_TD_END_OF_PACKET);
1213
1214 /* Lastly set SOP on the first descriptor. */
1215#ifdef GEM_DEBUG
1216 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d",
1217 __func__, seg, nexttx);
1218#endif
1219 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
1220 sc->sc_txwin = 0;
1221 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1181
1182 /* Lastly set SOP on the first descriptor. */
1183#ifdef GEM_DEBUG
1184 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d",
1185 __func__, seg, nexttx);
1186#endif
1187 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
1188 sc->sc_txwin = 0;
1189 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1222 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME |
1223 GEM_TD_START_OF_PACKET);
1190 htole64(GEM_TD_INTERRUPT_ME | GEM_TD_START_OF_PACKET);
1224 } else
1225 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1191 } else
1192 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |=
1226 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET);
1193 htole64(GEM_TD_START_OF_PACKET);
1227
1228 /* Sync the DMA map. */
1229 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1230 BUS_DMASYNC_PREWRITE);
1231
1232#ifdef GEM_DEBUG
1233 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1234 __func__, txs->txs_firstdesc, txs->txs_lastdesc,

--- 14 unchanged lines hidden (view full) ---

1249{
1250 const u_char *laddr = if_getlladdr(sc->sc_ifp);
1251
1252 GEM_LOCK_ASSERT(sc, MA_OWNED);
1253
1254 /* These registers are not cleared on reset. */
1255 if ((sc->sc_flags & GEM_INITED) == 0) {
1256 /* magic values */
1194
1195 /* Sync the DMA map. */
1196 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1197 BUS_DMASYNC_PREWRITE);
1198
1199#ifdef GEM_DEBUG
1200 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1201 __func__, txs->txs_firstdesc, txs->txs_lastdesc,

--- 14 unchanged lines hidden (view full) ---

1216{
1217 const u_char *laddr = if_getlladdr(sc->sc_ifp);
1218
1219 GEM_LOCK_ASSERT(sc, MA_OWNED);
1220
1221 /* These registers are not cleared on reset. */
1222 if ((sc->sc_flags & GEM_INITED) == 0) {
1223 /* magic values */
1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0);
1258 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8);
1259 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4);
1224 GEM_WRITE_4(sc, GEM_MAC_IPG0, 0);
1225 GEM_WRITE_4(sc, GEM_MAC_IPG1, 8);
1226 GEM_WRITE_4(sc, GEM_MAC_IPG2, 4);
1260
1261 /* min frame length */
1227
1228 /* min frame length */
1262 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1229 GEM_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1263 /* max frame length and max burst size */
1230 /* max frame length and max burst size */
1264 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME,
1231 GEM_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME,
1265 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1266
1267 /* more magic values */
1232 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16));
1233
1234 /* more magic values */
1268 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7);
1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4);
1270 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1271 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808);
1235 GEM_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7);
1236 GEM_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4);
1237 GEM_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1238 GEM_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808);
1272
1273 /* random number seed */
1239
1240 /* random number seed */
1274 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED,
1241 GEM_WRITE_4(sc, GEM_MAC_RANDOM_SEED,
1275 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1276
1277 /* secondary MAC address: 0:0:0:0:0:0 */
1242 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1243
1244 /* secondary MAC address: 0:0:0:0:0:0 */
1278 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0);
1279 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0);
1280 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0);
1245 GEM_WRITE_4(sc, GEM_MAC_ADDR3, 0);
1246 GEM_WRITE_4(sc, GEM_MAC_ADDR4, 0);
1247 GEM_WRITE_4(sc, GEM_MAC_ADDR5, 0);
1281
1282 /* MAC control address: 01:80:c2:00:00:01 */
1248
1249 /* MAC control address: 01:80:c2:00:00:01 */
1283 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001);
1284 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200);
1285 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180);
1250 GEM_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001);
1251 GEM_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200);
1252 GEM_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180);
1286
1287 /* MAC filter address: 0:0:0:0:0:0 */
1253
1254 /* MAC filter address: 0:0:0:0:0:0 */
1288 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0);
1289 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0);
1290 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0);
1291 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0);
1292 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0);
1255 GEM_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0);
1256 GEM_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0);
1257 GEM_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0);
1258 GEM_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0);
1259 GEM_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0);
1293
1294 sc->sc_flags |= GEM_INITED;
1295 }
1296
1297 /* Counters need to be zeroed. */
1260
1261 sc->sc_flags |= GEM_INITED;
1262 }
1263
1264 /* Counters need to be zeroed. */
1298 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
1299 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
1300 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
1301 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
1302 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0);
1303 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0);
1304 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0);
1305 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
1306 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
1307 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
1308 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
1265 GEM_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0);
1266 GEM_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0);
1267 GEM_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0);
1268 GEM_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0);
1269 GEM_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0);
1270 GEM_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0);
1271 GEM_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0);
1272 GEM_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0);
1273 GEM_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0);
1274 GEM_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0);
1275 GEM_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0);
1309
1310 /* Set XOFF PAUSE time. */
1276
1277 /* Set XOFF PAUSE time. */
1311 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1278 GEM_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1312
1313 /* Set the station address. */
1279
1280 /* Set the station address. */
1314 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1315 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1316 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1281 GEM_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1282 GEM_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1283 GEM_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1317
1318 /* Enable MII outputs. */
1284
1285 /* Enable MII outputs. */
1319 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
1286 GEM_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA);
1320}
1321
1322static void
1323gem_start(if_t ifp)
1324{
1325 struct gem_softc *sc = if_getsoftc(ifp);
1326
1327 GEM_LOCK(sc);

--- 11 unchanged lines hidden (view full) ---

1339 * should be incremented in multiples of 4 (the DMA engine fetches/
1340 * updates descriptors in batches of 4).
1341 */
1342#ifdef GEM_DEBUG
1343 CTR3(KTR_GEM, "%s: %s: kicking TX %d",
1344 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1345#endif
1346 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1287}
1288
1289static void
1290gem_start(if_t ifp)
1291{
1292 struct gem_softc *sc = if_getsoftc(ifp);
1293
1294 GEM_LOCK(sc);

--- 11 unchanged lines hidden (view full) ---

1306 * should be incremented in multiples of 4 (the DMA engine fetches/
1307 * updates descriptors in batches of 4).
1308 */
1309#ifdef GEM_DEBUG
1310 CTR3(KTR_GEM, "%s: %s: kicking TX %d",
1311 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1312#endif
1313 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1347 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext);
1314 GEM_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext);
1348}
1349
1350static void
1351gem_start_locked(if_t ifp)
1352{
1353 struct gem_softc *sc = if_getsoftc(ifp);
1354 struct mbuf *m;
1355 int kicked, ntx;

--- 72 unchanged lines hidden (view full) ---

1428 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1429 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1430#ifdef GEM_DEBUG
1431 if ((if_getflags(ifp) & IFF_DEBUG) != 0) {
1432 printf(" txsoft %p transmit chain:\n", txs);
1433 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1434 printf("descriptor %d: ", i);
1435 printf("gd_flags: 0x%016llx\t",
1315}
1316
1317static void
1318gem_start_locked(if_t ifp)
1319{
1320 struct gem_softc *sc = if_getsoftc(ifp);
1321 struct mbuf *m;
1322 int kicked, ntx;

--- 72 unchanged lines hidden (view full) ---

1395 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1396 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1397#ifdef GEM_DEBUG
1398 if ((if_getflags(ifp) & IFF_DEBUG) != 0) {
1399 printf(" txsoft %p transmit chain:\n", txs);
1400 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1401 printf("descriptor %d: ", i);
1402 printf("gd_flags: 0x%016llx\t",
1436 (long long)GEM_DMA_READ(sc,
1403 (long long)le64toh(
1437 sc->sc_txdescs[i].gd_flags));
1438 printf("gd_addr: 0x%016llx\n",
1404 sc->sc_txdescs[i].gd_flags));
1405 printf("gd_addr: 0x%016llx\n",
1439 (long long)GEM_DMA_READ(sc,
1406 (long long)le64toh(
1440 sc->sc_txdescs[i].gd_addr));
1441 if (i == txs->txs_lastdesc)
1442 break;
1443 }
1444 }
1445#endif
1446
1447 /*
1448 * In theory, we could harvest some descriptors before
1449 * the ring is empty, but that's a bit complicated.
1450 *
1451 * GEM_TX_COMPLETION points to the last descriptor
1452 * processed + 1.
1453 */
1407 sc->sc_txdescs[i].gd_addr));
1408 if (i == txs->txs_lastdesc)
1409 break;
1410 }
1411 }
1412#endif
1413
1414 /*
1415 * In theory, we could harvest some descriptors before
1416 * the ring is empty, but that's a bit complicated.
1417 *
1418 * GEM_TX_COMPLETION points to the last descriptor
1419 * processed + 1.
1420 */
1454 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION);
1421 txlast = GEM_READ_4(sc, GEM_TX_COMPLETION);
1455#ifdef GEM_DEBUG
1456 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
1457 "txs->txs_lastdesc = %d, txlast = %d",
1458 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1459#endif
1460 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1461 if ((txlast >= txs->txs_firstdesc) &&
1462 (txlast <= txs->txs_lastdesc))

--- 24 unchanged lines hidden (view full) ---

1487
1488 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1489 progress = 1;
1490 }
1491
1492#ifdef GEM_DEBUG
1493 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
1494 "GEM_TX_COMPLETION %x",
1422#ifdef GEM_DEBUG
1423 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, "
1424 "txs->txs_lastdesc = %d, txlast = %d",
1425 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1426#endif
1427 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1428 if ((txlast >= txs->txs_firstdesc) &&
1429 (txlast <= txs->txs_lastdesc))

--- 24 unchanged lines hidden (view full) ---

1454
1455 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1456 progress = 1;
1457 }
1458
1459#ifdef GEM_DEBUG
1460 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx "
1461 "GEM_TX_COMPLETION %x",
1495 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE),
1496 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) |
1497 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO),
1498 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION));
1462 __func__, GEM_READ_4(sc, GEM_TX_STATE_MACHINE),
1463 ((long long)GEM_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) |
1464 GEM_READ_4(sc, GEM_TX_DATA_PTR_LO),
1465 GEM_READ_4(sc, GEM_TX_COMPLETION));
1499#endif
1500
1501 if (progress) {
1502 if (sc->sc_txfree == GEM_NTXDESC - 1)
1503 sc->sc_txwin = 0;
1504
1505 /*
1506 * We freed some descriptors, so reset IFF_DRV_OACTIVE

--- 39 unchanged lines hidden (view full) ---

1546#ifdef GEM_DEBUG
1547 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1548#endif
1549
1550 /*
1551 * Read the completion register once. This limits
1552 * how long the following loop can execute.
1553 */
1466#endif
1467
1468 if (progress) {
1469 if (sc->sc_txfree == GEM_NTXDESC - 1)
1470 sc->sc_txwin = 0;
1471
1472 /*
1473 * We freed some descriptors, so reset IFF_DRV_OACTIVE

--- 39 unchanged lines hidden (view full) ---

1513#ifdef GEM_DEBUG
1514 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__);
1515#endif
1516
1517 /*
1518 * Read the completion register once. This limits
1519 * how long the following loop can execute.
1520 */
1554 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION);
1521 rxcomp = GEM_READ_4(sc, GEM_RX_COMPLETION);
1555#ifdef GEM_DEBUG
1556 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d",
1557 __func__, sc->sc_rxptr, rxcomp);
1558#endif
1559 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1560 for (; sc->sc_rxptr != rxcomp;) {
1561 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;
1522#ifdef GEM_DEBUG
1523 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d",
1524 __func__, sc->sc_rxptr, rxcomp);
1525#endif
1526 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1527 for (; sc->sc_rxptr != rxcomp;) {
1528 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf;
1562 rxstat = GEM_DMA_READ(sc,
1563 sc->sc_rxdescs[sc->sc_rxptr].gd_flags);
1529 rxstat = le64toh(sc->sc_rxdescs[sc->sc_rxptr].gd_flags);
1564
1565 if (rxstat & GEM_RD_OWN) {
1566#ifdef GEM_RINT_TIMEOUT
1567 /*
1568 * The descriptor is still marked as owned, although
1569 * it is supposed to have completed. This has been
1570 * observed on some machines. Just exiting here
1571 * might leave the packet sitting around until another

--- 15 unchanged lines hidden (view full) ---

1587 goto kickit;
1588 }
1589
1590#ifdef GEM_DEBUG
1591 if ((if_getflags(ifp) & IFF_DEBUG) != 0) {
1592 printf(" rxsoft %p descriptor %d: ",
1593 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr);
1594 printf("gd_flags: 0x%016llx\t",
1530
1531 if (rxstat & GEM_RD_OWN) {
1532#ifdef GEM_RINT_TIMEOUT
1533 /*
1534 * The descriptor is still marked as owned, although
1535 * it is supposed to have completed. This has been
1536 * observed on some machines. Just exiting here
1537 * might leave the packet sitting around until another

--- 15 unchanged lines hidden (view full) ---

1553 goto kickit;
1554 }
1555
1556#ifdef GEM_DEBUG
1557 if ((if_getflags(ifp) & IFF_DEBUG) != 0) {
1558 printf(" rxsoft %p descriptor %d: ",
1559 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr);
1560 printf("gd_flags: 0x%016llx\t",
1595 (long long)GEM_DMA_READ(sc,
1561 (long long)le64toh(
1596 sc->sc_rxdescs[sc->sc_rxptr].gd_flags));
1597 printf("gd_addr: 0x%016llx\n",
1562 sc->sc_rxdescs[sc->sc_rxptr].gd_flags));
1563 printf("gd_addr: 0x%016llx\n",
1598 (long long)GEM_DMA_READ(sc,
1564 (long long)le64toh(
1599 sc->sc_rxdescs[sc->sc_rxptr].gd_addr));
1600 }
1601#endif
1602
1603 /*
1604 * Allocate a new mbuf cluster. If that fails, we are
1605 * out of memory, and must drop the packet and recycle
1606 * the buffer that's already attached to this descriptor.

--- 11 unchanged lines hidden (view full) ---

1618 * current batch) and for optimum performance should be
1619 * incremented in multiples of 4 (the DMA engine fetches/
1620 * updates descriptors in batches of 4).
1621 */
1622 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1623 if ((sc->sc_rxptr % 4) == 0) {
1624 GEM_CDSYNC(sc,
1625 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1565 sc->sc_rxdescs[sc->sc_rxptr].gd_addr));
1566 }
1567#endif
1568
1569 /*
1570 * Allocate a new mbuf cluster. If that fails, we are
1571 * out of memory, and must drop the packet and recycle
1572 * the buffer that's already attached to this descriptor.

--- 11 unchanged lines hidden (view full) ---

1584 * current batch) and for optimum performance should be
1585 * incremented in multiples of 4 (the DMA engine fetches/
1586 * updates descriptors in batches of 4).
1587 */
1588 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr);
1589 if ((sc->sc_rxptr % 4) == 0) {
1590 GEM_CDSYNC(sc,
1591 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1626 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK,
1592 GEM_WRITE_4(sc, GEM_RX_KICK,
1627 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1628 GEM_NRXDESC_MASK);
1629 }
1630
1631 if (m == NULL) {
1632 if (rxstat & GEM_RD_OWN)
1633 break;
1634 continue;

--- 10 unchanged lines hidden (view full) ---

1645 /* Pass it on. */
1646 GEM_UNLOCK(sc);
1647 if_input(ifp, m);
1648 GEM_LOCK(sc);
1649 }
1650
1651#ifdef GEM_DEBUG
1652 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__,
1593 (sc->sc_rxptr + GEM_NRXDESC - 4) &
1594 GEM_NRXDESC_MASK);
1595 }
1596
1597 if (m == NULL) {
1598 if (rxstat & GEM_RD_OWN)
1599 break;
1600 continue;

--- 10 unchanged lines hidden (view full) ---

1611 /* Pass it on. */
1612 GEM_UNLOCK(sc);
1613 if_input(ifp, m);
1614 GEM_LOCK(sc);
1615 }
1616
1617#ifdef GEM_DEBUG
1618 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__,
1653 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION));
1619 sc->sc_rxptr, GEM_READ_4(sc, GEM_RX_COMPLETION));
1654#endif
1655}
1656
1657static int
1658gem_add_rxbuf(struct gem_softc *sc, int idx)
1659{
1660 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1661 struct mbuf *m;

--- 47 unchanged lines hidden (view full) ---

1709 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1710 if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
1711 gem_reset_rxdma(sc);
1712 return;
1713 }
1714
1715 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1716 if ((status & GEM_INTR_BERR) != 0) {
1620#endif
1621}
1622
1623static int
1624gem_add_rxbuf(struct gem_softc *sc, int idx)
1625{
1626 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1627 struct mbuf *m;

--- 47 unchanged lines hidden (view full) ---

1675 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1676 if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
1677 gem_reset_rxdma(sc);
1678 return;
1679 }
1680
1681 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1682 if ((status & GEM_INTR_BERR) != 0) {
1717 if ((sc->sc_flags & GEM_PCI) != 0)
1718 printf(", PCI bus error 0x%x\n",
1719 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS));
1720 else
1721 printf(", SBus error 0x%x\n",
1722 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS));
1683 printf(", PCI bus error 0x%x",
1684 GEM_READ_4(sc, GEM_PCI_ERROR_STATUS));
1723 }
1685 }
1686 printf("\n");
1724}
1725
1726void
1727gem_intr(void *v)
1728{
1729 struct gem_softc *sc = v;
1730 uint32_t status, status2;
1731
1732 GEM_LOCK(sc);
1687}
1688
1689void
1690gem_intr(void *v)
1691{
1692 struct gem_softc *sc = v;
1693 uint32_t status, status2;
1694
1695 GEM_LOCK(sc);
1733 status = GEM_BANK1_READ_4(sc, GEM_STATUS);
1696 status = GEM_READ_4(sc, GEM_STATUS);
1734
1735#ifdef GEM_DEBUG
1736 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1737 device_get_name(sc->sc_dev), __func__,
1738 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status);
1739
1740 /*
1741 * PCS interrupts must be cleared, otherwise no traffic is passed!
1742 */
1743 if ((status & GEM_INTR_PCS) != 0) {
1744 status2 =
1697
1698#ifdef GEM_DEBUG
1699 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x",
1700 device_get_name(sc->sc_dev), __func__,
1701 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status);
1702
1703 /*
1704 * PCS interrupts must be cleared, otherwise no traffic is passed!
1705 */
1706 if ((status & GEM_INTR_PCS) != 0) {
1707 status2 =
1745 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) |
1746 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS);
1708 GEM_READ_4(sc, GEM_MII_INTERRUP_STATUS) |
1709 GEM_READ_4(sc, GEM_MII_INTERRUP_STATUS);
1747 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1748 device_printf(sc->sc_dev,
1749 "%s: PCS link status changed\n", __func__);
1750 }
1751 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1710 if ((status2 & GEM_MII_INTERRUP_LINK) != 0)
1711 device_printf(sc->sc_dev,
1712 "%s: PCS link status changed\n", __func__);
1713 }
1714 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
1752 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS);
1715 status2 = GEM_READ_4(sc, GEM_MAC_CONTROL_STATUS);
1753 if ((status2 & GEM_MAC_PAUSED) != 0)
1754 device_printf(sc->sc_dev,
1755 "%s: PAUSE received (PAUSE time %d slots)\n",
1756 __func__, GEM_MAC_PAUSE_TIME(status2));
1757 if ((status2 & GEM_MAC_PAUSE) != 0)
1758 device_printf(sc->sc_dev,
1759 "%s: transited to PAUSE state\n", __func__);
1760 if ((status2 & GEM_MAC_RESUME) != 0)

--- 10 unchanged lines hidden (view full) ---

1771
1772 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1773 gem_rint(sc);
1774
1775 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1776 gem_tint(sc);
1777
1778 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) {
1716 if ((status2 & GEM_MAC_PAUSED) != 0)
1717 device_printf(sc->sc_dev,
1718 "%s: PAUSE received (PAUSE time %d slots)\n",
1719 __func__, GEM_MAC_PAUSE_TIME(status2));
1720 if ((status2 & GEM_MAC_PAUSE) != 0)
1721 device_printf(sc->sc_dev,
1722 "%s: transited to PAUSE state\n", __func__);
1723 if ((status2 & GEM_MAC_RESUME) != 0)

--- 10 unchanged lines hidden (view full) ---

1734
1735 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1736 gem_rint(sc);
1737
1738 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1739 gem_tint(sc);
1740
1741 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) {
1779 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS);
1742 status2 = GEM_READ_4(sc, GEM_MAC_TX_STATUS);
1780 if ((status2 &
1781 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
1782 GEM_MAC_TX_PEAK_EXP)) != 0)
1783 device_printf(sc->sc_dev,
1784 "MAC TX fault, status %x\n", status2);
1785 if ((status2 &
1786 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) {
1787 if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1);
1788 if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_RUNNING);
1789 gem_init_locked(sc);
1790 }
1791 }
1792 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) {
1743 if ((status2 &
1744 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP |
1745 GEM_MAC_TX_PEAK_EXP)) != 0)
1746 device_printf(sc->sc_dev,
1747 "MAC TX fault, status %x\n", status2);
1748 if ((status2 &
1749 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) {
1750 if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1);
1751 if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_RUNNING);
1752 gem_init_locked(sc);
1753 }
1754 }
1755 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) {
1793 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS);
1756 status2 = GEM_READ_4(sc, GEM_MAC_RX_STATUS);
1794 /*
1757 /*
1795 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
1796 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
1797 * silicon bug so handle them silently. Moreover, it's
1798 * likely that the receiver has hung so we reset it.
1758 * At least with GEM_SUN_GEM revisions GEM_MAC_RX_OVERFLOW
1759 * happen often due to a silicon bug so handle them silently.
1760 * Moreover, it's likely that the receiver has hung so we
1761 * reset it.
1799 */
1800 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) {
1801 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1802 gem_reset_rxdma(sc);
1803 } else if ((status2 &
1804 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0)
1805 device_printf(sc->sc_dev,
1806 "MAC RX fault, status %x\n", status2);

--- 6 unchanged lines hidden (view full) ---

1813{
1814 if_t ifp = sc->sc_ifp;
1815
1816 GEM_LOCK_ASSERT(sc, MA_OWNED);
1817
1818#ifdef GEM_DEBUG
1819 CTR4(KTR_GEM,
1820 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
1762 */
1763 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) {
1764 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1);
1765 gem_reset_rxdma(sc);
1766 } else if ((status2 &
1767 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0)
1768 device_printf(sc->sc_dev,
1769 "MAC RX fault, status %x\n", status2);

--- 6 unchanged lines hidden (view full) ---

1776{
1777 if_t ifp = sc->sc_ifp;
1778
1779 GEM_LOCK_ASSERT(sc, MA_OWNED);
1780
1781#ifdef GEM_DEBUG
1782 CTR4(KTR_GEM,
1783 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x",
1821 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG),
1822 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS),
1823 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG));
1784 __func__, GEM_READ_4(sc, GEM_RX_CONFIG),
1785 GEM_READ_4(sc, GEM_MAC_RX_STATUS),
1786 GEM_READ_4(sc, GEM_MAC_RX_CONFIG));
1824 CTR4(KTR_GEM,
1825 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
1787 CTR4(KTR_GEM,
1788 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x",
1826 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG),
1827 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS),
1828 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG));
1789 __func__, GEM_READ_4(sc, GEM_TX_CONFIG),
1790 GEM_READ_4(sc, GEM_MAC_TX_STATUS),
1791 GEM_READ_4(sc, GEM_MAC_TX_CONFIG));
1829#endif
1830
1831 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1832 return (0);
1833
1834 if ((sc->sc_flags & GEM_LINK) != 0)
1835 device_printf(sc->sc_dev, "device timeout\n");
1836 else if (bootverbose)

--- 7 unchanged lines hidden (view full) ---

1844 return (EJUSTRETURN);
1845}
1846
1847static void
1848gem_mifinit(struct gem_softc *sc)
1849{
1850
1851 /* Configure the MIF in frame mode. */
1792#endif
1793
1794 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1795 return (0);
1796
1797 if ((sc->sc_flags & GEM_LINK) != 0)
1798 device_printf(sc->sc_dev, "device timeout\n");
1799 else if (bootverbose)

--- 7 unchanged lines hidden (view full) ---

1807 return (EJUSTRETURN);
1808}
1809
1810static void
1811gem_mifinit(struct gem_softc *sc)
1812{
1813
1814 /* Configure the MIF in frame mode. */
1852 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG,
1853 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1854 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4,
1815 GEM_WRITE_4(sc, GEM_MIF_CONFIG,
1816 GEM_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA);
1817 GEM_BARRIER(sc, GEM_MIF_CONFIG, 4,
1855 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1856}
1857
1858/*
1859 * MII interface
1860 *
1861 * The MII interface supports at least three different operating modes:
1862 *

--- 37 unchanged lines hidden (view full) ---

1900 break;
1901 case MII_EXTSR:
1902 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1903 default:
1904 device_printf(sc->sc_dev,
1905 "%s: unhandled register %d\n", __func__, reg);
1906 return (0);
1907 }
1818 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1819}
1820
1821/*
1822 * MII interface
1823 *
1824 * The MII interface supports at least three different operating modes:
1825 *

--- 37 unchanged lines hidden (view full) ---

1863 break;
1864 case MII_EXTSR:
1865 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
1866 default:
1867 device_printf(sc->sc_dev,
1868 "%s: unhandled register %d\n", __func__, reg);
1869 return (0);
1870 }
1908 return (GEM_BANK1_READ_4(sc, reg));
1871 return (GEM_READ_4(sc, reg));
1909 }
1910
1911 /* Construct the frame command. */
1912 v = GEM_MIF_FRAME_READ |
1913 (phy << GEM_MIF_PHY_SHIFT) |
1914 (reg << GEM_MIF_REG_SHIFT);
1915
1872 }
1873
1874 /* Construct the frame command. */
1875 v = GEM_MIF_FRAME_READ |
1876 (phy << GEM_MIF_PHY_SHIFT) |
1877 (reg << GEM_MIF_REG_SHIFT);
1878
1916 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1917 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4,
1879 GEM_WRITE_4(sc, GEM_MIF_FRAME, v);
1880 GEM_BARRIER(sc, GEM_MIF_FRAME, 4,
1918 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1919 for (n = 0; n < 100; n++) {
1920 DELAY(1);
1881 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1882 for (n = 0; n < 100; n++) {
1883 DELAY(1);
1921 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
1884 v = GEM_READ_4(sc, GEM_MIF_FRAME);
1922 if (v & GEM_MIF_FRAME_TA0)
1923 return (v & GEM_MIF_FRAME_DATA);
1924 }
1925
1926 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1927 return (0);
1928}
1929

--- 13 unchanged lines hidden (view full) ---

1943 switch (reg) {
1944 case MII_BMSR:
1945 reg = GEM_MII_STATUS;
1946 break;
1947 case MII_BMCR:
1948 reg = GEM_MII_CONTROL;
1949 if ((val & GEM_MII_CONTROL_RESET) == 0)
1950 break;
1885 if (v & GEM_MIF_FRAME_TA0)
1886 return (v & GEM_MIF_FRAME_DATA);
1887 }
1888
1889 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1890 return (0);
1891}
1892

--- 13 unchanged lines hidden (view full) ---

1906 switch (reg) {
1907 case MII_BMSR:
1908 reg = GEM_MII_STATUS;
1909 break;
1910 case MII_BMCR:
1911 reg = GEM_MII_CONTROL;
1912 if ((val & GEM_MII_CONTROL_RESET) == 0)
1913 break;
1951 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val);
1952 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4,
1914 GEM_WRITE_4(sc, GEM_MII_CONTROL, val);
1915 GEM_BARRIER(sc, GEM_MII_CONTROL, 4,
1953 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1916 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1954 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL,
1917 if (!gem_bitwait(sc, GEM_MII_CONTROL,
1955 GEM_MII_CONTROL_RESET, 0))
1956 device_printf(sc->sc_dev,
1957 "cannot reset PCS\n");
1958 /* FALLTHROUGH */
1959 case MII_ANAR:
1918 GEM_MII_CONTROL_RESET, 0))
1919 device_printf(sc->sc_dev,
1920 "cannot reset PCS\n");
1921 /* FALLTHROUGH */
1922 case MII_ANAR:
1960 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0);
1961 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
1923 GEM_WRITE_4(sc, GEM_MII_CONFIG, 0);
1924 GEM_BARRIER(sc, GEM_MII_CONFIG, 4,
1962 BUS_SPACE_BARRIER_WRITE);
1925 BUS_SPACE_BARRIER_WRITE);
1963 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val);
1964 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4,
1926 GEM_WRITE_4(sc, GEM_MII_ANAR, val);
1927 GEM_BARRIER(sc, GEM_MII_ANAR, 4,
1965 BUS_SPACE_BARRIER_WRITE);
1928 BUS_SPACE_BARRIER_WRITE);
1966 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
1929 GEM_WRITE_4(sc, GEM_MII_SLINK_CONTROL,
1967 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
1930 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D);
1968 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
1931 GEM_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4,
1969 BUS_SPACE_BARRIER_WRITE);
1932 BUS_SPACE_BARRIER_WRITE);
1970 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG,
1933 GEM_WRITE_4(sc, GEM_MII_CONFIG,
1971 GEM_MII_CONFIG_ENABLE);
1934 GEM_MII_CONFIG_ENABLE);
1972 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4,
1935 GEM_BARRIER(sc, GEM_MII_CONFIG, 4,
1973 BUS_SPACE_BARRIER_WRITE);
1974 return (0);
1975 case MII_ANLPAR:
1976 reg = GEM_MII_ANLPAR;
1977 break;
1978 default:
1979 device_printf(sc->sc_dev,
1980 "%s: unhandled register %d\n", __func__, reg);
1981 return (0);
1982 }
1936 BUS_SPACE_BARRIER_WRITE);
1937 return (0);
1938 case MII_ANLPAR:
1939 reg = GEM_MII_ANLPAR;
1940 break;
1941 default:
1942 device_printf(sc->sc_dev,
1943 "%s: unhandled register %d\n", __func__, reg);
1944 return (0);
1945 }
1983 GEM_BANK1_WRITE_4(sc, reg, val);
1984 GEM_BANK1_BARRIER(sc, reg, 4,
1946 GEM_WRITE_4(sc, reg, val);
1947 GEM_BARRIER(sc, reg, 4,
1985 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1986 return (0);
1987 }
1988
1989 /* Construct the frame command. */
1990 v = GEM_MIF_FRAME_WRITE |
1991 (phy << GEM_MIF_PHY_SHIFT) |
1992 (reg << GEM_MIF_REG_SHIFT) |
1993 (val & GEM_MIF_FRAME_DATA);
1994
1948 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1949 return (0);
1950 }
1951
1952 /* Construct the frame command. */
1953 v = GEM_MIF_FRAME_WRITE |
1954 (phy << GEM_MIF_PHY_SHIFT) |
1955 (reg << GEM_MIF_REG_SHIFT) |
1956 (val & GEM_MIF_FRAME_DATA);
1957
1995 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v);
1996 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4,
1958 GEM_WRITE_4(sc, GEM_MIF_FRAME, v);
1959 GEM_BARRIER(sc, GEM_MIF_FRAME, 4,
1997 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1998 for (n = 0; n < 100; n++) {
1999 DELAY(1);
1960 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1961 for (n = 0; n < 100; n++) {
1962 DELAY(1);
2000 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME);
1963 v = GEM_READ_4(sc, GEM_MIF_FRAME);
2001 if (v & GEM_MIF_FRAME_TA0)
2002 return (1);
2003 }
2004
2005 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2006 return (0);
2007}
2008

--- 42 unchanged lines hidden (view full) ---

2051 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
2052 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2053 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
2054 else if (gigabit != 0) {
2055 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
2056 txcfg |= GEM_MAC_TX_CARR_EXTEND;
2057 }
2058 (void)gem_disable_tx(sc);
1964 if (v & GEM_MIF_FRAME_TA0)
1965 return (1);
1966 }
1967
1968 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
1969 return (0);
1970}
1971

--- 42 unchanged lines hidden (view full) ---

2014 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
2015 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2016 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
2017 else if (gigabit != 0) {
2018 rxcfg |= GEM_MAC_RX_CARR_EXTEND;
2019 txcfg |= GEM_MAC_TX_CARR_EXTEND;
2020 }
2021 (void)gem_disable_tx(sc);
2059 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg);
2022 GEM_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg);
2060 (void)gem_disable_rx(sc);
2023 (void)gem_disable_rx(sc);
2061 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg);
2024 GEM_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg);
2062
2025
2063 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) &
2026 v = GEM_READ_4(sc, GEM_MAC_CONTROL_CONFIG) &
2064 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
2065 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2066 IFM_ETH_RXPAUSE) != 0)
2067 v |= GEM_MAC_CC_RX_PAUSE;
2068 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2069 IFM_ETH_TXPAUSE) != 0)
2070 v |= GEM_MAC_CC_TX_PAUSE;
2027 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
2028 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2029 IFM_ETH_RXPAUSE) != 0)
2030 v |= GEM_MAC_CC_RX_PAUSE;
2031 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2032 IFM_ETH_TXPAUSE) != 0)
2033 v |= GEM_MAC_CC_TX_PAUSE;
2071 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v);
2034 GEM_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v);
2072
2073 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2074 gigabit != 0)
2035
2036 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2037 gigabit != 0)
2075 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2038 GEM_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2076 GEM_MAC_SLOT_TIME_CARR_EXTEND);
2077 else
2039 GEM_MAC_SLOT_TIME_CARR_EXTEND);
2040 else
2078 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2041 GEM_WRITE_4(sc, GEM_MAC_SLOT_TIME,
2079 GEM_MAC_SLOT_TIME_NORMAL);
2080
2081 /* XIF Configuration */
2082 v = GEM_MAC_XIF_LINK_LED;
2083 v |= GEM_MAC_XIF_TX_MII_ENA;
2084 if ((sc->sc_flags & GEM_SERDES) == 0) {
2042 GEM_MAC_SLOT_TIME_NORMAL);
2043
2044 /* XIF Configuration */
2045 v = GEM_MAC_XIF_LINK_LED;
2046 v |= GEM_MAC_XIF_TX_MII_ENA;
2047 if ((sc->sc_flags & GEM_SERDES) == 0) {
2085 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) &
2048 if ((GEM_READ_4(sc, GEM_MIF_CONFIG) &
2086 GEM_MIF_CONFIG_PHY_SEL) != 0) {
2087 /* External MII needs echo disable if half duplex. */
2088 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2089 IFM_FDX) == 0)
2090 v |= GEM_MAC_XIF_ECHO_DISABL;
2091 } else
2092 /*
2093 * Internal MII needs buffer enable.
2094 * XXX buffer enable makes only sense for an
2095 * external PHY.
2096 */
2097 v |= GEM_MAC_XIF_MII_BUF_ENA;
2098 }
2099 if (gigabit != 0)
2100 v |= GEM_MAC_XIF_GMII_MODE;
2101 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2102 v |= GEM_MAC_XIF_FDPLX_LED;
2049 GEM_MIF_CONFIG_PHY_SEL) != 0) {
2050 /* External MII needs echo disable if half duplex. */
2051 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2052 IFM_FDX) == 0)
2053 v |= GEM_MAC_XIF_ECHO_DISABL;
2054 } else
2055 /*
2056 * Internal MII needs buffer enable.
2057 * XXX buffer enable makes only sense for an
2058 * external PHY.
2059 */
2060 v |= GEM_MAC_XIF_MII_BUF_ENA;
2061 }
2062 if (gigabit != 0)
2063 v |= GEM_MAC_XIF_GMII_MODE;
2064 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2065 v |= GEM_MAC_XIF_FDPLX_LED;
2103 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v);
2066 GEM_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v);
2104
2105 sc->sc_mac_rxcfg = rxcfg;
2106 if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) != 0 &&
2107 (sc->sc_flags & GEM_LINK) != 0) {
2067
2068 sc->sc_mac_rxcfg = rxcfg;
2069 if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) != 0 &&
2070 (sc->sc_flags & GEM_LINK) != 0) {
2108 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG,
2071 GEM_WRITE_4(sc, GEM_MAC_TX_CONFIG,
2109 txcfg | GEM_MAC_TX_ENABLE);
2072 txcfg | GEM_MAC_TX_ENABLE);
2110 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG,
2073 GEM_WRITE_4(sc, GEM_MAC_RX_CONFIG,
2111 rxcfg | GEM_MAC_RX_ENABLE);
2112 }
2113}
2114
2115int
2116gem_mediachange(if_t ifp)
2117{
2118 struct gem_softc *sc = if_getsoftc(ifp);

--- 105 unchanged lines hidden (view full) ---

2224
2225 GEM_LOCK_ASSERT(sc, MA_OWNED);
2226
2227 /*
2228 * Turn off the RX MAC and the hash filter as required by the Sun GEM
2229 * programming restrictions.
2230 */
2231 v = sc->sc_mac_rxcfg & ~GEM_MAC_RX_HASH_FILTER;
2074 rxcfg | GEM_MAC_RX_ENABLE);
2075 }
2076}
2077
2078int
2079gem_mediachange(if_t ifp)
2080{
2081 struct gem_softc *sc = if_getsoftc(ifp);

--- 105 unchanged lines hidden (view full) ---

2187
2188 GEM_LOCK_ASSERT(sc, MA_OWNED);
2189
2190 /*
2191 * Turn off the RX MAC and the hash filter as required by the Sun GEM
2192 * programming restrictions.
2193 */
2194 v = sc->sc_mac_rxcfg & ~GEM_MAC_RX_HASH_FILTER;
2232 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
2233 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
2195 GEM_WRITE_4(sc, GEM_MAC_RX_CONFIG, v);
2196 GEM_BARRIER(sc, GEM_MAC_RX_CONFIG, 4,
2234 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2197 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2235 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER |
2198 if (!gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER |
2236 GEM_MAC_RX_ENABLE, 0))
2237 device_printf(sc->sc_dev,
2238 "cannot disable RX MAC or hash filter\n");
2239
2240 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP);
2241 if ((if_getflags(ifp) & IFF_PROMISC) != 0) {
2242 v |= GEM_MAC_RX_PROMISCUOUS;
2243 goto chipit;

--- 14 unchanged lines hidden (view full) ---

2258
2259 memset(hash, 0, sizeof(hash));
2260 if_foreach_llmaddr(ifp, gem_hash_maddr, hash);
2261
2262 v |= GEM_MAC_RX_HASH_FILTER;
2263
2264 /* Now load the hash table into the chip (if we are using it). */
2265 for (i = 0; i < 16; i++)
2199 GEM_MAC_RX_ENABLE, 0))
2200 device_printf(sc->sc_dev,
2201 "cannot disable RX MAC or hash filter\n");
2202
2203 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP);
2204 if ((if_getflags(ifp) & IFF_PROMISC) != 0) {
2205 v |= GEM_MAC_RX_PROMISCUOUS;
2206 goto chipit;

--- 14 unchanged lines hidden (view full) ---

2221
2222 memset(hash, 0, sizeof(hash));
2223 if_foreach_llmaddr(ifp, gem_hash_maddr, hash);
2224
2225 v |= GEM_MAC_RX_HASH_FILTER;
2226
2227 /* Now load the hash table into the chip (if we are using it). */
2228 for (i = 0; i < 16; i++)
2266 GEM_BANK1_WRITE_4(sc,
2229 GEM_WRITE_4(sc,
2267 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
2268 hash[i]);
2269
2270 chipit:
2271 sc->sc_mac_rxcfg = v;
2230 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0),
2231 hash[i]);
2232
2233 chipit:
2234 sc->sc_mac_rxcfg = v;
2272 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v | GEM_MAC_RX_ENABLE);
2235 GEM_WRITE_4(sc, GEM_MAC_RX_CONFIG, v | GEM_MAC_RX_ENABLE);
2273}
2236}