ena.h (b899a02ad7330cae3c9bb08ad7975601dc3b9551) ena.h (82e558eacf222ac497bc11fa9f2c7778e97fbc7a)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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53#endif
54#define DEVICE_NAME "Elastic Network Adapter (ENA)"
55#define DEVICE_DESC "ENA adapter"
56
57/* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
58#define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
59
60/* 1 for AENQ + ADMIN */
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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53#endif
54#define DEVICE_NAME "Elastic Network Adapter (ENA)"
55#define DEVICE_DESC "ENA adapter"
56
57/* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */
58#define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
59
60/* 1 for AENQ + ADMIN */
61#define ENA_ADMIN_MSIX_VEC 1
62#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
61#define ENA_ADMIN_MSIX_VEC 1
62#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
63
63
64#define ENA_REG_BAR 0
65#define ENA_MEM_BAR 2
64#define ENA_REG_BAR 0
65#define ENA_MEM_BAR 2
66
66
67#define ENA_BUS_DMA_SEGS 32
67#define ENA_BUS_DMA_SEGS 32
68
68
69#define ENA_DEFAULT_BUF_RING_SIZE 4096
69#define ENA_DEFAULT_BUF_RING_SIZE 4096
70
70
71#define ENA_DEFAULT_RING_SIZE 1024
72#define ENA_MIN_RING_SIZE 256
71#define ENA_DEFAULT_RING_SIZE 1024
72#define ENA_MIN_RING_SIZE 256
73
74/*
75 * Refill Rx queue when number of required descriptors is above
76 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
77 */
73
74/*
75 * Refill Rx queue when number of required descriptors is above
76 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
77 */
78#define ENA_RX_REFILL_THRESH_DIVIDER 8
79#define ENA_RX_REFILL_THRESH_PACKET 256
78#define ENA_RX_REFILL_THRESH_DIVIDER 8
79#define ENA_RX_REFILL_THRESH_PACKET 256
80
80
81#define ENA_IRQNAME_SIZE 40
81#define ENA_IRQNAME_SIZE 40
82
82
83#define ENA_PKT_MAX_BUFS 19
83#define ENA_PKT_MAX_BUFS 19
84
84
85#define ENA_RX_RSS_TABLE_LOG_SIZE 7
86#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
85#define ENA_RX_RSS_TABLE_LOG_SIZE 7
86#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
87
87
88#define ENA_HASH_KEY_SIZE 40
88#define ENA_HASH_KEY_SIZE 40
89
89
90#define ENA_MAX_FRAME_LEN 10000
91#define ENA_MIN_FRAME_LEN 60
90#define ENA_MAX_FRAME_LEN 10000
91#define ENA_MIN_FRAME_LEN 60
92
93#define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2)
94
95#define DB_THRESHOLD 64
96
97#define TX_COMMIT 32
98 /*
99 * TX budget for cleaning. It should be half of the RX budget to reduce amount

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106 * How many times we can repeat cleanup in the io irq handling routine if the
107 * RX or TX budget was depleted.
108 */
109#define CLEAN_BUDGET 8
110
111#define RX_IRQ_INTERVAL 20
112#define TX_IRQ_INTERVAL 50
113
92
93#define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2)
94
95#define DB_THRESHOLD 64
96
97#define TX_COMMIT 32
98 /*
99 * TX budget for cleaning. It should be half of the RX budget to reduce amount

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106 * How many times we can repeat cleanup in the io irq handling routine if the
107 * RX or TX budget was depleted.
108 */
109#define CLEAN_BUDGET 8
110
111#define RX_IRQ_INTERVAL 20
112#define TX_IRQ_INTERVAL 50
113
114#define ENA_MIN_MTU 128
114#define ENA_MIN_MTU 128
115
115
116#define ENA_TSO_MAXSIZE 65536
116#define ENA_TSO_MAXSIZE 65536
117
117
118#define ENA_MMIO_DISABLE_REG_READ BIT(0)
118#define ENA_MMIO_DISABLE_REG_READ BIT(0)
119
119
120#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
120#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
121
121
122#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
122#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
123
123
124#define ENA_IO_TXQ_IDX(q) (2 * (q))
125#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
126#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
127#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
124#define ENA_IO_TXQ_IDX(q) (2 * (q))
125#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
126#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
127#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
128
128
129#define ENA_MGMNT_IRQ_IDX 0
130#define ENA_IO_IRQ_FIRST_IDX 1
131#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
129#define ENA_MGMNT_IRQ_IDX 0
130#define ENA_IO_IRQ_FIRST_IDX 1
131#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
132
132
133#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
133#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
134
135/*
136 * ENA device should send keep alive msg every 1 sec.
137 * We wait for 6 sec just to be on the safe side.
138 */
139#define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
140
141/* Time in jiffies before concluding the transmitter is hung. */
142#define DEFAULT_TX_CMP_TO (SBT_1S * 5)
143
144/* Number of queues to check for missing queues per timer tick */
145#define DEFAULT_TX_MONITORED_QUEUES (4)
146
147/* Max number of timeouted packets before device reset */
148#define DEFAULT_TX_CMP_THRESHOLD (128)
149
150/*
151 * Supported PCI vendor and devices IDs
152 */
134
135/*
136 * ENA device should send keep alive msg every 1 sec.
137 * We wait for 6 sec just to be on the safe side.
138 */
139#define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6)
140
141/* Time in jiffies before concluding the transmitter is hung. */
142#define DEFAULT_TX_CMP_TO (SBT_1S * 5)
143
144/* Number of queues to check for missing queues per timer tick */
145#define DEFAULT_TX_MONITORED_QUEUES (4)
146
147/* Max number of timeouted packets before device reset */
148#define DEFAULT_TX_CMP_THRESHOLD (128)
149
150/*
151 * Supported PCI vendor and devices IDs
152 */
153#define PCI_VENDOR_ID_AMAZON 0x1d0f
153#define PCI_VENDOR_ID_AMAZON 0x1d0f
154
154
155#define PCI_DEV_ID_ENA_PF 0x0ec2
156#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2
157#define PCI_DEV_ID_ENA_VF 0xec20
158#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21
155#define PCI_DEV_ID_ENA_PF 0x0ec2
156#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2
157#define PCI_DEV_ID_ENA_VF 0xec20
158#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21
159
160/*
161 * Flags indicating current ENA driver state
162 */
163enum ena_flags_t {
164 ENA_FLAG_DEVICE_RUNNING,
165 ENA_FLAG_DEV_UP,
166 ENA_FLAG_LINK_UP,

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485 /* Statistics */
486 struct ena_stats_dev dev_stats;
487 struct ena_hw_stats hw_stats;
488 struct ena_admin_eni_stats eni_metrics;
489
490 enum ena_regs_reset_reason_types reset_reason;
491};
492
159
160/*
161 * Flags indicating current ENA driver state
162 */
163enum ena_flags_t {
164 ENA_FLAG_DEVICE_RUNNING,
165 ENA_FLAG_DEV_UP,
166 ENA_FLAG_LINK_UP,

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485 /* Statistics */
486 struct ena_stats_dev dev_stats;
487 struct ena_hw_stats hw_stats;
488 struct ena_admin_eni_stats eni_metrics;
489
490 enum ena_regs_reset_reason_types reset_reason;
491};
492
493#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
494#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
495#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
493#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
494#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
495#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
496#define ENA_RING_MTX_ASSERT(_ring) \
497 mtx_assert(&(_ring)->ring_mtx, MA_OWNED)
498
499#define ENA_LOCK_INIT() \
500 sx_init(&ena_global_lock, "ENA global lock")
501#define ENA_LOCK_DESTROY() sx_destroy(&ena_global_lock)
502#define ENA_LOCK_LOCK() sx_xlock(&ena_global_lock)
503#define ENA_LOCK_UNLOCK() sx_unlock(&ena_global_lock)
504#define ENA_LOCK_ASSERT() sx_assert(&ena_global_lock, SA_XLOCKED)
505
496#define ENA_RING_MTX_ASSERT(_ring) \
497 mtx_assert(&(_ring)->ring_mtx, MA_OWNED)
498
499#define ENA_LOCK_INIT() \
500 sx_init(&ena_global_lock, "ENA global lock")
501#define ENA_LOCK_DESTROY() sx_destroy(&ena_global_lock)
502#define ENA_LOCK_LOCK() sx_xlock(&ena_global_lock)
503#define ENA_LOCK_UNLOCK() sx_unlock(&ena_global_lock)
504#define ENA_LOCK_ASSERT() sx_assert(&ena_global_lock, SA_XLOCKED)
505
506#define ENA_TIMER_INIT(_adapter) \
506#define ENA_TIMER_INIT(_adapter) \
507 callout_init(&(_adapter)->timer_service, true)
507 callout_init(&(_adapter)->timer_service, true)
508#define ENA_TIMER_DRAIN(_adapter) \
508#define ENA_TIMER_DRAIN(_adapter) \
509 callout_drain(&(_adapter)->timer_service)
509 callout_drain(&(_adapter)->timer_service)
510#define ENA_TIMER_RESET(_adapter) \
510#define ENA_TIMER_RESET(_adapter) \
511 callout_reset_sbt(&(_adapter)->timer_service, SBT_1S, SBT_1S, \
512 ena_timer_service, (void*)(_adapter), 0)
513
514#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
515#define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi)
516
517extern struct sx ena_global_lock;
518
511 callout_reset_sbt(&(_adapter)->timer_service, SBT_1S, SBT_1S, \
512 ena_timer_service, (void*)(_adapter), 0)
513
514#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
515#define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi)
516
517extern struct sx ena_global_lock;
518
519static inline int ena_mbuf_count(struct mbuf *mbuf)
520{
521 int count = 1;
522
523 while ((mbuf = mbuf->m_next) != NULL)
524 ++count;
525
526 return count;
527}
528
529int ena_up(struct ena_adapter *adapter);
530void ena_down(struct ena_adapter *adapter);
531int ena_restore_device(struct ena_adapter *adapter);
532void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
533int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num);
534int ena_update_buf_ring_size(struct ena_adapter *adapter,
535 uint32_t new_buf_ring_size);
536int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size,
537 uint32_t new_rx_size);
538int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num);
539
519int ena_up(struct ena_adapter *adapter);
520void ena_down(struct ena_adapter *adapter);
521int ena_restore_device(struct ena_adapter *adapter);
522void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
523int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num);
524int ena_update_buf_ring_size(struct ena_adapter *adapter,
525 uint32_t new_buf_ring_size);
526int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size,
527 uint32_t new_rx_size);
528int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num);
529
530static inline int
531ena_mbuf_count(struct mbuf *mbuf)
532{
533 int count = 1;
534
535 while ((mbuf = mbuf->m_next) != NULL)
536 ++count;
537
538 return count;
539}
540
540static inline void
541ena_trigger_reset(struct ena_adapter *adapter,
542 enum ena_regs_reset_reason_types reset_reason)
543{
544 if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) {
545 adapter->reset_reason = reset_reason;
546 ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter);
547 }
548}
549
550static inline void
551ena_ring_tx_doorbell(struct ena_ring *tx_ring)
552{
553 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
554 counter_u64_add(tx_ring->tx_stats.doorbells, 1);
555 tx_ring->acum_pkts = 0;
556}
557
558#endif /* !(ENA_H) */
541static inline void
542ena_trigger_reset(struct ena_adapter *adapter,
543 enum ena_regs_reset_reason_types reset_reason)
544{
545 if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) {
546 adapter->reset_reason = reset_reason;
547 ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter);
548 }
549}
550
551static inline void
552ena_ring_tx_doorbell(struct ena_ring *tx_ring)
553{
554 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
555 counter_u64_add(tx_ring->tx_stats.doorbells, 1);
556 tx_ring->acum_pkts = 0;
557}
558
559#endif /* !(ENA_H) */