ena.c (44e86fbdcf5a3e625095652a3d0ab99532e54eea) ena.c (888810f0fb0c8993c4f3f841db7ff88ebc41396c)
1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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553 if (nm_info->map_seg[j] != NULL) {
554 bus_dmamap_destroy(tx_tag,
555 nm_info->map_seg[j]);
556 nm_info->map_seg[j] = NULL;
557 }
558 }
559 }
560#endif /* DEV_NETMAP */
1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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553 if (nm_info->map_seg[j] != NULL) {
554 bus_dmamap_destroy(tx_tag,
555 nm_info->map_seg[j]);
556 nm_info->map_seg[j] = NULL;
557 }
558 }
559 }
560#endif /* DEV_NETMAP */
561 if (tx_info->map_head != NULL) {
562 bus_dmamap_destroy(tx_tag, tx_info->map_head);
563 tx_info->map_head = NULL;
561 if (tx_info->dmamap != NULL) {
562 bus_dmamap_destroy(tx_tag, tx_info->dmamap);
563 tx_info->dmamap = NULL;
564 }
564 }
565
566 if (tx_info->map_seg != NULL) {
567 bus_dmamap_destroy(tx_tag, tx_info->map_seg);
568 tx_info->map_seg = NULL;
569 }
570 }
571}
572
573/**
574 * ena_setup_tx_resources - allocate Tx resources (Descriptors)
575 * @adapter: network interface device structure
576 * @qid: queue index
577 *

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622 /* Make sure that drbr is empty */
623 ENA_RING_MTX_LOCK(tx_ring);
624 drbr_flush(adapter->ifp, tx_ring->br);
625 ENA_RING_MTX_UNLOCK(tx_ring);
626
627 /* ... and create the buffer DMA maps */
628 for (i = 0; i < tx_ring->ring_size; i++) {
629 err = bus_dmamap_create(adapter->tx_buf_tag, 0,
565 }
566}
567
568/**
569 * ena_setup_tx_resources - allocate Tx resources (Descriptors)
570 * @adapter: network interface device structure
571 * @qid: queue index
572 *

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617 /* Make sure that drbr is empty */
618 ENA_RING_MTX_LOCK(tx_ring);
619 drbr_flush(adapter->ifp, tx_ring->br);
620 ENA_RING_MTX_UNLOCK(tx_ring);
621
622 /* ... and create the buffer DMA maps */
623 for (i = 0; i < tx_ring->ring_size; i++) {
624 err = bus_dmamap_create(adapter->tx_buf_tag, 0,
630 &tx_ring->tx_buffer_info[i].map_head);
625 &tx_ring->tx_buffer_info[i].dmamap);
631 if (unlikely(err != 0)) {
632 ena_trace(ENA_ALERT,
626 if (unlikely(err != 0)) {
627 ena_trace(ENA_ALERT,
633 "Unable to create Tx DMA map_head for buffer %d\n",
628 "Unable to create Tx DMA map for buffer %d\n",
634 i);
635 goto err_map_release;
636 }
629 i);
630 goto err_map_release;
631 }
637 tx_ring->tx_buffer_info[i].seg_mapped = false;
638
632
639 err = bus_dmamap_create(adapter->tx_buf_tag, 0,
640 &tx_ring->tx_buffer_info[i].map_seg);
641 if (unlikely(err != 0)) {
642 ena_trace(ENA_ALERT,
643 "Unable to create Tx DMA map_seg for buffer %d\n",
644 i);
645 goto err_map_release;
646 }
647 tx_ring->tx_buffer_info[i].head_mapped = false;
648
649#ifdef DEV_NETMAP
650 if (adapter->ifp->if_capenable & IFCAP_NETMAP) {
651 map = tx_ring->tx_buffer_info[i].nm_info.map_seg;
652 for (j = 0; j < ENA_PKT_MAX_BUFS; j++) {
653 err = bus_dmamap_create(adapter->tx_buf_tag, 0,
654 &map[j]);
655 if (unlikely(err != 0)) {
656 ena_trace(ENA_ALERT, "Unable to create "

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715 taskqueue_free(tx_ring->enqueue_tq);
716
717 ENA_RING_MTX_LOCK(tx_ring);
718 /* Flush buffer ring, */
719 drbr_flush(adapter->ifp, tx_ring->br);
720
721 /* Free buffer DMA maps, */
722 for (int i = 0; i < tx_ring->ring_size; i++) {
633#ifdef DEV_NETMAP
634 if (adapter->ifp->if_capenable & IFCAP_NETMAP) {
635 map = tx_ring->tx_buffer_info[i].nm_info.map_seg;
636 for (j = 0; j < ENA_PKT_MAX_BUFS; j++) {
637 err = bus_dmamap_create(adapter->tx_buf_tag, 0,
638 &map[j]);
639 if (unlikely(err != 0)) {
640 ena_trace(ENA_ALERT, "Unable to create "

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699 taskqueue_free(tx_ring->enqueue_tq);
700
701 ENA_RING_MTX_LOCK(tx_ring);
702 /* Flush buffer ring, */
703 drbr_flush(adapter->ifp, tx_ring->br);
704
705 /* Free buffer DMA maps, */
706 for (int i = 0; i < tx_ring->ring_size; i++) {
723 if (tx_ring->tx_buffer_info[i].head_mapped == true) {
724 bus_dmamap_sync(adapter->tx_buf_tag,
725 tx_ring->tx_buffer_info[i].map_head,
726 BUS_DMASYNC_POSTWRITE);
727 bus_dmamap_unload(adapter->tx_buf_tag,
728 tx_ring->tx_buffer_info[i].map_head);
729 tx_ring->tx_buffer_info[i].head_mapped = false;
730 }
707 bus_dmamap_sync(adapter->tx_buf_tag,
708 tx_ring->tx_buffer_info[i].dmamap, BUS_DMASYNC_POSTWRITE);
709 bus_dmamap_unload(adapter->tx_buf_tag,
710 tx_ring->tx_buffer_info[i].dmamap);
731 bus_dmamap_destroy(adapter->tx_buf_tag,
711 bus_dmamap_destroy(adapter->tx_buf_tag,
732 tx_ring->tx_buffer_info[i].map_head);
712 tx_ring->tx_buffer_info[i].dmamap);
733
713
734 if (tx_ring->tx_buffer_info[i].seg_mapped == true) {
735 bus_dmamap_sync(adapter->tx_buf_tag,
736 tx_ring->tx_buffer_info[i].map_seg,
737 BUS_DMASYNC_POSTWRITE);
738 bus_dmamap_unload(adapter->tx_buf_tag,
739 tx_ring->tx_buffer_info[i].map_seg);
740 tx_ring->tx_buffer_info[i].seg_mapped = false;
741 }
742 bus_dmamap_destroy(adapter->tx_buf_tag,
743 tx_ring->tx_buffer_info[i].map_seg);
744
745#ifdef DEV_NETMAP
746 if (adapter->ifp->if_capenable & IFCAP_NETMAP) {
747 nm_info = &tx_ring->tx_buffer_info[i].nm_info;
748 for (j = 0; j < ENA_PKT_MAX_BUFS; j++) {
749 if (nm_info->socket_buf_idx[j] != 0) {
750 bus_dmamap_sync(adapter->tx_buf_tag,
751 nm_info->map_seg[j],
752 BUS_DMASYNC_POSTWRITE);

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1204 qid, i);
1205 print_once = false;
1206 } else {
1207 ena_trace(ENA_DBG,
1208 "free uncompleted tx mbuf qid %d idx 0x%x\n",
1209 qid, i);
1210 }
1211
714#ifdef DEV_NETMAP
715 if (adapter->ifp->if_capenable & IFCAP_NETMAP) {
716 nm_info = &tx_ring->tx_buffer_info[i].nm_info;
717 for (j = 0; j < ENA_PKT_MAX_BUFS; j++) {
718 if (nm_info->socket_buf_idx[j] != 0) {
719 bus_dmamap_sync(adapter->tx_buf_tag,
720 nm_info->map_seg[j],
721 BUS_DMASYNC_POSTWRITE);

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1173 qid, i);
1174 print_once = false;
1175 } else {
1176 ena_trace(ENA_DBG,
1177 "free uncompleted tx mbuf qid %d idx 0x%x\n",
1178 qid, i);
1179 }
1180
1212 if (tx_info->head_mapped == true) {
1213 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->map_head,
1214 BUS_DMASYNC_POSTWRITE);
1215 bus_dmamap_unload(adapter->tx_buf_tag,
1216 tx_info->map_head);
1217 tx_info->head_mapped = false;
1218 }
1181 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap,
1182 BUS_DMASYNC_POSTWRITE);
1183 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->dmamap);
1219
1184
1220 if (tx_info->seg_mapped == true) {
1221 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->map_seg,
1222 BUS_DMASYNC_POSTWRITE);
1223 bus_dmamap_unload(adapter->tx_buf_tag,
1224 tx_info->map_seg);
1225 tx_info->seg_mapped = false;
1226 }
1227
1228 m_free(tx_info->mbuf);
1229 tx_info->mbuf = NULL;
1230 }
1231 ENA_RING_MTX_UNLOCK(tx_ring);
1232}
1233
1234static void
1235ena_free_all_tx_bufs(struct ena_adapter *adapter)

--- 2402 unchanged lines hidden --- 		1185 m_free(tx_info->mbuf);
1186 tx_info->mbuf = NULL;
1187 }
1188 ENA_RING_MTX_UNLOCK(tx_ring);
1189}
1190
1191static void
1192ena_free_all_tx_bufs(struct ena_adapter *adapter)

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