if_em.h (27067774dce3388702a4cf744d7096c6fb71b688) if_em.h (f2d6ace4a684fcb98293983758c73d703338a78b)
1/******************************************************************************
1/*$FreeBSD$*/
2#include "opt_em.h"
3#include "opt_ddb.h"
4#include "opt_inet.h"
5#include "opt_inet6.h"
2
6
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
7#ifdef HAVE_KERNEL_OPTION_HEADERS
8#include "opt_device_polling.h"
9#endif
31
10
32******************************************************************************/
33/*$FreeBSD$*/
11#include <sys/param.h>
12#include <sys/systm.h>
13#ifdef DDB
14#include <sys/types.h>
15#include <ddb/ddb.h>
16#endif
17#if __FreeBSD_version >= 800000
18#include <sys/buf_ring.h>
19#endif
20#include <sys/bus.h>
21#include <sys/endian.h>
22#include <sys/kernel.h>
23#include <sys/kthread.h>
24#include <sys/malloc.h>
25#include <sys/mbuf.h>
26#include <sys/module.h>
27#include <sys/rman.h>
28#include <sys/smp.h>
29#include <sys/socket.h>
30#include <sys/sockio.h>
31#include <sys/sysctl.h>
32#include <sys/taskqueue.h>
33#include <sys/eventhandler.h>
34#include <machine/bus.h>
35#include <machine/resource.h>
34
36
37#include <net/bpf.h>
38#include <net/ethernet.h>
39#include <net/if.h>
40#include <net/if_var.h>
41#include <net/if_arp.h>
42#include <net/if_dl.h>
43#include <net/if_media.h>
44#include <net/iflib.h>
35
45
46#include <net/if_types.h>
47#include <net/if_vlan_var.h>
48
49#include <netinet/in_systm.h>
50#include <netinet/in.h>
51#include <netinet/if_ether.h>
52#include <netinet/ip.h>
53#include <netinet/ip6.h>
54#include <netinet/tcp.h>
55#include <netinet/udp.h>
56
57#include <machine/in_cksum.h>
58#include <dev/led/led.h>
59#include <dev/pci/pcivar.h>
60#include <dev/pci/pcireg.h>
61
62#include "e1000_api.h"
63#include "e1000_82571.h"
64#include "ifdi_if.h"
65
66
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40/* Tunables */
41
42/*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
67#ifndef _EM_H_DEFINED_
68#define _EM_H_DEFINED_
69
70
71/* Tunables */
72
73/*
74 * EM_TXD: Maximum number of Transmit Descriptors
75 * Valid Range: 80-256 for 82542 and 82543-based adapters
76 * 80-4096 for others
77 * Default Value: 256
78 * This value is the number of transmit descriptors allocated by the driver.
79 * Increasing this value allows the driver to queue more transmits. Each
80 * descriptor is 16 bytes.
81 * Since TDLEN should be multiple of 128bytes, the number of transmit
82 * desscriptors should meet the following condition.
83 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
84 */
54#define EM_MIN_TXD 80
85#define EM_MIN_TXD 128
55#define EM_MAX_TXD 4096
86#define EM_MAX_TXD 4096
56#ifdef EM_MULTIQUEUE
57#define EM_DEFAULT_TXD 4096
58#else
59#define EM_DEFAULT_TXD 1024
60#endif
87#define EM_DEFAULT_TXD 1024
88#define EM_DEFAULT_MULTI_TXD 4096
61
62/*
63 * EM_RXD - Maximum number of receive Descriptors
64 * Valid Range: 80-256 for 82542 and 82543-based adapters
65 * 80-4096 for others
66 * Default Value: 256
67 * This value is the number of receive descriptors allocated by the driver.
68 * Increasing this value allows the driver to buffer more incoming packets.
69 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
70 * descriptor. The maximum MTU size is 16110.
71 * Since TDLEN should be multiple of 128bytes, the number of transmit
72 * desscriptors should meet the following condition.
73 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
74 */
89
90/*
91 * EM_RXD - Maximum number of receive Descriptors
92 * Valid Range: 80-256 for 82542 and 82543-based adapters
93 * 80-4096 for others
94 * Default Value: 256
95 * This value is the number of receive descriptors allocated by the driver.
96 * Increasing this value allows the driver to buffer more incoming packets.
97 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
98 * descriptor. The maximum MTU size is 16110.
99 * Since TDLEN should be multiple of 128bytes, the number of transmit
100 * desscriptors should meet the following condition.
101 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
102 */
75#define EM_MIN_RXD 80
103#define EM_MIN_RXD 128
76#define EM_MAX_RXD 4096
104#define EM_MAX_RXD 4096
77#ifdef EM_MULTIQUEUE
78#define EM_DEFAULT_RXD 4096
79#else
80#define EM_DEFAULT_RXD 1024
81#endif
105#define EM_DEFAULT_RXD 1024
106#define EM_DEFAULT_MULTI_RXD 4096
82
83/*
84 * EM_TIDV - Transmit Interrupt Delay Value
85 * Valid Range: 0-65535 (0=off)
86 * Default Value: 64
87 * This value delays the generation of transmit interrupts in units of
88 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
89 * efficiency if properly tuned for specific network traffic. If the

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144 */
145#ifdef EM_MULTIQUEUE
146#define EM_RADV 128
147#else
148#define EM_RADV 64
149#endif
150
151/*
107
108/*
109 * EM_TIDV - Transmit Interrupt Delay Value
110 * Valid Range: 0-65535 (0=off)
111 * Default Value: 64
112 * This value delays the generation of transmit interrupts in units of
113 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
114 * efficiency if properly tuned for specific network traffic. If the

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169 */
170#ifdef EM_MULTIQUEUE
171#define EM_RADV 128
172#else
173#define EM_RADV 64
174#endif
175
176/*
152 * This parameter controls the max duration of transmit watchdog.
153 */
154#define EM_WATCHDOG (10 * hz)
155
156/*
157 * This parameter controls when the driver calls the routine to reclaim
158 * transmit descriptors.
159 */
160#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
161
162/*
163 * This parameter controls whether or not autonegotation is enabled.
164 * 0 - Disable autonegotiation
165 * 1 - Enable autonegotiation
166 */
167#define DO_AUTO_NEG 1
168
169/*
170 * This parameter control whether or not the driver will wait for

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216#define EM_TX_IDLE 0x00000000
217#define EM_TX_BUSY 0x00000001
218#define EM_TX_HUNG 0x80000000
219#define EM_TX_MAXTRIES 10
220
221#define PCICFG_DESC_RING_STATUS 0xe4
222#define FLUSH_DESC_REQUIRED 0x100
223
177 * This parameter controls whether or not autonegotation is enabled.
178 * 0 - Disable autonegotiation
179 * 1 - Enable autonegotiation
180 */
181#define DO_AUTO_NEG 1
182
183/*
184 * This parameter control whether or not the driver will wait for

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230#define EM_TX_IDLE 0x00000000
231#define EM_TX_BUSY 0x00000001
232#define EM_TX_HUNG 0x80000000
233#define EM_TX_MAXTRIES 10
234
235#define PCICFG_DESC_RING_STATUS 0xe4
236#define FLUSH_DESC_REQUIRED 0x100
237
238
239#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \
240 ((hw->mac.type <= e1000_82576) ? 16 : 8))
241#define IGB_RX_HTHRESH 8
242#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
243 (adapter->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4)
244
245#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
246#define IGB_TX_HTHRESH 1
247#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \
248 (adapter->intr_type == IFLIB_INTR_MSIX) ? 1 : 16)
249
224/*
225 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
226 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
227 * also optimize cache line size effect. H/W supports up to cache line size 128.
228 */
229#define EM_DBA_ALIGN 128
230
231/*

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237 (1 << 24) | \
238 (1 << 25) /* Handle errata in MQ mode */
239#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
240
241/* PCI Config defines */
242#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
243#define EM_BAR_TYPE_MASK 0x00000001
244#define EM_BAR_TYPE_MMEM 0x00000000
250/*
251 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
252 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
253 * also optimize cache line size effect. H/W supports up to cache line size 128.
254 */
255#define EM_DBA_ALIGN 128
256
257/*

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263 (1 << 24) | \
264 (1 << 25) /* Handle errata in MQ mode */
265#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
266
267/* PCI Config defines */
268#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
269#define EM_BAR_TYPE_MASK 0x00000001
270#define EM_BAR_TYPE_MMEM 0x00000000
271#define EM_BAR_TYPE_IO 0x00000001
245#define EM_BAR_TYPE_FLASH 0x0014
246#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
247#define EM_BAR_MEM_TYPE_MASK 0x00000006
248#define EM_BAR_MEM_TYPE_32BIT 0x00000000
249#define EM_BAR_MEM_TYPE_64BIT 0x00000004
250#define EM_MSIX_BAR 3 /* On 82575 */
251
252/* More backward compatibility */

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274#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
275#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
276#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
277#define EM_MSIX_LINK 0x01000000 /* For 82574 use */
278#define ETH_ZLEN 60
279#define ETH_ADDR_LEN 6
280#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
281
272#define EM_BAR_TYPE_FLASH 0x0014
273#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
274#define EM_BAR_MEM_TYPE_MASK 0x00000006
275#define EM_BAR_MEM_TYPE_32BIT 0x00000000
276#define EM_BAR_MEM_TYPE_64BIT 0x00000004
277#define EM_MSIX_BAR 3 /* On 82575 */
278
279/* More backward compatibility */

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301#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
302#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
303#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
304#define EM_MSIX_LINK 0x01000000 /* For 82574 use */
305#define ETH_ZLEN 60
306#define ETH_ADDR_LEN 6
307#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
308
309#define IGB_PKTTYPE_MASK 0x0000FFF0
310#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
311
282/*
283 * 82574 has a nonstandard address for EIAC
284 * and since its only used in MSIX, and in
285 * the em driver only 82574 uses MSIX we can
286 * solve it just using this define.
287 */
288#define EM_EIAC 0x000DC
289/*
290 * 82574 only reports 3 MSI-X vectors by default;
291 * defines assisting with making it report 5 are
292 * located here.
293 */
294#define EM_NVM_PCIE_CTRL 0x1B
295#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
296#define EM_NVM_MSIX_N_SHIFT 7
297
312/*
313 * 82574 has a nonstandard address for EIAC
314 * and since its only used in MSIX, and in
315 * the em driver only 82574 uses MSIX we can
316 * solve it just using this define.
317 */
318#define EM_EIAC 0x000DC
319/*
320 * 82574 only reports 3 MSI-X vectors by default;
321 * defines assisting with making it report 5 are
322 * located here.
323 */
324#define EM_NVM_PCIE_CTRL 0x1B
325#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
326#define EM_NVM_MSIX_N_SHIFT 7
327
298/*
299 * Bus dma allocation structure used by
300 * e1000_dma_malloc and e1000_dma_free.
301 */
302struct em_dma_alloc {
303 bus_addr_t dma_paddr;
304 caddr_t dma_vaddr;
305 bus_dma_tag_t dma_tag;
306 bus_dmamap_t dma_map;
307 bus_dma_segment_t dma_seg;
308 int dma_nseg;
309};
310
311struct adapter;
312
313struct em_int_delay_info {
314 struct adapter *adapter; /* Back-pointer to the adapter struct */
315 int offset; /* Register offset to read/write */
316 int value; /* Current value in usecs */
317};
318
319/*
320 * The transmit ring, one per tx queue
321 */
322struct tx_ring {
323 struct adapter *adapter;
328struct adapter;
329
330struct em_int_delay_info {
331 struct adapter *adapter; /* Back-pointer to the adapter struct */
332 int offset; /* Register offset to read/write */
333 int value; /* Current value in usecs */
334};
335
336/*
337 * The transmit ring, one per tx queue
338 */
339struct tx_ring {
340 struct adapter *adapter;
324 struct mtx tx_mtx;
325 char mtx_name[16];
341 struct em_tx_queue *que;
326 u32 me;
342 u32 me;
327 u32 msix;
328 u32 ims;
329 int busy;
343 int busy;
330 struct em_dma_alloc txdma;
331 struct e1000_tx_desc *tx_base;
344 struct e1000_tx_desc *tx_base;
332 struct task tx_task;
333 struct taskqueue *tq;
334 u32 next_avail_desc;
335 u32 next_to_clean;
345 uint64_t tx_paddr;
336 struct em_txbuffer *tx_buffers;
346 struct em_txbuffer *tx_buffers;
337 volatile u16 tx_avail;
338 u32 tx_tso; /* last tx was tso */
347 u32 tx_tso; /* last tx was tso */
339 u16 last_hw_offload;
340 u8 last_hw_ipcso;
341 u8 last_hw_ipcss;
342 u8 last_hw_tucso;
343 u8 last_hw_tucss;
344#if __FreeBSD_version >= 800000
345 struct buf_ring *br;
346#endif
348
347 /* Interrupt resources */
349 /* Interrupt resources */
348 bus_dma_tag_t txtag;
349 void *tag;
350 struct resource *res;
351 unsigned long tx_irq;
352 unsigned long no_desc_avail;
350 void *tag;
351 struct resource *res;
352 unsigned long tx_irq;
353 unsigned long no_desc_avail;
354
355 /* Saved csum offloading context information */
356 int csum_flags;
357 int csum_lhlen;
358 int csum_iphlen;
359
360 int csum_thlen;
361 int csum_mss;
362 int csum_pktlen;
363
364 uint32_t csum_txd_upper;
365 uint32_t csum_txd_lower; /* last field */
353};
354
355/*
356 * The Receive ring, one per rx queue
357 */
358struct rx_ring {
359 struct adapter *adapter;
366};
367
368/*
369 * The Receive ring, one per rx queue
370 */
371struct rx_ring {
372 struct adapter *adapter;
373 struct em_rx_queue *que;
360 u32 me;
374 u32 me;
361 u32 msix;
362 u32 ims;
363 struct mtx rx_mtx;
364 char mtx_name[16];
365 u32 payload;
375 u32 payload;
366 struct task rx_task;
367 struct taskqueue *tq;
368 union e1000_rx_desc_extended *rx_base;
376 union e1000_rx_desc_extended *rx_base;
369 struct em_dma_alloc rxdma;
370 u32 next_to_refresh;
371 u32 next_to_check;
372 struct em_rxbuffer *rx_buffers;
373 struct mbuf *fmp;
374 struct mbuf *lmp;
377 uint64_t rx_paddr;
375
376 /* Interrupt resources */
377 void *tag;
378 struct resource *res;
378
379 /* Interrupt resources */
380 void *tag;
381 struct resource *res;
379 bus_dma_tag_t rxtag;
380 bool discard;
381
382 /* Soft stats */
383 unsigned long rx_irq;
384 unsigned long rx_discarded;
385 unsigned long rx_packets;
386 unsigned long rx_bytes;
387};
388
382 bool discard;
383
384 /* Soft stats */
385 unsigned long rx_irq;
386 unsigned long rx_discarded;
387 unsigned long rx_packets;
388 unsigned long rx_bytes;
389};
390
391struct em_tx_queue {
392 struct adapter *adapter;
393 u32 msix;
394 u32 eims; /* This queue's EIMS bit */
395 u32 me;
396 struct tx_ring txr;
397};
389
398
399struct em_rx_queue {
400 struct adapter *adapter;
401 u32 me;
402 u32 msix;
403 u32 eims;
404 struct rx_ring rxr;
405 u64 irqs;
406 struct if_irq que_irq;
407};
408
390/* Our adapter structure */
391struct adapter {
409/* Our adapter structure */
410struct adapter {
392 if_t ifp;
411 struct ifnet *ifp;
393 struct e1000_hw hw;
394
412 struct e1000_hw hw;
413
414 if_softc_ctx_t shared;
415 if_ctx_t ctx;
416#define tx_num_queues shared->isc_ntxqsets
417#define rx_num_queues shared->isc_nrxqsets
418#define intr_type shared->isc_intr
395 /* FreeBSD operating-system-specific structures. */
396 struct e1000_osdep osdep;
419 /* FreeBSD operating-system-specific structures. */
420 struct e1000_osdep osdep;
397 device_t dev;
421 struct device *dev;
398 struct cdev *led_dev;
399
422 struct cdev *led_dev;
423
424 struct em_tx_queue *tx_queues;
425 struct em_rx_queue *rx_queues;
426 struct if_irq irq;
427
400 struct resource *memory;
401 struct resource *flash;
428 struct resource *memory;
429 struct resource *flash;
402 struct resource *msix_mem;
430 struct resource *ioport;
431 int io_rid;
403
404 struct resource *res;
405 void *tag;
406 u32 linkvec;
407 u32 ivars;
408
432
433 struct resource *res;
434 void *tag;
435 u32 linkvec;
436 u32 ivars;
437
409 struct ifmedia media;
410 struct callout timer;
438 struct ifmedia *media;
411 int msix;
412 int if_flags;
439 int msix;
440 int if_flags;
413 int max_frame_size;
414 int min_frame_size;
441 int min_frame_size;
415 struct mtx core_mtx;
416 int em_insert_vlan_header;
417 u32 ims;
418 bool in_detach;
419
420 /* Task for FAST handling */
442 int em_insert_vlan_header;
443 u32 ims;
444 bool in_detach;
445
446 /* Task for FAST handling */
421 struct task link_task;
422 struct task que_task;
423 struct taskqueue *tq; /* private task queue */
447 struct grouptask link_task;
424
448
425 eventhandler_tag vlan_attach;
426 eventhandler_tag vlan_detach;
427
428 u16 num_vlans;
429 u8 num_queues;
430
431 /*
432 * Transmit rings:
433 * Allocated at run time, an array of rings.
434 */
435 struct tx_ring *tx_rings;
436 int num_tx_desc;
449 u16 num_vlans;
437 u32 txd_cmd;
438
450 u32 txd_cmd;
451
439 /*
440 * Receive rings:
441 * Allocated at run time, an array of rings.
442 */
443 struct rx_ring *rx_rings;
444 int num_rx_desc;
452 u32 tx_process_limit;
445 u32 rx_process_limit;
446 u32 rx_mbuf_sz;
447
448 /* Management and WOL features */
449 u32 wol;
450 bool has_manage;
451 bool has_amt;
452

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462 u32 shadow_vfta[EM_VFTA_SIZE];
463
464 /* Info about the interface */
465 u16 link_active;
466 u16 fc;
467 u16 link_speed;
468 u16 link_duplex;
469 u32 smartspeed;
453 u32 rx_process_limit;
454 u32 rx_mbuf_sz;
455
456 /* Management and WOL features */
457 u32 wol;
458 bool has_manage;
459 bool has_amt;
460

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470 u32 shadow_vfta[EM_VFTA_SIZE];
471
472 /* Info about the interface */
473 u16 link_active;
474 u16 fc;
475 u16 link_speed;
476 u16 link_duplex;
477 u32 smartspeed;
478 u32 dmac;
479 int link_mask;
470
480
481 u64 que_mask;
482
483
471 struct em_int_delay_info tx_int_delay;
472 struct em_int_delay_info tx_abs_int_delay;
473 struct em_int_delay_info rx_int_delay;
474 struct em_int_delay_info rx_abs_int_delay;
475 struct em_int_delay_info tx_itr;
476
477 /* Misc stats maintained by the driver */
478 unsigned long dropped_pkts;

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497 unsigned int vendor_id;
498 unsigned int device_id;
499 unsigned int subvendor_id;
500 unsigned int subdevice_id;
501 unsigned int index;
502} em_vendor_info_t;
503
504struct em_txbuffer {
484 struct em_int_delay_info tx_int_delay;
485 struct em_int_delay_info tx_abs_int_delay;
486 struct em_int_delay_info rx_int_delay;
487 struct em_int_delay_info rx_abs_int_delay;
488 struct em_int_delay_info tx_itr;
489
490 /* Misc stats maintained by the driver */
491 unsigned long dropped_pkts;

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510 unsigned int vendor_id;
511 unsigned int device_id;
512 unsigned int subvendor_id;
513 unsigned int subdevice_id;
514 unsigned int index;
515} em_vendor_info_t;
516
517struct em_txbuffer {
505 int next_eop; /* Index of the desc to watch */
506 struct mbuf *m_head;
507 bus_dmamap_t map; /* bus_dma map for packet */
518 int eop;
508};
509
519};
520
510struct em_rxbuffer {
511 int next_eop; /* Index of the desc to watch */
512 struct mbuf *m_head;
513 bus_dmamap_t map; /* bus_dma map for packet */
514 bus_addr_t paddr;
515};
516
521
517
518/*
519** Find the number of unrefreshed RX descriptors
520*/
521static inline u16
522e1000_rx_unrefreshed(struct rx_ring *rxr)
523{
524 struct adapter *adapter = rxr->adapter;
525
526 if (rxr->next_to_check > rxr->next_to_refresh)
527 return (rxr->next_to_check - rxr->next_to_refresh - 1);
528 else
529 return ((adapter->num_rx_desc + rxr->next_to_check) -
530 rxr->next_to_refresh - 1);
531}
532
533#define EM_CORE_LOCK_INIT(_sc, _name) \
534 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
535#define EM_TX_LOCK_INIT(_sc, _name) \
536 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
537#define EM_RX_LOCK_INIT(_sc, _name) \
538 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
539#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
540#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)

--- 18 unchanged lines hidden --- 		522#define EM_CORE_LOCK_INIT(_sc, _name) \
523 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
524#define EM_TX_LOCK_INIT(_sc, _name) \
525 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
526#define EM_RX_LOCK_INIT(_sc, _name) \
527 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
528#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
529#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)

--- 18 unchanged lines hidden ---