e1000_ich8lan.c (db06a6f4ef6cbe2fecc10a453cfa70611fc4ac27) e1000_ich8lan.c (4dab5c3769d953bed52fdd06bea77a96af745cfd)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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71static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
72static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
73static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
74static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
75static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
76static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
77static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
78static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 59 unchanged lines hidden (view full) ---

71static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
72static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
73static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
74static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
75static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
76static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
77static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
78static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
79 u8 *mc_addr_list,
80 u32 mc_addr_count);
79 u8 *mc_addr_list,
80 u32 mc_addr_count);
81static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
82static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
83static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
84static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
81static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
82static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
83static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
84static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
85 bool active);
85 bool active);
86static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
86static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
87 bool active);
87 bool active);
88static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
88static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
89 u16 words, u16 *data);
89 u16 words, u16 *data);
90static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
90static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
91 u16 words, u16 *data);
91 u16 words, u16 *data);
92static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
93static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
94static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
92static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
93static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
94static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
95 u16 *data);
95 u16 *data);
96static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
97static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
98static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
99static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
100static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
101static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
102static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
96static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
97static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
98static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
99static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
100static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
101static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
102static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
103 u16 *speed, u16 *duplex);
103 u16 *speed, u16 *duplex);
104static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
105static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
106static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
107static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
108static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
109static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
110static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
111static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
112static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
113static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
114static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
115static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
116static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
118static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
104static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
105static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
106static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
107static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
108static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
109static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
110static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
111static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
112static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
113static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
114static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
115static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
116static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
118static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 *data);
119 u32 offset, u8 *data);
120static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
120static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 size, u16 *data);
121 u8 size, u16 *data);
122static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
122static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
123 u32 offset, u16 *data);
123 u32 offset, u16 *data);
124static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
124static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
125 u32 offset, u8 byte);
125 u32 offset, u8 byte);
126static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
126static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
127 u32 offset, u8 data);
127 u32 offset, u8 data);
128static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 u8 size, u16 data);
129 u8 size, u16 data);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
134static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
135static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
130static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
134static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
135static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
138#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
138
139
140#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
141
139/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
140/* Offset 04h HSFSTS */
141union ich8_hws_flash_status {
142 struct ich8_hsfsts {
142/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
143/* Offset 04h HSFSTS */
144union ich8_hws_flash_status {
145 struct ich8_hsfsts {
143 u16 flcdone :1; /* bit 0 Flash Cycle Done */
144 u16 flcerr :1; /* bit 1 Flash Cycle Error */
145 u16 dael :1; /* bit 2 Direct Access error Log */
146 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
147 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
148 u16 reserved1 :2; /* bit 13:6 Reserved */
149 u16 reserved2 :6; /* bit 13:6 Reserved */
150 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
151 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
146 u16 flcdone:1; /* bit 0 Flash Cycle Done */
147 u16 flcerr:1; /* bit 1 Flash Cycle Error */
148 u16 dael:1; /* bit 2 Direct Access error Log */
149 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
150 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
151 u16 reserved1:2; /* bit 13:6 Reserved */
152 u16 reserved2:6; /* bit 13:6 Reserved */
153 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
154 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
152 } hsf_status;
153 u16 regval;
154};
155
156/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
157/* Offset 06h FLCTL */
158union ich8_hws_flash_ctrl {
159 struct ich8_hsflctl {
155 } hsf_status;
156 u16 regval;
157};
158
159/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
160/* Offset 06h FLCTL */
161union ich8_hws_flash_ctrl {
162 struct ich8_hsflctl {
160 u16 flcgo :1; /* 0 Flash Cycle Go */
161 u16 flcycle :2; /* 2:1 Flash Cycle */
162 u16 reserved :5; /* 7:3 Reserved */
163 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
164 u16 flockdn :6; /* 15:10 Reserved */
163 u16 flcgo:1; /* 0 Flash Cycle Go */
164 u16 flcycle:2; /* 2:1 Flash Cycle */
165 u16 reserved:5; /* 7:3 Reserved */
166 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
167 u16 flockdn:6; /* 15:10 Reserved */
165 } hsf_ctrl;
166 u16 regval;
167};
168
169/* ICH Flash Region Access Permissions */
170union ich8_hws_flash_regacc {
171 struct ich8_flracc {
168 } hsf_ctrl;
169 u16 regval;
170};
171
172/* ICH Flash Region Access Permissions */
173union ich8_hws_flash_regacc {
174 struct ich8_flracc {
172 u32 grra :8; /* 0:7 GbE region Read Access */
173 u32 grwa :8; /* 8:15 GbE region Write Access */
174 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
175 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
175 u32 grra:8; /* 0:7 GbE region Read Access */
176 u32 grwa:8; /* 8:15 GbE region Write Access */
177 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
178 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
176 } hsf_flregacc;
177 u16 regval;
178};
179
179 } hsf_flregacc;
180 u16 regval;
181};
182
183static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
184{
185 u32 ctrl;
186
187 DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan");
188
189 ctrl = E1000_READ_REG(hw, E1000_CTRL);
190 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
191 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
192 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
193 E1000_WRITE_FLUSH(hw);
194 usec_delay(10);
195 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
196 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
197}
198
180/**
181 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
182 * @hw: pointer to the HW structure
183 *
184 * Initialize family-specific PHY parameters and function pointers.
185 **/
186static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
187{
188 struct e1000_phy_info *phy = &hw->phy;
199/**
200 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
201 * @hw: pointer to the HW structure
202 *
203 * Initialize family-specific PHY parameters and function pointers.
204 **/
205static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
206{
207 struct e1000_phy_info *phy = &hw->phy;
189 u32 ctrl, fwsm;
190 s32 ret_val = E1000_SUCCESS;
191
192 DEBUGFUNC("e1000_init_phy_params_pchlan");
193
208 s32 ret_val = E1000_SUCCESS;
209
210 DEBUGFUNC("e1000_init_phy_params_pchlan");
211
194 phy->addr = 1;
195 phy->reset_delay_us = 100;
212 phy->addr = 1;
213 phy->reset_delay_us = 100;
196
214
197 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
198 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
199 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
200 phy->ops.read_reg = e1000_read_phy_reg_hv;
201 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
202 phy->ops.release = e1000_release_swflag_ich8lan;
203 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
204 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
205 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
206 phy->ops.write_reg = e1000_write_phy_reg_hv;
207 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
208 phy->ops.power_up = e1000_power_up_phy_copper;
209 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
210 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
215 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
216 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
217 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
218 phy->ops.set_page = e1000_set_page_igp;
219 phy->ops.read_reg = e1000_read_phy_reg_hv;
220 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
221 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
222 phy->ops.release = e1000_release_swflag_ich8lan;
223 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
224 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
225 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
226 phy->ops.write_reg = e1000_write_phy_reg_hv;
227 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
228 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
229 phy->ops.power_up = e1000_power_up_phy_copper;
230 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
231 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
211
232
212 /*
213 * The MAC-PHY interconnect may still be in SMBus mode
214 * after Sx->S0. If the manageability engine (ME) is
215 * disabled, then toggle the LANPHYPC Value bit to force
216 * the interconnect to PCIe mode.
217 */
218 fwsm = E1000_READ_REG(hw, E1000_FWSM);
219 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) &&
220 !(hw->phy.ops.check_reset_block(hw))) {
221 ctrl = E1000_READ_REG(hw, E1000_CTRL);
222 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
223 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
224 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
225 usec_delay(10);
226 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
227 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
233 if (!hw->phy.ops.check_reset_block(hw)) {
234 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
235
236 /*
237 * The MAC-PHY interconnect may still be in SMBus mode after
238 * Sx->S0. If resetting the PHY is not blocked, toggle the
239 * LANPHYPC Value bit to force the interconnect to PCIe mode.
240 */
241 e1000_toggle_lanphypc_value_ich8lan(hw);
228 msec_delay(50);
229
230 /*
231 * Gate automatic PHY configuration by hardware on
232 * non-managed 82579
233 */
242 msec_delay(50);
243
244 /*
245 * Gate automatic PHY configuration by hardware on
246 * non-managed 82579
247 */
234 if (hw->mac.type == e1000_pch2lan)
248 if ((hw->mac.type == e1000_pch2lan) &&
249 !(fwsm & E1000_ICH_FWSM_FW_VALID))
235 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
250 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
236 }
237
251
238 /*
239 * Reset the PHY before any acccess to it. Doing so, ensures that
240 * the PHY is in a known good state before we read/write PHY registers.
241 * The generic reset is sufficient here, because we haven't determined
242 * the PHY type yet.
243 */
244 ret_val = e1000_phy_hw_reset_generic(hw);
245 if (ret_val)
246 goto out;
252 /*
253 * Reset the PHY before any access to it. Doing so, ensures
254 * that the PHY is in a known good state before we read/write
255 * PHY registers. The generic reset is sufficient here,
256 * because we haven't determined the PHY type yet.
257 */
258 ret_val = e1000_phy_hw_reset_generic(hw);
259 if (ret_val)
260 goto out;
247
261
248 /* Ungate automatic PHY configuration on non-managed 82579 */
249 if ((hw->mac.type == e1000_pch2lan) &&
250 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
251 msec_delay(10);
252 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
262 /* Ungate automatic PHY configuration on non-managed 82579 */
263 if ((hw->mac.type == e1000_pch2lan) &&
264 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
265 msec_delay(10);
266 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
267 }
253 }
254
255 phy->id = e1000_phy_unknown;
256 switch (hw->mac.type) {
257 default:
258 ret_val = e1000_get_phy_id(hw);
259 if (ret_val)
260 goto out;

--- 49 unchanged lines hidden (view full) ---

310static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
311{
312 struct e1000_phy_info *phy = &hw->phy;
313 s32 ret_val = E1000_SUCCESS;
314 u16 i = 0;
315
316 DEBUGFUNC("e1000_init_phy_params_ich8lan");
317
268 }
269
270 phy->id = e1000_phy_unknown;
271 switch (hw->mac.type) {
272 default:
273 ret_val = e1000_get_phy_id(hw);
274 if (ret_val)
275 goto out;

--- 49 unchanged lines hidden (view full) ---

325static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
326{
327 struct e1000_phy_info *phy = &hw->phy;
328 s32 ret_val = E1000_SUCCESS;
329 u16 i = 0;
330
331 DEBUGFUNC("e1000_init_phy_params_ich8lan");
332
318 phy->addr = 1;
319 phy->reset_delay_us = 100;
333 phy->addr = 1;
334 phy->reset_delay_us = 100;
320
335
321 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
322 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
323 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
324 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
325 phy->ops.read_reg = e1000_read_phy_reg_igp;
326 phy->ops.release = e1000_release_swflag_ich8lan;
327 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
328 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
329 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
330 phy->ops.write_reg = e1000_write_phy_reg_igp;
331 phy->ops.power_up = e1000_power_up_phy_copper;
332 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
336 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
337 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
338 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
339 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
340 phy->ops.read_reg = e1000_read_phy_reg_igp;
341 phy->ops.release = e1000_release_swflag_ich8lan;
342 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
343 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
344 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
345 phy->ops.write_reg = e1000_write_phy_reg_igp;
346 phy->ops.power_up = e1000_power_up_phy_copper;
347 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
333
334 /*
335 * We may need to do this twice - once for IGP and if that fails,
336 * we'll set BM func pointers and try again
337 */
338 ret_val = e1000_determine_phy_address(hw);
339 if (ret_val) {
340 phy->ops.write_reg = e1000_write_phy_reg_bm;

--- 92 unchanged lines hidden (view full) ---

433 /* flash_base_addr is byte-aligned */
434 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
435
436 /*
437 * find total size of the NVM, then cut in half since the total
438 * size represents two separate NVM banks.
439 */
440 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
348
349 /*
350 * We may need to do this twice - once for IGP and if that fails,
351 * we'll set BM func pointers and try again
352 */
353 ret_val = e1000_determine_phy_address(hw);
354 if (ret_val) {
355 phy->ops.write_reg = e1000_write_phy_reg_bm;

--- 92 unchanged lines hidden (view full) ---

448 /* flash_base_addr is byte-aligned */
449 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
450
451 /*
452 * find total size of the NVM, then cut in half since the total
453 * size represents two separate NVM banks.
454 */
455 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
441 << FLASH_SECTOR_ADDR_SHIFT;
456 << FLASH_SECTOR_ADDR_SHIFT;
442 nvm->flash_bank_size /= 2;
443 /* Adjust to word count */
444 nvm->flash_bank_size /= sizeof(u16);
445
446 nvm->word_size = E1000_SHADOW_RAM_WORDS;
447
448 /* Clear shadow ram */
449 for (i = 0; i < nvm->word_size; i++) {
450 dev_spec->shadow_ram[i].modified = FALSE;
451 dev_spec->shadow_ram[i].value = 0xFFFF;
452 }
453
454 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
455 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
456
457 /* Function Pointers */
457 nvm->flash_bank_size /= 2;
458 /* Adjust to word count */
459 nvm->flash_bank_size /= sizeof(u16);
460
461 nvm->word_size = E1000_SHADOW_RAM_WORDS;
462
463 /* Clear shadow ram */
464 for (i = 0; i < nvm->word_size; i++) {
465 dev_spec->shadow_ram[i].modified = FALSE;
466 dev_spec->shadow_ram[i].value = 0xFFFF;
467 }
468
469 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
470 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
471
472 /* Function Pointers */
458 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
459 nvm->ops.release = e1000_release_nvm_ich8lan;
460 nvm->ops.read = e1000_read_nvm_ich8lan;
461 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
473 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
474 nvm->ops.release = e1000_release_nvm_ich8lan;
475 nvm->ops.read = e1000_read_nvm_ich8lan;
476 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
462 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
477 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
463 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
464 nvm->ops.write = e1000_write_nvm_ich8lan;
478 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
479 nvm->ops.write = e1000_write_nvm_ich8lan;
465
466out:
467 return ret_val;
468}
469
470/**
471 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
472 * @hw: pointer to the HW structure
473 *
474 * Initialize family-specific MAC parameters and function
475 * pointers.
476 **/
477static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
478{
479 struct e1000_mac_info *mac = &hw->mac;
480
481out:
482 return ret_val;
483}
484
485/**
486 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
487 * @hw: pointer to the HW structure
488 *
489 * Initialize family-specific MAC parameters and function
490 * pointers.
491 **/
492static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
493{
494 struct e1000_mac_info *mac = &hw->mac;
480 u16 pci_cfg;
481
482 DEBUGFUNC("e1000_init_mac_params_ich8lan");
483
484 /* Set media type function pointer */
485 hw->phy.media_type = e1000_media_type_copper;
486
487 /* Set mta register count */
488 mac->mta_reg_count = 32;

--- 55 unchanged lines hidden (view full) ---

544 case e1000_pch2lan:
545 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
546 mac->ops.rar_set = e1000_rar_set_pch2lan;
547 /* multicast address update for pch2 */
548 mac->ops.update_mc_addr_list =
549 e1000_update_mc_addr_list_pch2lan;
550 /* fall-through */
551 case e1000_pchlan:
495
496 DEBUGFUNC("e1000_init_mac_params_ich8lan");
497
498 /* Set media type function pointer */
499 hw->phy.media_type = e1000_media_type_copper;
500
501 /* Set mta register count */
502 mac->mta_reg_count = 32;

--- 55 unchanged lines hidden (view full) ---

558 case e1000_pch2lan:
559 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
560 mac->ops.rar_set = e1000_rar_set_pch2lan;
561 /* multicast address update for pch2 */
562 mac->ops.update_mc_addr_list =
563 e1000_update_mc_addr_list_pch2lan;
564 /* fall-through */
565 case e1000_pchlan:
552 /* save PCH revision_id */
553 e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
554 hw->revision_id = (u8)(pci_cfg &= 0x000F);
555 /* check management mode */
556 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
557 /* ID LED init */
558 mac->ops.id_led_init = e1000_id_led_init_pchlan;
559 /* setup LED */
560 mac->ops.setup_led = e1000_setup_led_pchlan;
561 /* cleanup LED */
562 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
563 /* turn on/off LED */
564 mac->ops.led_on = e1000_led_on_pchlan;
565 mac->ops.led_off = e1000_led_off_pchlan;
566 break;
567 default:
568 break;
569 }
570
566 /* check management mode */
567 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
568 /* ID LED init */
569 mac->ops.id_led_init = e1000_id_led_init_pchlan;
570 /* setup LED */
571 mac->ops.setup_led = e1000_setup_led_pchlan;
572 /* cleanup LED */
573 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
574 /* turn on/off LED */
575 mac->ops.led_on = e1000_led_on_pchlan;
576 mac->ops.led_off = e1000_led_off_pchlan;
577 break;
578 default:
579 break;
580 }
581
582#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
583 if (mac->type == e1000_pch_lpt) {
584 }
585
586#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
571 /* Enable PCS Lock-loss workaround for ICH8 */
572 if (mac->type == e1000_ich8lan)
573 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
574
575 /* Gate automatic PHY configuration by hardware on managed 82579 */
576 if ((mac->type == e1000_pch2lan) &&
577 (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
578 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);

--- 5 unchanged lines hidden (view full) ---

584 * e1000_set_eee_pchlan - Enable/disable EEE support
585 * @hw: pointer to the HW structure
586 *
587 * Enable/disable EEE based on setting in dev_spec structure. The bits in
588 * the LPI Control register will remain set only if/when link is up.
589 **/
590static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
591{
587 /* Enable PCS Lock-loss workaround for ICH8 */
588 if (mac->type == e1000_ich8lan)
589 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
590
591 /* Gate automatic PHY configuration by hardware on managed 82579 */
592 if ((mac->type == e1000_pch2lan) &&
593 (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
594 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);

--- 5 unchanged lines hidden (view full) ---

600 * e1000_set_eee_pchlan - Enable/disable EEE support
601 * @hw: pointer to the HW structure
602 *
603 * Enable/disable EEE based on setting in dev_spec structure. The bits in
604 * the LPI Control register will remain set only if/when link is up.
605 **/
606static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
607{
608 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
592 s32 ret_val = E1000_SUCCESS;
593 u16 phy_reg;
594
595 DEBUGFUNC("e1000_set_eee_pchlan");
596
597 if (hw->phy.type != e1000_phy_82579)
598 goto out;
599
600 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
601 if (ret_val)
602 goto out;
603
609 s32 ret_val = E1000_SUCCESS;
610 u16 phy_reg;
611
612 DEBUGFUNC("e1000_set_eee_pchlan");
613
614 if (hw->phy.type != e1000_phy_82579)
615 goto out;
616
617 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
618 if (ret_val)
619 goto out;
620
604 if (hw->dev_spec.ich8lan.eee_disable)
621 if (dev_spec->eee_disable)
605 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
606 else
607 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
608
609 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
610out:
611 return ret_val;
612}

--- 6 unchanged lines hidden (view full) ---

619 * change in link status has been detected, then we read the PHY registers
620 * to get the current speed/duplex if link exists.
621 **/
622static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
623{
624 struct e1000_mac_info *mac = &hw->mac;
625 s32 ret_val;
626 bool link;
622 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
623 else
624 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
625
626 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
627out:
628 return ret_val;
629}

--- 6 unchanged lines hidden (view full) ---

636 * change in link status has been detected, then we read the PHY registers
637 * to get the current speed/duplex if link exists.
638 **/
639static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
640{
641 struct e1000_mac_info *mac = &hw->mac;
642 s32 ret_val;
643 bool link;
644 u16 phy_reg;
627
628 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
629
630 /*
631 * We only want to go out to the PHY registers to see if Auto-Neg
632 * has completed and/or if our link status has changed. The
633 * get_link_status flag is set upon receiving a Link Status
634 * Change or Rx Sequence Error interrupt.

--- 13 unchanged lines hidden (view full) ---

648 goto out;
649
650 if (hw->mac.type == e1000_pchlan) {
651 ret_val = e1000_k1_gig_workaround_hv(hw, link);
652 if (ret_val)
653 goto out;
654 }
655
645
646 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
647
648 /*
649 * We only want to go out to the PHY registers to see if Auto-Neg
650 * has completed and/or if our link status has changed. The
651 * get_link_status flag is set upon receiving a Link Status
652 * Change or Rx Sequence Error interrupt.

--- 13 unchanged lines hidden (view full) ---

666 goto out;
667
668 if (hw->mac.type == e1000_pchlan) {
669 ret_val = e1000_k1_gig_workaround_hv(hw, link);
670 if (ret_val)
671 goto out;
672 }
673
674#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
675 if (hw->mac.type == e1000_pch_lpt) {
676 }
677
678#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
656 if (!link)
657 goto out; /* No link detected */
658
659 mac->get_link_status = FALSE;
660
679 if (!link)
680 goto out; /* No link detected */
681
682 mac->get_link_status = FALSE;
683
661 if (hw->phy.type == e1000_phy_82578) {
662 ret_val = e1000_link_stall_workaround_hv(hw);
663 if (ret_val)
664 goto out;
665 }
666
667 if (hw->mac.type == e1000_pch2lan) {
684 switch (hw->mac.type) {
685 case e1000_pch2lan:
668 ret_val = e1000_k1_workaround_lv(hw);
669 if (ret_val)
670 goto out;
686 ret_val = e1000_k1_workaround_lv(hw);
687 if (ret_val)
688 goto out;
689 /* fall-thru */
690 case e1000_pchlan:
691 if (hw->phy.type == e1000_phy_82578) {
692 ret_val = e1000_link_stall_workaround_hv(hw);
693 if (ret_val)
694 goto out;
695 }
696
697 /*
698 * Workaround for PCHx parts in half-duplex:
699 * Set the number of preambles removed from the packet
700 * when it is passed from the PHY to the MAC to prevent
701 * the MAC from misinterpreting the packet type.
702 */
703 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
704 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
705
706 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
707 E1000_STATUS_FD)
708 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
709
710 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
711 break;
712 default:
713 break;
671 }
672
673 /*
674 * Check if there was DownShift, must be checked
675 * immediately after link-up
676 */
677 e1000_check_downshift_generic(hw);
678

--- 110 unchanged lines hidden (view full) ---

789 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
790 break;
791
792 msec_delay_irq(1);
793 timeout--;
794 }
795
796 if (!timeout) {
714 }
715
716 /*
717 * Check if there was DownShift, must be checked
718 * immediately after link-up
719 */
720 e1000_check_downshift_generic(hw);
721

--- 110 unchanged lines hidden (view full) ---

832 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
833 break;
834
835 msec_delay_irq(1);
836 timeout--;
837 }
838
839 if (!timeout) {
797 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
840 DEBUGOUT("SW has already locked the resource.\n");
798 ret_val = -E1000_ERR_CONFIG;
799 goto out;
800 }
801
802 timeout = SW_FLAG_TIMEOUT;
803
804 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
805 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
806
807 while (timeout) {
808 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
809 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
810 break;
811
812 msec_delay_irq(1);
813 timeout--;
814 }
815
816 if (!timeout) {
841 ret_val = -E1000_ERR_CONFIG;
842 goto out;
843 }
844
845 timeout = SW_FLAG_TIMEOUT;
846
847 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
848 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
849
850 while (timeout) {
851 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
852 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
853 break;
854
855 msec_delay_irq(1);
856 timeout--;
857 }
858
859 if (!timeout) {
817 DEBUGOUT("Failed to acquire the semaphore.\n");
860 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
861 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
818 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
819 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
820 ret_val = -E1000_ERR_CONFIG;
821 goto out;
822 }
823
824out:
825 if (ret_val)

--- 87 unchanged lines hidden (view full) ---

913
914 DEBUGFUNC("e1000_rar_set_pch2lan");
915
916 /*
917 * HW expects these in little endian so we reverse the byte order
918 * from network order (big endian) to little endian
919 */
920 rar_low = ((u32) addr[0] |
862 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
863 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
864 ret_val = -E1000_ERR_CONFIG;
865 goto out;
866 }
867
868out:
869 if (ret_val)

--- 87 unchanged lines hidden (view full) ---

957
958 DEBUGFUNC("e1000_rar_set_pch2lan");
959
960 /*
961 * HW expects these in little endian so we reverse the byte order
962 * from network order (big endian) to little endian
963 */
964 rar_low = ((u32) addr[0] |
921 ((u32) addr[1] << 8) |
922 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
965 ((u32) addr[1] << 8) |
966 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
923
924 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
925
926 /* If MAC address zero, no need to set the AV bit */
927 if (rar_low || rar_high)
928 rar_high |= E1000_RAH_AV;
929
930 if (index == 0) {

--- 27 unchanged lines hidden (view full) ---

958 * @hw: pointer to the HW structure
959 * @mc_addr_list: array of multicast addresses to program
960 * @mc_addr_count: number of multicast addresses to program
961 *
962 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
963 * The caller must have a packed mc_addr_list of multicast addresses.
964 **/
965static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
967
968 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
969
970 /* If MAC address zero, no need to set the AV bit */
971 if (rar_low || rar_high)
972 rar_high |= E1000_RAH_AV;
973
974 if (index == 0) {

--- 27 unchanged lines hidden (view full) ---

1002 * @hw: pointer to the HW structure
1003 * @mc_addr_list: array of multicast addresses to program
1004 * @mc_addr_count: number of multicast addresses to program
1005 *
1006 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1007 * The caller must have a packed mc_addr_list of multicast addresses.
1008 **/
1009static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
966 u8 *mc_addr_list,
967 u32 mc_addr_count)
1010 u8 *mc_addr_list,
1011 u32 mc_addr_count)
968{
1012{
1013 u16 phy_reg = 0;
969 int i;
1014 int i;
1015 s32 ret_val;
970
971 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
972
973 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
974
1016
1017 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1018
1019 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1020
1021 ret_val = hw->phy.ops.acquire(hw);
1022 if (ret_val)
1023 return;
1024
1025 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1026 if (ret_val)
1027 goto release;
1028
975 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1029 for (i = 0; i < hw->mac.mta_reg_count; i++) {
976 hw->phy.ops.write_reg(hw, BM_MTA(i),
977 (u16)(hw->mac.mta_shadow[i] & 0xFFFF));
978 hw->phy.ops.write_reg(hw, (BM_MTA(i) + 1),
979 (u16)((hw->mac.mta_shadow[i] >> 16) &
980 0xFFFF));
1030 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1031 (u16)(hw->mac.mta_shadow[i] &
1032 0xFFFF));
1033 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1034 (u16)((hw->mac.mta_shadow[i] >> 16) &
1035 0xFFFF));
981 }
1036 }
1037
1038 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1039
1040release:
1041 hw->phy.ops.release(hw);
982}
983
984/**
985 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
986 * @hw: pointer to the HW structure
987 *
988 * Checks if firmware is blocking the reset of the PHY.
989 * This is a function pointer entry point only called by
990 * reset routines.
991 **/
992static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
993{
994 u32 fwsm;
995
996 DEBUGFUNC("e1000_check_reset_block_ich8lan");
997
1042}
1043
1044/**
1045 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1046 * @hw: pointer to the HW structure
1047 *
1048 * Checks if firmware is blocking the reset of the PHY.
1049 * This is a function pointer entry point only called by
1050 * reset routines.
1051 **/
1052static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1053{
1054 u32 fwsm;
1055
1056 DEBUGFUNC("e1000_check_reset_block_ich8lan");
1057
998 if (hw->phy.reset_disable)
999 return E1000_BLK_PHY_RESET;
1000
1001 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1002
1003 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
1058 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1059
1060 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
1004 : E1000_BLK_PHY_RESET;
1061 : E1000_BLK_PHY_RESET;
1005}
1006
1007/**
1008 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1009 * @hw: pointer to the HW structure
1010 *
1011 * Assumes semaphore already acquired.
1012 *

--- 169 unchanged lines hidden (view full) ---

1182 ret_val = hw->phy.ops.acquire(hw);
1183 if (ret_val)
1184 goto out;
1185
1186 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1187 if (link) {
1188 if (hw->phy.type == e1000_phy_82578) {
1189 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1062}
1063
1064/**
1065 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1066 * @hw: pointer to the HW structure
1067 *
1068 * Assumes semaphore already acquired.
1069 *

--- 169 unchanged lines hidden (view full) ---

1239 ret_val = hw->phy.ops.acquire(hw);
1240 if (ret_val)
1241 goto out;
1242
1243 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1244 if (link) {
1245 if (hw->phy.type == e1000_phy_82578) {
1246 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1190 &status_reg);
1247 &status_reg);
1191 if (ret_val)
1192 goto release;
1193
1194 status_reg &= BM_CS_STATUS_LINK_UP |
1248 if (ret_val)
1249 goto release;
1250
1251 status_reg &= BM_CS_STATUS_LINK_UP |
1195 BM_CS_STATUS_RESOLVED |
1196 BM_CS_STATUS_SPEED_MASK;
1252 BM_CS_STATUS_RESOLVED |
1253 BM_CS_STATUS_SPEED_MASK;
1197
1198 if (status_reg == (BM_CS_STATUS_LINK_UP |
1254
1255 if (status_reg == (BM_CS_STATUS_LINK_UP |
1199 BM_CS_STATUS_RESOLVED |
1200 BM_CS_STATUS_SPEED_1000))
1256 BM_CS_STATUS_RESOLVED |
1257 BM_CS_STATUS_SPEED_1000))
1201 k1_enable = FALSE;
1202 }
1203
1204 if (hw->phy.type == e1000_phy_82577) {
1205 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1258 k1_enable = FALSE;
1259 }
1260
1261 if (hw->phy.type == e1000_phy_82577) {
1262 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1206 &status_reg);
1263 &status_reg);
1207 if (ret_val)
1208 goto release;
1209
1210 status_reg &= HV_M_STATUS_LINK_UP |
1264 if (ret_val)
1265 goto release;
1266
1267 status_reg &= HV_M_STATUS_LINK_UP |
1211 HV_M_STATUS_AUTONEG_COMPLETE |
1212 HV_M_STATUS_SPEED_MASK;
1268 HV_M_STATUS_AUTONEG_COMPLETE |
1269 HV_M_STATUS_SPEED_MASK;
1213
1214 if (status_reg == (HV_M_STATUS_LINK_UP |
1270
1271 if (status_reg == (HV_M_STATUS_LINK_UP |
1215 HV_M_STATUS_AUTONEG_COMPLETE |
1216 HV_M_STATUS_SPEED_1000))
1272 HV_M_STATUS_AUTONEG_COMPLETE |
1273 HV_M_STATUS_SPEED_1000))
1217 k1_enable = FALSE;
1218 }
1219
1220 /* Link stall fix for link up */
1221 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1274 k1_enable = FALSE;
1275 }
1276
1277 /* Link stall fix for link up */
1278 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1222 0x0100);
1279 0x0100);
1223 if (ret_val)
1224 goto release;
1225
1226 } else {
1227 /* Link stall fix for link down */
1228 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1280 if (ret_val)
1281 goto release;
1282
1283 } else {
1284 /* Link stall fix for link down */
1285 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1229 0x4100);
1286 0x4100);
1230 if (ret_val)
1231 goto release;
1232 }
1233
1234 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1235
1236release:
1237 hw->phy.ops.release(hw);

--- 16 unchanged lines hidden (view full) ---

1254 s32 ret_val = E1000_SUCCESS;
1255 u32 ctrl_reg = 0;
1256 u32 ctrl_ext = 0;
1257 u32 reg = 0;
1258 u16 kmrn_reg = 0;
1259
1260 DEBUGFUNC("e1000_configure_k1_ich8lan");
1261
1287 if (ret_val)
1288 goto release;
1289 }
1290
1291 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1292
1293release:
1294 hw->phy.ops.release(hw);

--- 16 unchanged lines hidden (view full) ---

1311 s32 ret_val = E1000_SUCCESS;
1312 u32 ctrl_reg = 0;
1313 u32 ctrl_ext = 0;
1314 u32 reg = 0;
1315 u16 kmrn_reg = 0;
1316
1317 DEBUGFUNC("e1000_configure_k1_ich8lan");
1318
1262 ret_val = e1000_read_kmrn_reg_locked(hw,
1263 E1000_KMRNCTRLSTA_K1_CONFIG,
1264 &kmrn_reg);
1319 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1320 &kmrn_reg);
1265 if (ret_val)
1266 goto out;
1267
1268 if (k1_enable)
1269 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1270 else
1271 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1272
1321 if (ret_val)
1322 goto out;
1323
1324 if (k1_enable)
1325 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1326 else
1327 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1328
1273 ret_val = e1000_write_kmrn_reg_locked(hw,
1274 E1000_KMRNCTRLSTA_K1_CONFIG,
1275 kmrn_reg);
1329 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1330 kmrn_reg);
1276 if (ret_val)
1277 goto out;
1278
1279 usec_delay(20);
1280 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1281 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1282
1283 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1284 reg |= E1000_CTRL_FRCSPD;
1285 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1286
1287 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1331 if (ret_val)
1332 goto out;
1333
1334 usec_delay(20);
1335 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1336 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1337
1338 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1339 reg |= E1000_CTRL_FRCSPD;
1340 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1341
1342 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1343 E1000_WRITE_FLUSH(hw);
1288 usec_delay(20);
1289 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1290 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1344 usec_delay(20);
1345 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1346 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1347 E1000_WRITE_FLUSH(hw);
1291 usec_delay(20);
1292
1293out:
1294 return ret_val;
1295}
1296
1297/**
1298 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1299 * @hw: pointer to the HW structure
1300 * @d0_state: boolean if entering d0 or d3 device state
1301 *
1302 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1303 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1304 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1305 **/
1348 usec_delay(20);
1349
1350out:
1351 return ret_val;
1352}
1353
1354/**
1355 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1356 * @hw: pointer to the HW structure
1357 * @d0_state: boolean if entering d0 or d3 device state
1358 *
1359 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1360 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1361 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1362 **/
1306s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1363static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1307{
1308 s32 ret_val = 0;
1309 u32 mac_reg;
1310 u16 oem_reg;
1311
1312 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
1313
1314 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))

--- 22 unchanged lines hidden (view full) ---

1337 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1338
1339 if (d0_state) {
1340 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1341 oem_reg |= HV_OEM_BITS_GBE_DIS;
1342
1343 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1344 oem_reg |= HV_OEM_BITS_LPLU;
1364{
1365 s32 ret_val = 0;
1366 u32 mac_reg;
1367 u16 oem_reg;
1368
1369 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
1370
1371 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))

--- 22 unchanged lines hidden (view full) ---

1394 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1395
1396 if (d0_state) {
1397 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1398 oem_reg |= HV_OEM_BITS_GBE_DIS;
1399
1400 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1401 oem_reg |= HV_OEM_BITS_LPLU;
1402
1403 /* Set Restart auto-neg to activate the bits */
1404 if (!hw->phy.ops.check_reset_block(hw))
1405 oem_reg |= HV_OEM_BITS_RESTART_AN;
1345 } else {
1406 } else {
1346 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1407 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1408 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1347 oem_reg |= HV_OEM_BITS_GBE_DIS;
1348
1409 oem_reg |= HV_OEM_BITS_GBE_DIS;
1410
1349 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1411 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1412 E1000_PHY_CTRL_NOND0A_LPLU))
1350 oem_reg |= HV_OEM_BITS_LPLU;
1351 }
1413 oem_reg |= HV_OEM_BITS_LPLU;
1414 }
1352 /* Restart auto-neg to activate the bits */
1353 if (!hw->phy.ops.check_reset_block(hw))
1354 oem_reg |= HV_OEM_BITS_RESTART_AN;
1415
1355 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1356
1357out:
1358 hw->phy.ops.release(hw);
1359
1360 return ret_val;
1361}
1362
1363
1364/**
1416 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1417
1418out:
1419 hw->phy.ops.release(hw);
1420
1421 return ret_val;
1422}
1423
1424
1425/**
1365 * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
1366 * @hw: pointer to the HW structure
1367 **/
1368s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
1369{
1370 DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan");
1371
1372 if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
1373 return E1000_SUCCESS;
1374
1375 return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
1376}
1377
1378/**
1379 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1380 * @hw: pointer to the HW structure
1381 **/
1382static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1383{
1384 s32 ret_val;
1385 u16 data;
1386

--- 26 unchanged lines hidden (view full) ---

1413
1414 /* Set MDIO slow mode before any other MDIO access */
1415 if (hw->phy.type == e1000_phy_82577) {
1416 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1417 if (ret_val)
1418 goto out;
1419 }
1420
1426 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1427 * @hw: pointer to the HW structure
1428 **/
1429static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1430{
1431 s32 ret_val;
1432 u16 data;
1433

--- 26 unchanged lines hidden (view full) ---

1460
1461 /* Set MDIO slow mode before any other MDIO access */
1462 if (hw->phy.type == e1000_phy_82577) {
1463 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1464 if (ret_val)
1465 goto out;
1466 }
1467
1421 /* Hanksville M Phy init for IEEE. */
1422 if ((hw->revision_id == 2) &&
1423 (hw->phy.type == e1000_phy_82577) &&
1424 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
1425 hw->phy.ops.write_reg(hw, 0x10, 0x8823);
1426 hw->phy.ops.write_reg(hw, 0x11, 0x0018);
1427 hw->phy.ops.write_reg(hw, 0x10, 0x8824);
1428 hw->phy.ops.write_reg(hw, 0x11, 0x0016);
1429 hw->phy.ops.write_reg(hw, 0x10, 0x8825);
1430 hw->phy.ops.write_reg(hw, 0x11, 0x001A);
1431 hw->phy.ops.write_reg(hw, 0x10, 0x888C);
1432 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
1433 hw->phy.ops.write_reg(hw, 0x10, 0x888D);
1434 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
1435 hw->phy.ops.write_reg(hw, 0x10, 0x888E);
1436 hw->phy.ops.write_reg(hw, 0x11, 0x0007);
1437 hw->phy.ops.write_reg(hw, 0x10, 0x8827);
1438 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
1439 hw->phy.ops.write_reg(hw, 0x10, 0x8835);
1440 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
1441 hw->phy.ops.write_reg(hw, 0x10, 0x8834);
1442 hw->phy.ops.write_reg(hw, 0x11, 0x0001);
1443 hw->phy.ops.write_reg(hw, 0x10, 0x8833);
1444 hw->phy.ops.write_reg(hw, 0x11, 0x0002);
1445 }
1446
1447 if (((hw->phy.type == e1000_phy_82577) &&
1448 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1449 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1450 /* Disable generation of early preamble */
1451 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1452 if (ret_val)
1453 goto out;
1454
1455 /* Preamble tuning for SSC */
1468 if (((hw->phy.type == e1000_phy_82577) &&
1469 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1470 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1471 /* Disable generation of early preamble */
1472 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1473 if (ret_val)
1474 goto out;
1475
1476 /* Preamble tuning for SSC */
1456 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
1477 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
1478 0xA204);
1457 if (ret_val)
1458 goto out;
1459 }
1460
1461 if (hw->phy.type == e1000_phy_82578) {
1479 if (ret_val)
1480 goto out;
1481 }
1482
1483 if (hw->phy.type == e1000_phy_82578) {
1462 if (hw->revision_id < 3) {
1463 /* PHY config */
1464 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
1465 0x66C0);
1466 if (ret_val)
1467 goto out;
1468
1469 /* PHY config */
1470 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
1471 0xFFFF);
1472 if (ret_val)
1473 goto out;
1474 }
1475
1476 /*
1477 * Return registers to default by doing a soft reset then
1478 * writing 0x3140 to the control register.
1479 */
1480 if (hw->phy.revision < 2) {
1481 e1000_phy_sw_reset_generic(hw);
1482 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
1484 /*
1485 * Return registers to default by doing a soft reset then
1486 * writing 0x3140 to the control register.
1487 */
1488 if (hw->phy.revision < 2) {
1489 e1000_phy_sw_reset_generic(hw);
1490 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
1483 0x3140);
1491 0x3140);
1484 }
1485 }
1486
1492 }
1493 }
1494
1487 if ((hw->revision_id == 2) &&
1488 (hw->phy.type == e1000_phy_82577) &&
1489 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
1490 /*
1491 * Workaround for OEM (GbE) not operating after reset -
1492 * restart AN (twice)
1493 */
1494 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
1495 if (ret_val)
1496 goto out;
1497 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
1498 if (ret_val)
1499 goto out;
1500 }
1501
1502 /* Select page 0 */
1503 ret_val = hw->phy.ops.acquire(hw);
1504 if (ret_val)
1505 goto out;
1506
1507 hw->phy.addr = 1;
1508 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1509 hw->phy.ops.release(hw);

--- 7 unchanged lines hidden (view full) ---

1517 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
1518 if (ret_val)
1519 goto out;
1520
1521 /* Workaround for link disconnects on a busy hub in half duplex */
1522 ret_val = hw->phy.ops.acquire(hw);
1523 if (ret_val)
1524 goto out;
1495 /* Select page 0 */
1496 ret_val = hw->phy.ops.acquire(hw);
1497 if (ret_val)
1498 goto out;
1499
1500 hw->phy.addr = 1;
1501 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1502 hw->phy.ops.release(hw);

--- 7 unchanged lines hidden (view full) ---

1510 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
1511 if (ret_val)
1512 goto out;
1513
1514 /* Workaround for link disconnects on a busy hub in half duplex */
1515 ret_val = hw->phy.ops.acquire(hw);
1516 if (ret_val)
1517 goto out;
1525 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG_REG,
1526 &phy_data);
1518 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1527 if (ret_val)
1528 goto release;
1519 if (ret_val)
1520 goto release;
1529 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG_REG,
1530 phy_data & 0x00FF);
1521 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1522 phy_data & 0x00FF);
1531release:
1532 hw->phy.ops.release(hw);
1533out:
1534 return ret_val;
1535}
1536
1537/**
1538 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1539 * @hw: pointer to the HW structure
1540 **/
1541void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1542{
1543 u32 mac_reg;
1523release:
1524 hw->phy.ops.release(hw);
1525out:
1526 return ret_val;
1527}
1528
1529/**
1530 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1531 * @hw: pointer to the HW structure
1532 **/
1533void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1534{
1535 u32 mac_reg;
1544 u16 i;
1536 u16 i, phy_reg = 0;
1537 s32 ret_val;
1545
1546 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
1547
1538
1539 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
1540
1541 ret_val = hw->phy.ops.acquire(hw);
1542 if (ret_val)
1543 return;
1544 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1545 if (ret_val)
1546 goto release;
1547
1548 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1549 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1550 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
1548 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1549 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1550 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
1551 hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1552 hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1551 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1552 (u16)(mac_reg & 0xFFFF));
1553 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1554 (u16)((mac_reg >> 16) & 0xFFFF));
1555
1553 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
1556 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
1554 hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1555 hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1557 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1558 (u16)(mac_reg & 0xFFFF));
1559 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1560 (u16)((mac_reg & E1000_RAH_AV)
1561 >> 16));
1556 }
1562 }
1563
1564 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1565
1566release:
1567 hw->phy.ops.release(hw);
1557}
1558
1559static u32 e1000_calc_rx_da_crc(u8 mac[])
1560{
1561 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1562 u32 i, j, mask, crc;
1563
1564 DEBUGFUNC("e1000_calc_rx_da_crc");

--- 24 unchanged lines hidden (view full) ---

1589
1590 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
1591
1592 if (hw->mac.type != e1000_pch2lan)
1593 goto out;
1594
1595 /* disable Rx path while enabling/disabling workaround */
1596 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
1568}
1569
1570static u32 e1000_calc_rx_da_crc(u8 mac[])
1571{
1572 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1573 u32 i, j, mask, crc;
1574
1575 DEBUGFUNC("e1000_calc_rx_da_crc");

--- 24 unchanged lines hidden (view full) ---

1600
1601 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
1602
1603 if (hw->mac.type != e1000_pch2lan)
1604 goto out;
1605
1606 /* disable Rx path while enabling/disabling workaround */
1607 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
1597 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1608 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
1609 phy_reg | (1 << 14));
1598 if (ret_val)
1599 goto out;
1600
1601 if (enable) {
1602 /*
1603 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1604 * SHRAL/H) and initial CRC values to the MAC
1605 */

--- 65 unchanged lines hidden (view full) ---

1671 if (ret_val)
1672 goto out;
1673 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1674 data &= ~(0x3FF << 2);
1675 data |= (0x1A << 2);
1676 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1677 if (ret_val)
1678 goto out;
1610 if (ret_val)
1611 goto out;
1612
1613 if (enable) {
1614 /*
1615 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1616 * SHRAL/H) and initial CRC values to the MAC
1617 */

--- 65 unchanged lines hidden (view full) ---

1683 if (ret_val)
1684 goto out;
1685 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1686 data &= ~(0x3FF << 2);
1687 data |= (0x1A << 2);
1688 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1689 if (ret_val)
1690 goto out;
1679 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00);
1691 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
1680 if (ret_val)
1681 goto out;
1682 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1692 if (ret_val)
1693 goto out;
1694 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1683 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10));
1695 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
1696 (1 << 10));
1684 if (ret_val)
1685 goto out;
1686 } else {
1687 /* Write MAC register values back to h/w defaults */
1688 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1689 mac_reg &= ~(0xF << 14);
1690 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1691

--- 40 unchanged lines hidden (view full) ---

1732 data |= (0x8 << 2);
1733 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1734 if (ret_val)
1735 goto out;
1736 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
1737 if (ret_val)
1738 goto out;
1739 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1697 if (ret_val)
1698 goto out;
1699 } else {
1700 /* Write MAC register values back to h/w defaults */
1701 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1702 mac_reg &= ~(0xF << 14);
1703 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1704

--- 40 unchanged lines hidden (view full) ---

1745 data |= (0x8 << 2);
1746 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1747 if (ret_val)
1748 goto out;
1749 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
1750 if (ret_val)
1751 goto out;
1752 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1740 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10));
1753 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
1754 ~(1 << 10));
1741 if (ret_val)
1742 goto out;
1743 }
1744
1745 /* re-enable Rx path after enabling/disabling workaround */
1755 if (ret_val)
1756 goto out;
1757 }
1758
1759 /* re-enable Rx path after enabling/disabling workaround */
1746 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1760 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
1761 ~(1 << 14));
1747
1748out:
1749 return ret_val;
1750}
1751
1752/**
1753 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1754 * done after every PHY reset.

--- 5 unchanged lines hidden (view full) ---

1760 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
1761
1762 if (hw->mac.type != e1000_pch2lan)
1763 goto out;
1764
1765 /* Set MDIO slow mode before any other MDIO access */
1766 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1767
1762
1763out:
1764 return ret_val;
1765}
1766
1767/**
1768 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1769 * done after every PHY reset.

--- 5 unchanged lines hidden (view full) ---

1775 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
1776
1777 if (hw->mac.type != e1000_pch2lan)
1778 goto out;
1779
1780 /* Set MDIO slow mode before any other MDIO access */
1781 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1782
1783 ret_val = hw->phy.ops.acquire(hw);
1784 if (ret_val)
1785 goto out;
1786 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1787 I82579_MSE_THRESHOLD);
1788 if (ret_val)
1789 goto release;
1790 /* set MSE higher to enable link to stay up when noise is high */
1791 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1792 0x0034);
1793 if (ret_val)
1794 goto release;
1795 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1796 I82579_MSE_LINK_DOWN);
1797 if (ret_val)
1798 goto release;
1799 /* drop link after 5 times MSE threshold was reached */
1800 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1801 0x0005);
1802release:
1803 hw->phy.ops.release(hw);
1804
1768out:
1769 return ret_val;
1770}
1771
1772/**
1773 * e1000_k1_gig_workaround_lv - K1 Si workaround
1774 * @hw: pointer to the HW structure
1775 *
1776 * Workaround to set the K1 beacon duration for 82579 parts
1777 **/
1778static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1779{
1780 s32 ret_val = E1000_SUCCESS;
1781 u16 status_reg = 0;
1782 u32 mac_reg;
1805out:
1806 return ret_val;
1807}
1808
1809/**
1810 * e1000_k1_gig_workaround_lv - K1 Si workaround
1811 * @hw: pointer to the HW structure
1812 *
1813 * Workaround to set the K1 beacon duration for 82579 parts
1814 **/
1815static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1816{
1817 s32 ret_val = E1000_SUCCESS;
1818 u16 status_reg = 0;
1819 u32 mac_reg;
1820 u16 phy_reg;
1783
1784 DEBUGFUNC("e1000_k1_workaround_lv");
1785
1786 if (hw->mac.type != e1000_pch2lan)
1787 goto out;
1788
1789 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1790 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
1791 if (ret_val)
1792 goto out;
1793
1794 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1795 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1796 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1797 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1798
1821
1822 DEBUGFUNC("e1000_k1_workaround_lv");
1823
1824 if (hw->mac.type != e1000_pch2lan)
1825 goto out;
1826
1827 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1828 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
1829 if (ret_val)
1830 goto out;
1831
1832 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1833 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1834 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1835 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1836
1799 if (status_reg & HV_M_STATUS_SPEED_1000)
1837 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
1838 if (ret_val)
1839 goto out;
1840
1841 if (status_reg & HV_M_STATUS_SPEED_1000) {
1800 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1842 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1801 else
1843 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1844 } else {
1802 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1845 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1803
1846 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1847 }
1804 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1848 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1849 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
1805 }
1806
1807out:
1808 return ret_val;
1809}
1810
1811/**
1812 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware

--- 19 unchanged lines hidden (view full) ---

1832 else
1833 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1834
1835 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1836 return;
1837}
1838
1839/**
1850 }
1851
1852out:
1853 return ret_val;
1854}
1855
1856/**
1857 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware

--- 19 unchanged lines hidden (view full) ---

1877 else
1878 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1879
1880 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1881 return;
1882}
1883
1884/**
1840 * e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around
1841 * needed for Nahum3 + Hanksville testing, requested by HW team
1842 **/
1843static s32 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw)
1844{
1845 s32 ret_val = E1000_SUCCESS;
1846
1847 DEBUGFUNC("e1000_hv_phy_tuning_workaround_ich8lan");
1848
1849 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1850 if (ret_val)
1851 goto out;
1852
1853 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
1854 if (ret_val)
1855 goto out;
1856
1857 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0);
1858 if (ret_val)
1859 goto out;
1860
1861 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF);
1862
1863out:
1864 return ret_val;
1865}
1866
1867/**
1868 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1869 * @hw: pointer to the HW structure
1870 *
1871 * Check the appropriate indication the MAC has finished configuring the
1872 * PHY after a software reset.
1873 **/
1874static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1875{

--- 50 unchanged lines hidden (view full) ---

1926 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1927 if (ret_val)
1928 goto out;
1929 break;
1930 default:
1931 break;
1932 }
1933
1885 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1886 * @hw: pointer to the HW structure
1887 *
1888 * Check the appropriate indication the MAC has finished configuring the
1889 * PHY after a software reset.
1890 **/
1891static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1892{

--- 50 unchanged lines hidden (view full) ---

1943 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1944 if (ret_val)
1945 goto out;
1946 break;
1947 default:
1948 break;
1949 }
1950
1934 if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) {
1935 ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw);
1936 if (ret_val)
1937 goto out;
1951 /* Clear the host wakeup bit after lcd reset */
1952 if (hw->mac.type >= e1000_pchlan) {
1953 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
1954 reg &= ~BM_WUC_HOST_WU_BIT;
1955 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
1938 }
1939
1956 }
1957
1940 /* Dummy read to clear the phy wakeup bit after lcd reset */
1941 if (hw->mac.type >= e1000_pchlan)
1942 hw->phy.ops.read_reg(hw, BM_WUC, &reg);
1943
1944 /* Configure the LCD with the extended configuration region in NVM */
1945 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1946 if (ret_val)
1947 goto out;
1948
1949 /* Configure the LCD with the OEM bits in NVM */
1950 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
1951

--- 74 unchanged lines hidden (view full) ---

2026 if (ret_val)
2027 goto out;
2028
2029 if (active)
2030 oem_reg |= HV_OEM_BITS_LPLU;
2031 else
2032 oem_reg &= ~HV_OEM_BITS_LPLU;
2033
1958 /* Configure the LCD with the extended configuration region in NVM */
1959 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1960 if (ret_val)
1961 goto out;
1962
1963 /* Configure the LCD with the OEM bits in NVM */
1964 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
1965

--- 74 unchanged lines hidden (view full) ---

2040 if (ret_val)
2041 goto out;
2042
2043 if (active)
2044 oem_reg |= HV_OEM_BITS_LPLU;
2045 else
2046 oem_reg &= ~HV_OEM_BITS_LPLU;
2047
2034 oem_reg |= HV_OEM_BITS_RESTART_AN;
2048 if (!hw->phy.ops.check_reset_block(hw))
2049 oem_reg |= HV_OEM_BITS_RESTART_AN;
2050
2035 ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2036
2037out:
2038 return ret_val;
2039}
2040
2041/**
2042 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state

--- 33 unchanged lines hidden (view full) ---

2076 * Call gig speed drop workaround on LPLU before accessing
2077 * any PHY registers
2078 */
2079 if (hw->mac.type == e1000_ich8lan)
2080 e1000_gig_downshift_workaround_ich8lan(hw);
2081
2082 /* When LPLU is enabled, we should disable SmartSpeed */
2083 ret_val = phy->ops.read_reg(hw,
2051 ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2052
2053out:
2054 return ret_val;
2055}
2056
2057/**
2058 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state

--- 33 unchanged lines hidden (view full) ---

2092 * Call gig speed drop workaround on LPLU before accessing
2093 * any PHY registers
2094 */
2095 if (hw->mac.type == e1000_ich8lan)
2096 e1000_gig_downshift_workaround_ich8lan(hw);
2097
2098 /* When LPLU is enabled, we should disable SmartSpeed */
2099 ret_val = phy->ops.read_reg(hw,
2084 IGP01E1000_PHY_PORT_CONFIG,
2085 &data);
2100 IGP01E1000_PHY_PORT_CONFIG,
2101 &data);
2086 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2087 ret_val = phy->ops.write_reg(hw,
2102 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2103 ret_val = phy->ops.write_reg(hw,
2088 IGP01E1000_PHY_PORT_CONFIG,
2089 data);
2104 IGP01E1000_PHY_PORT_CONFIG,
2105 data);
2090 if (ret_val)
2091 goto out;
2092 } else {
2093 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2094 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2095
2096 if (phy->type != e1000_phy_igp_3)
2097 goto out;
2098
2099 /*
2100 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2101 * during Dx states where the power conservation is most
2102 * important. During driver activity we should enable
2103 * SmartSpeed, so performance is maintained.
2104 */
2105 if (phy->smart_speed == e1000_smart_speed_on) {
2106 ret_val = phy->ops.read_reg(hw,
2106 if (ret_val)
2107 goto out;
2108 } else {
2109 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2110 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2111
2112 if (phy->type != e1000_phy_igp_3)
2113 goto out;
2114
2115 /*
2116 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2117 * during Dx states where the power conservation is most
2118 * important. During driver activity we should enable
2119 * SmartSpeed, so performance is maintained.
2120 */
2121 if (phy->smart_speed == e1000_smart_speed_on) {
2122 ret_val = phy->ops.read_reg(hw,
2107 IGP01E1000_PHY_PORT_CONFIG,
2108 &data);
2123 IGP01E1000_PHY_PORT_CONFIG,
2124 &data);
2109 if (ret_val)
2110 goto out;
2111
2112 data |= IGP01E1000_PSCFR_SMART_SPEED;
2113 ret_val = phy->ops.write_reg(hw,
2125 if (ret_val)
2126 goto out;
2127
2128 data |= IGP01E1000_PSCFR_SMART_SPEED;
2129 ret_val = phy->ops.write_reg(hw,
2114 IGP01E1000_PHY_PORT_CONFIG,
2115 data);
2130 IGP01E1000_PHY_PORT_CONFIG,
2131 data);
2116 if (ret_val)
2117 goto out;
2118 } else if (phy->smart_speed == e1000_smart_speed_off) {
2119 ret_val = phy->ops.read_reg(hw,
2132 if (ret_val)
2133 goto out;
2134 } else if (phy->smart_speed == e1000_smart_speed_off) {
2135 ret_val = phy->ops.read_reg(hw,
2120 IGP01E1000_PHY_PORT_CONFIG,
2121 &data);
2136 IGP01E1000_PHY_PORT_CONFIG,
2137 &data);
2122 if (ret_val)
2123 goto out;
2124
2125 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2126 ret_val = phy->ops.write_reg(hw,
2138 if (ret_val)
2139 goto out;
2140
2141 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2142 ret_val = phy->ops.write_reg(hw,
2127 IGP01E1000_PHY_PORT_CONFIG,
2128 data);
2143 IGP01E1000_PHY_PORT_CONFIG,
2144 data);
2129 if (ret_val)
2130 goto out;
2131 }
2132 }
2133
2134out:
2135 return ret_val;
2136}

--- 32 unchanged lines hidden (view full) ---

2169 /*
2170 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2171 * during Dx states where the power conservation is most
2172 * important. During driver activity we should enable
2173 * SmartSpeed, so performance is maintained.
2174 */
2175 if (phy->smart_speed == e1000_smart_speed_on) {
2176 ret_val = phy->ops.read_reg(hw,
2145 if (ret_val)
2146 goto out;
2147 }
2148 }
2149
2150out:
2151 return ret_val;
2152}

--- 32 unchanged lines hidden (view full) ---

2185 /*
2186 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2187 * during Dx states where the power conservation is most
2188 * important. During driver activity we should enable
2189 * SmartSpeed, so performance is maintained.
2190 */
2191 if (phy->smart_speed == e1000_smart_speed_on) {
2192 ret_val = phy->ops.read_reg(hw,
2177 IGP01E1000_PHY_PORT_CONFIG,
2178 &data);
2193 IGP01E1000_PHY_PORT_CONFIG,
2194 &data);
2179 if (ret_val)
2180 goto out;
2181
2182 data |= IGP01E1000_PSCFR_SMART_SPEED;
2183 ret_val = phy->ops.write_reg(hw,
2195 if (ret_val)
2196 goto out;
2197
2198 data |= IGP01E1000_PSCFR_SMART_SPEED;
2199 ret_val = phy->ops.write_reg(hw,
2184 IGP01E1000_PHY_PORT_CONFIG,
2185 data);
2200 IGP01E1000_PHY_PORT_CONFIG,
2201 data);
2186 if (ret_val)
2187 goto out;
2188 } else if (phy->smart_speed == e1000_smart_speed_off) {
2189 ret_val = phy->ops.read_reg(hw,
2202 if (ret_val)
2203 goto out;
2204 } else if (phy->smart_speed == e1000_smart_speed_off) {
2205 ret_val = phy->ops.read_reg(hw,
2190 IGP01E1000_PHY_PORT_CONFIG,
2191 &data);
2206 IGP01E1000_PHY_PORT_CONFIG,
2207 &data);
2192 if (ret_val)
2193 goto out;
2194
2195 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2196 ret_val = phy->ops.write_reg(hw,
2208 if (ret_val)
2209 goto out;
2210
2211 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2212 ret_val = phy->ops.write_reg(hw,
2197 IGP01E1000_PHY_PORT_CONFIG,
2198 data);
2213 IGP01E1000_PHY_PORT_CONFIG,
2214 data);
2199 if (ret_val)
2200 goto out;
2201 }
2202 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2215 if (ret_val)
2216 goto out;
2217 }
2218 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2203 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2204 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2219 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2220 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2205 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2206 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2207
2208 if (phy->type != e1000_phy_igp_3)
2209 goto out;
2210
2211 /*
2212 * Call gig speed drop workaround on LPLU before accessing
2213 * any PHY registers
2214 */
2215 if (hw->mac.type == e1000_ich8lan)
2216 e1000_gig_downshift_workaround_ich8lan(hw);
2217
2218 /* When LPLU is enabled, we should disable SmartSpeed */
2219 ret_val = phy->ops.read_reg(hw,
2221 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2222 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2223
2224 if (phy->type != e1000_phy_igp_3)
2225 goto out;
2226
2227 /*
2228 * Call gig speed drop workaround on LPLU before accessing
2229 * any PHY registers
2230 */
2231 if (hw->mac.type == e1000_ich8lan)
2232 e1000_gig_downshift_workaround_ich8lan(hw);
2233
2234 /* When LPLU is enabled, we should disable SmartSpeed */
2235 ret_val = phy->ops.read_reg(hw,
2220 IGP01E1000_PHY_PORT_CONFIG,
2221 &data);
2236 IGP01E1000_PHY_PORT_CONFIG,
2237 &data);
2222 if (ret_val)
2223 goto out;
2224
2225 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2226 ret_val = phy->ops.write_reg(hw,
2238 if (ret_val)
2239 goto out;
2240
2241 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2242 ret_val = phy->ops.write_reg(hw,
2227 IGP01E1000_PHY_PORT_CONFIG,
2228 data);
2243 IGP01E1000_PHY_PORT_CONFIG,
2244 data);
2229 }
2230
2231out:
2232 return ret_val;
2233}
2234
2235/**
2236 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1

--- 22 unchanged lines hidden (view full) ---

2259 E1000_EECD_SEC1VAL_VALID_MASK) {
2260 if (eecd & E1000_EECD_SEC1VAL)
2261 *bank = 1;
2262 else
2263 *bank = 0;
2264
2265 goto out;
2266 }
2245 }
2246
2247out:
2248 return ret_val;
2249}
2250
2251/**
2252 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1

--- 22 unchanged lines hidden (view full) ---

2275 E1000_EECD_SEC1VAL_VALID_MASK) {
2276 if (eecd & E1000_EECD_SEC1VAL)
2277 *bank = 1;
2278 else
2279 *bank = 0;
2280
2281 goto out;
2282 }
2267 DEBUGOUT("Unable to determine valid NVM bank via EEC - "
2268 "reading flash signature\n");
2283 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2269 /* fall-thru */
2270 default:
2271 /* set bank to 0 in case flash read fails */
2272 *bank = 0;
2273
2274 /* Check bank 0 */
2275 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2284 /* fall-thru */
2285 default:
2286 /* set bank to 0 in case flash read fails */
2287 *bank = 0;
2288
2289 /* Check bank 0 */
2290 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2276 &sig_byte);
2291 &sig_byte);
2277 if (ret_val)
2278 goto out;
2279 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2280 E1000_ICH_NVM_SIG_VALUE) {
2281 *bank = 0;
2282 goto out;
2283 }
2284
2285 /* Check bank 1 */
2286 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2292 if (ret_val)
2293 goto out;
2294 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2295 E1000_ICH_NVM_SIG_VALUE) {
2296 *bank = 0;
2297 goto out;
2298 }
2299
2300 /* Check bank 1 */
2301 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2287 bank1_offset,
2288 &sig_byte);
2302 bank1_offset,
2303 &sig_byte);
2289 if (ret_val)
2290 goto out;
2291 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2292 E1000_ICH_NVM_SIG_VALUE) {
2293 *bank = 1;
2294 goto out;
2295 }
2296

--- 10 unchanged lines hidden (view full) ---

2307 * @hw: pointer to the HW structure
2308 * @offset: The offset (in bytes) of the word(s) to read.
2309 * @words: Size of data to read in words
2310 * @data: Pointer to the word(s) to read at offset.
2311 *
2312 * Reads a word(s) from the NVM using the flash access registers.
2313 **/
2314static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2304 if (ret_val)
2305 goto out;
2306 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2307 E1000_ICH_NVM_SIG_VALUE) {
2308 *bank = 1;
2309 goto out;
2310 }
2311

--- 10 unchanged lines hidden (view full) ---

2322 * @hw: pointer to the HW structure
2323 * @offset: The offset (in bytes) of the word(s) to read.
2324 * @words: Size of data to read in words
2325 * @data: Pointer to the word(s) to read at offset.
2326 *
2327 * Reads a word(s) from the NVM using the flash access registers.
2328 **/
2329static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2315 u16 *data)
2330 u16 *data)
2316{
2317 struct e1000_nvm_info *nvm = &hw->nvm;
2318 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2319 u32 act_offset;
2320 s32 ret_val = E1000_SUCCESS;
2321 u32 bank = 0;
2322 u16 i, word;
2323

--- 14 unchanged lines hidden (view full) ---

2338 bank = 0;
2339 }
2340
2341 act_offset = (bank) ? nvm->flash_bank_size : 0;
2342 act_offset += offset;
2343
2344 ret_val = E1000_SUCCESS;
2345 for (i = 0; i < words; i++) {
2331{
2332 struct e1000_nvm_info *nvm = &hw->nvm;
2333 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2334 u32 act_offset;
2335 s32 ret_val = E1000_SUCCESS;
2336 u32 bank = 0;
2337 u16 i, word;
2338

--- 14 unchanged lines hidden (view full) ---

2353 bank = 0;
2354 }
2355
2356 act_offset = (bank) ? nvm->flash_bank_size : 0;
2357 act_offset += offset;
2358
2359 ret_val = E1000_SUCCESS;
2360 for (i = 0; i < words; i++) {
2346 if ((dev_spec->shadow_ram) &&
2347 (dev_spec->shadow_ram[offset+i].modified)) {
2361 if (dev_spec->shadow_ram[offset+i].modified) {
2348 data[i] = dev_spec->shadow_ram[offset+i].value;
2349 } else {
2350 ret_val = e1000_read_flash_word_ich8lan(hw,
2362 data[i] = dev_spec->shadow_ram[offset+i].value;
2363 } else {
2364 ret_val = e1000_read_flash_word_ich8lan(hw,
2351 act_offset + i,
2352 &word);
2365 act_offset + i,
2366 &word);
2353 if (ret_val)
2354 break;
2355 data[i] = word;
2356 }
2357 }
2358
2359 nvm->ops.release(hw);
2360

--- 17 unchanged lines hidden (view full) ---

2378 s32 ret_val = -E1000_ERR_NVM;
2379
2380 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
2381
2382 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2383
2384 /* Check if the flash descriptor is valid */
2385 if (hsfsts.hsf_status.fldesvalid == 0) {
2367 if (ret_val)
2368 break;
2369 data[i] = word;
2370 }
2371 }
2372
2373 nvm->ops.release(hw);
2374

--- 17 unchanged lines hidden (view full) ---

2392 s32 ret_val = -E1000_ERR_NVM;
2393
2394 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
2395
2396 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2397
2398 /* Check if the flash descriptor is valid */
2399 if (hsfsts.hsf_status.fldesvalid == 0) {
2386 DEBUGOUT("Flash descriptor invalid. "
2387 "SW Sequencing must be used.");
2400 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
2388 goto out;
2389 }
2390
2391 /* Clear FCERR and DAEL in hw status by writing 1 */
2392 hsfsts.hsf_status.flcerr = 1;
2393 hsfsts.hsf_status.dael = 1;
2394
2395 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);

--- 20 unchanged lines hidden (view full) ---

2416 s32 i;
2417
2418 /*
2419 * Otherwise poll for sometime so the current
2420 * cycle has a chance to end before giving up.
2421 */
2422 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2423 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2401 goto out;
2402 }
2403
2404 /* Clear FCERR and DAEL in hw status by writing 1 */
2405 hsfsts.hsf_status.flcerr = 1;
2406 hsfsts.hsf_status.dael = 1;
2407
2408 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);

--- 20 unchanged lines hidden (view full) ---

2429 s32 i;
2430
2431 /*
2432 * Otherwise poll for sometime so the current
2433 * cycle has a chance to end before giving up.
2434 */
2435 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2436 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2424 ICH_FLASH_HSFSTS);
2437 ICH_FLASH_HSFSTS);
2425 if (hsfsts.hsf_status.flcinprog == 0) {
2426 ret_val = E1000_SUCCESS;
2427 break;
2428 }
2429 usec_delay(1);
2430 }
2431 if (ret_val == E1000_SUCCESS) {
2432 /*
2433 * Successful in waiting for previous cycle to timeout,
2434 * now set the Flash Cycle Done.
2435 */
2436 hsfsts.hsf_status.flcdone = 1;
2437 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
2438 if (hsfsts.hsf_status.flcinprog == 0) {
2439 ret_val = E1000_SUCCESS;
2440 break;
2441 }
2442 usec_delay(1);
2443 }
2444 if (ret_val == E1000_SUCCESS) {
2445 /*
2446 * Successful in waiting for previous cycle to timeout,
2447 * now set the Flash Cycle Done.
2448 */
2449 hsfsts.hsf_status.flcdone = 1;
2450 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
2438 hsfsts.regval);
2451 hsfsts.regval);
2439 } else {
2452 } else {
2440 DEBUGOUT("Flash controller busy, cannot get access");
2453 DEBUGOUT("Flash controller busy, cannot get access\n");
2441 }
2442 }
2443
2444out:
2445 return ret_val;
2446}
2447
2448/**

--- 36 unchanged lines hidden (view full) ---

2485 * @hw: pointer to the HW structure
2486 * @offset: offset to data location
2487 * @data: pointer to the location for storing the data
2488 *
2489 * Reads the flash word at offset into data. Offset is converted
2490 * to bytes before read.
2491 **/
2492static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2454 }
2455 }
2456
2457out:
2458 return ret_val;
2459}
2460
2461/**

--- 36 unchanged lines hidden (view full) ---

2498 * @hw: pointer to the HW structure
2499 * @offset: offset to data location
2500 * @data: pointer to the location for storing the data
2501 *
2502 * Reads the flash word at offset into data. Offset is converted
2503 * to bytes before read.
2504 **/
2505static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2493 u16 *data)
2506 u16 *data)
2494{
2495 s32 ret_val;
2496
2497 DEBUGFUNC("e1000_read_flash_word_ich8lan");
2498
2499 if (!data) {
2500 ret_val = -E1000_ERR_NVM;
2501 goto out;

--- 12 unchanged lines hidden (view full) ---

2514 * e1000_read_flash_byte_ich8lan - Read byte from flash
2515 * @hw: pointer to the HW structure
2516 * @offset: The offset of the byte to read.
2517 * @data: Pointer to a byte to store the value read.
2518 *
2519 * Reads a single byte from the NVM using the flash access registers.
2520 **/
2521static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2507{
2508 s32 ret_val;
2509
2510 DEBUGFUNC("e1000_read_flash_word_ich8lan");
2511
2512 if (!data) {
2513 ret_val = -E1000_ERR_NVM;
2514 goto out;

--- 12 unchanged lines hidden (view full) ---

2527 * e1000_read_flash_byte_ich8lan - Read byte from flash
2528 * @hw: pointer to the HW structure
2529 * @offset: The offset of the byte to read.
2530 * @data: Pointer to a byte to store the value read.
2531 *
2532 * Reads a single byte from the NVM using the flash access registers.
2533 **/
2534static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2522 u8 *data)
2535 u8 *data)
2523{
2524 s32 ret_val = E1000_SUCCESS;
2525 u16 word = 0;
2526
2527 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2528 if (ret_val)
2529 goto out;
2530

--- 8 unchanged lines hidden (view full) ---

2539 * @hw: pointer to the HW structure
2540 * @offset: The offset (in bytes) of the byte or word to read.
2541 * @size: Size of data to read, 1=byte 2=word
2542 * @data: Pointer to the word to store the value read.
2543 *
2544 * Reads a byte or word from the NVM using the flash access registers.
2545 **/
2546static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2536{
2537 s32 ret_val = E1000_SUCCESS;
2538 u16 word = 0;
2539
2540 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2541 if (ret_val)
2542 goto out;
2543

--- 8 unchanged lines hidden (view full) ---

2552 * @hw: pointer to the HW structure
2553 * @offset: The offset (in bytes) of the byte or word to read.
2554 * @size: Size of data to read, 1=byte 2=word
2555 * @data: Pointer to the word to store the value read.
2556 *
2557 * Reads a byte or word from the NVM using the flash access registers.
2558 **/
2559static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2547 u8 size, u16 *data)
2560 u8 size, u16 *data)
2548{
2549 union ich8_hws_flash_status hsfsts;
2550 union ich8_hws_flash_ctrl hsflctl;
2551 u32 flash_linear_addr;
2552 u32 flash_data = 0;
2553 s32 ret_val = -E1000_ERR_NVM;
2554 u8 count = 0;
2555
2556 DEBUGFUNC("e1000_read_flash_data_ich8lan");
2557
2558 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2559 goto out;
2560
2561 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2561{
2562 union ich8_hws_flash_status hsfsts;
2563 union ich8_hws_flash_ctrl hsflctl;
2564 u32 flash_linear_addr;
2565 u32 flash_data = 0;
2566 s32 ret_val = -E1000_ERR_NVM;
2567 u8 count = 0;
2568
2569 DEBUGFUNC("e1000_read_flash_data_ich8lan");
2570
2571 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2572 goto out;
2573
2574 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2562 hw->nvm.flash_base_addr;
2575 hw->nvm.flash_base_addr;
2563
2564 do {
2565 usec_delay(1);
2566 /* Steps */
2567 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2568 if (ret_val != E1000_SUCCESS)
2569 break;
2570
2571 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2572 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2573 hsflctl.hsf_ctrl.fldbcount = size - 1;
2574 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2575 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2576
2577 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
2578
2579 ret_val = e1000_flash_cycle_ich8lan(hw,
2576
2577 do {
2578 usec_delay(1);
2579 /* Steps */
2580 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2581 if (ret_val != E1000_SUCCESS)
2582 break;
2583
2584 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2585 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2586 hsflctl.hsf_ctrl.fldbcount = size - 1;
2587 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2588 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2589
2590 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
2591
2592 ret_val = e1000_flash_cycle_ich8lan(hw,
2580 ICH_FLASH_READ_COMMAND_TIMEOUT);
2593 ICH_FLASH_READ_COMMAND_TIMEOUT);
2581
2582 /*
2583 * Check if FCERR is set to 1, if set to 1, clear it
2584 * and try the whole sequence a few more times, else
2585 * read in (shift in) the Flash Data0, the order is
2586 * least significant byte first msb to lsb
2587 */
2588 if (ret_val == E1000_SUCCESS) {

--- 6 unchanged lines hidden (view full) ---

2595 } else {
2596 /*
2597 * If we've gotten here, then things are probably
2598 * completely hosed, but if the error condition is
2599 * detected, it won't hurt to give it another try...
2600 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2601 */
2602 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2594
2595 /*
2596 * Check if FCERR is set to 1, if set to 1, clear it
2597 * and try the whole sequence a few more times, else
2598 * read in (shift in) the Flash Data0, the order is
2599 * least significant byte first msb to lsb
2600 */
2601 if (ret_val == E1000_SUCCESS) {

--- 6 unchanged lines hidden (view full) ---

2608 } else {
2609 /*
2610 * If we've gotten here, then things are probably
2611 * completely hosed, but if the error condition is
2612 * detected, it won't hurt to give it another try...
2613 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2614 */
2615 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2603 ICH_FLASH_HSFSTS);
2616 ICH_FLASH_HSFSTS);
2604 if (hsfsts.hsf_status.flcerr == 1) {
2605 /* Repeat for some time before giving up. */
2606 continue;
2607 } else if (hsfsts.hsf_status.flcdone == 0) {
2617 if (hsfsts.hsf_status.flcerr == 1) {
2618 /* Repeat for some time before giving up. */
2619 continue;
2620 } else if (hsfsts.hsf_status.flcdone == 0) {
2608 DEBUGOUT("Timeout error - flash cycle "
2609 "did not complete.");
2621 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
2610 break;
2611 }
2612 }
2613 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2614
2615out:
2616 return ret_val;
2617}
2618
2619/**
2620 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2621 * @hw: pointer to the HW structure
2622 * @offset: The offset (in bytes) of the word(s) to write.
2623 * @words: Size of data to write in words
2624 * @data: Pointer to the word(s) to write at offset.
2625 *
2626 * Writes a byte or word to the NVM using the flash access registers.
2627 **/
2628static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2622 break;
2623 }
2624 }
2625 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2626
2627out:
2628 return ret_val;
2629}
2630
2631/**
2632 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2633 * @hw: pointer to the HW structure
2634 * @offset: The offset (in bytes) of the word(s) to write.
2635 * @words: Size of data to write in words
2636 * @data: Pointer to the word(s) to write at offset.
2637 *
2638 * Writes a byte or word to the NVM using the flash access registers.
2639 **/
2640static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2629 u16 *data)
2641 u16 *data)
2630{
2631 struct e1000_nvm_info *nvm = &hw->nvm;
2632 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2633 s32 ret_val = E1000_SUCCESS;
2634 u16 i;
2635
2636 DEBUGFUNC("e1000_write_nvm_ich8lan");
2637

--- 77 unchanged lines hidden (view full) ---

2715 * Determine whether to write the value stored
2716 * in the other NVM bank or a modified value stored
2717 * in the shadow RAM
2718 */
2719 if (dev_spec->shadow_ram[i].modified) {
2720 data = dev_spec->shadow_ram[i].value;
2721 } else {
2722 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2642{
2643 struct e1000_nvm_info *nvm = &hw->nvm;
2644 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2645 s32 ret_val = E1000_SUCCESS;
2646 u16 i;
2647
2648 DEBUGFUNC("e1000_write_nvm_ich8lan");
2649

--- 77 unchanged lines hidden (view full) ---

2727 * Determine whether to write the value stored
2728 * in the other NVM bank or a modified value stored
2729 * in the shadow RAM
2730 */
2731 if (dev_spec->shadow_ram[i].modified) {
2732 data = dev_spec->shadow_ram[i].value;
2733 } else {
2734 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2723 old_bank_offset,
2724 &data);
2735 old_bank_offset,
2736 &data);
2725 if (ret_val)
2726 break;
2727 }
2728
2729 /*
2730 * If the word is 0x13, then make sure the signature bits
2731 * (15:14) are 11b until the commit has completed.
2732 * This will allow us to write 10b which indicates the

--- 5 unchanged lines hidden (view full) ---

2738 data |= E1000_ICH_NVM_SIG_MASK;
2739
2740 /* Convert offset to bytes. */
2741 act_offset = (i + new_bank_offset) << 1;
2742
2743 usec_delay(100);
2744 /* Write the bytes to the new bank. */
2745 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2737 if (ret_val)
2738 break;
2739 }
2740
2741 /*
2742 * If the word is 0x13, then make sure the signature bits
2743 * (15:14) are 11b until the commit has completed.
2744 * This will allow us to write 10b which indicates the

--- 5 unchanged lines hidden (view full) ---

2750 data |= E1000_ICH_NVM_SIG_MASK;
2751
2752 /* Convert offset to bytes. */
2753 act_offset = (i + new_bank_offset) << 1;
2754
2755 usec_delay(100);
2756 /* Write the bytes to the new bank. */
2757 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2746 act_offset,
2747 (u8)data);
2758 act_offset,
2759 (u8)data);
2748 if (ret_val)
2749 break;
2750
2751 usec_delay(100);
2752 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2760 if (ret_val)
2761 break;
2762
2763 usec_delay(100);
2764 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2753 act_offset + 1,
2754 (u8)(data >> 8));
2765 act_offset + 1,
2766 (u8)(data >> 8));
2755 if (ret_val)
2756 break;
2757 }
2758
2759 /*
2760 * Don't bother writing the segment valid bits if sector
2761 * programming failed.
2762 */

--- 10 unchanged lines hidden (view full) ---

2773 */
2774 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2775 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2776 if (ret_val)
2777 goto release;
2778
2779 data &= 0xBFFF;
2780 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2767 if (ret_val)
2768 break;
2769 }
2770
2771 /*
2772 * Don't bother writing the segment valid bits if sector
2773 * programming failed.
2774 */

--- 10 unchanged lines hidden (view full) ---

2785 */
2786 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2787 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2788 if (ret_val)
2789 goto release;
2790
2791 data &= 0xBFFF;
2792 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2781 act_offset * 2 + 1,
2782 (u8)(data >> 8));
2793 act_offset * 2 + 1,
2794 (u8)(data >> 8));
2783 if (ret_val)
2784 goto release;
2785
2786 /*
2787 * And invalidate the previously valid segment by setting
2788 * its signature word (0x13) high_byte to 0b. This can be
2789 * done without an erase because flash erase sets all bits
2790 * to 1's. We can write 1's to 0's without an erase

--- 74 unchanged lines hidden (view full) ---

2865 * @hw: pointer to the HW structure
2866 * @offset: The offset (in bytes) of the byte/word to read.
2867 * @size: Size of data to read, 1=byte 2=word
2868 * @data: The byte(s) to write to the NVM.
2869 *
2870 * Writes one/two bytes to the NVM using the flash access registers.
2871 **/
2872static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2795 if (ret_val)
2796 goto release;
2797
2798 /*
2799 * And invalidate the previously valid segment by setting
2800 * its signature word (0x13) high_byte to 0b. This can be
2801 * done without an erase because flash erase sets all bits
2802 * to 1's. We can write 1's to 0's without an erase

--- 74 unchanged lines hidden (view full) ---

2877 * @hw: pointer to the HW structure
2878 * @offset: The offset (in bytes) of the byte/word to read.
2879 * @size: Size of data to read, 1=byte 2=word
2880 * @data: The byte(s) to write to the NVM.
2881 *
2882 * Writes one/two bytes to the NVM using the flash access registers.
2883 **/
2884static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2873 u8 size, u16 data)
2885 u8 size, u16 data)
2874{
2875 union ich8_hws_flash_status hsfsts;
2876 union ich8_hws_flash_ctrl hsflctl;
2877 u32 flash_linear_addr;
2878 u32 flash_data = 0;
2879 s32 ret_val = -E1000_ERR_NVM;
2880 u8 count = 0;
2881
2882 DEBUGFUNC("e1000_write_ich8_data");
2883
2884 if (size < 1 || size > 2 || data > size * 0xff ||
2885 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2886 goto out;
2887
2888 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2886{
2887 union ich8_hws_flash_status hsfsts;
2888 union ich8_hws_flash_ctrl hsflctl;
2889 u32 flash_linear_addr;
2890 u32 flash_data = 0;
2891 s32 ret_val = -E1000_ERR_NVM;
2892 u8 count = 0;
2893
2894 DEBUGFUNC("e1000_write_ich8_data");
2895
2896 if (size < 1 || size > 2 || data > size * 0xff ||
2897 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2898 goto out;
2899
2900 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2889 hw->nvm.flash_base_addr;
2901 hw->nvm.flash_base_addr;
2890
2891 do {
2892 usec_delay(1);
2893 /* Steps */
2894 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2895 if (ret_val != E1000_SUCCESS)
2896 break;
2897

--- 12 unchanged lines hidden (view full) ---

2910
2911 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
2912
2913 /*
2914 * check if FCERR is set to 1 , if set to 1, clear it
2915 * and try the whole sequence a few more times else done
2916 */
2917 ret_val = e1000_flash_cycle_ich8lan(hw,
2902
2903 do {
2904 usec_delay(1);
2905 /* Steps */
2906 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2907 if (ret_val != E1000_SUCCESS)
2908 break;
2909

--- 12 unchanged lines hidden (view full) ---

2922
2923 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
2924
2925 /*
2926 * check if FCERR is set to 1 , if set to 1, clear it
2927 * and try the whole sequence a few more times else done
2928 */
2929 ret_val = e1000_flash_cycle_ich8lan(hw,
2918 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2930 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2919 if (ret_val == E1000_SUCCESS)
2920 break;
2921
2922 /*
2923 * If we're here, then things are most likely
2924 * completely hosed, but if the error condition
2925 * is detected, it won't hurt to give it another
2926 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2927 */
2928 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2929 if (hsfsts.hsf_status.flcerr == 1)
2930 /* Repeat for some time before giving up. */
2931 continue;
2932 if (hsfsts.hsf_status.flcdone == 0) {
2931 if (ret_val == E1000_SUCCESS)
2932 break;
2933
2934 /*
2935 * If we're here, then things are most likely
2936 * completely hosed, but if the error condition
2937 * is detected, it won't hurt to give it another
2938 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2939 */
2940 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2941 if (hsfsts.hsf_status.flcerr == 1)
2942 /* Repeat for some time before giving up. */
2943 continue;
2944 if (hsfsts.hsf_status.flcdone == 0) {
2933 DEBUGOUT("Timeout error - flash cycle "
2934 "did not complete.");
2945 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
2935 break;
2936 }
2937 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2938
2939out:
2940 return ret_val;
2941}
2942
2943/**
2944 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2945 * @hw: pointer to the HW structure
2946 * @offset: The index of the byte to read.
2947 * @data: The byte to write to the NVM.
2948 *
2949 * Writes a single byte to the NVM using the flash access registers.
2950 **/
2951static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2946 break;
2947 }
2948 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2949
2950out:
2951 return ret_val;
2952}
2953
2954/**
2955 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2956 * @hw: pointer to the HW structure
2957 * @offset: The index of the byte to read.
2958 * @data: The byte to write to the NVM.
2959 *
2960 * Writes a single byte to the NVM using the flash access registers.
2961 **/
2962static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2952 u8 data)
2963 u8 data)
2953{
2954 u16 word = (u16)data;
2955
2956 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
2957
2958 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2959}
2960
2961/**
2962 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2963 * @hw: pointer to the HW structure
2964 * @offset: The offset of the byte to write.
2965 * @byte: The byte to write to the NVM.
2966 *
2967 * Writes a single byte to the NVM using the flash access registers.
2968 * Goes through a retry algorithm before giving up.
2969 **/
2970static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2964{
2965 u16 word = (u16)data;
2966
2967 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
2968
2969 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2970}
2971
2972/**
2973 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2974 * @hw: pointer to the HW structure
2975 * @offset: The offset of the byte to write.
2976 * @byte: The byte to write to the NVM.
2977 *
2978 * Writes a single byte to the NVM using the flash access registers.
2979 * Goes through a retry algorithm before giving up.
2980 **/
2981static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2971 u32 offset, u8 byte)
2982 u32 offset, u8 byte)
2972{
2973 s32 ret_val;
2974 u16 program_retries;
2975
2976 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
2977
2978 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2979 if (ret_val == E1000_SUCCESS)

--- 86 unchanged lines hidden (view full) ---

3066 if (ret_val)
3067 goto out;
3068
3069 /*
3070 * Write a value 11 (block Erase) in Flash
3071 * Cycle field in hw flash control
3072 */
3073 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
2983{
2984 s32 ret_val;
2985 u16 program_retries;
2986
2987 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
2988
2989 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2990 if (ret_val == E1000_SUCCESS)

--- 86 unchanged lines hidden (view full) ---

3077 if (ret_val)
3078 goto out;
3079
3080 /*
3081 * Write a value 11 (block Erase) in Flash
3082 * Cycle field in hw flash control
3083 */
3084 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
3074 ICH_FLASH_HSFCTL);
3085 ICH_FLASH_HSFCTL);
3075 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3076 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3086 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3087 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3077 hsflctl.regval);
3088 hsflctl.regval);
3078
3079 /*
3080 * Write the last 24 bits of an index within the
3081 * block into Flash Linear address field in Flash
3082 * Address.
3083 */
3084 flash_linear_addr += (j * sector_size);
3085 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3089
3090 /*
3091 * Write the last 24 bits of an index within the
3092 * block into Flash Linear address field in Flash
3093 * Address.
3094 */
3095 flash_linear_addr += (j * sector_size);
3096 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3086 flash_linear_addr);
3097 flash_linear_addr);
3087
3088 ret_val = e1000_flash_cycle_ich8lan(hw,
3098
3099 ret_val = e1000_flash_cycle_ich8lan(hw,
3089 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3100 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3090 if (ret_val == E1000_SUCCESS)
3091 break;
3092
3093 /*
3094 * Check if FCERR is set to 1. If 1,
3095 * clear it and try the whole sequence
3096 * a few more times else Done
3097 */

--- 27 unchanged lines hidden (view full) ---

3125 DEBUGFUNC("e1000_valid_led_default_ich8lan");
3126
3127 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3128 if (ret_val) {
3129 DEBUGOUT("NVM Read Error\n");
3130 goto out;
3131 }
3132
3101 if (ret_val == E1000_SUCCESS)
3102 break;
3103
3104 /*
3105 * Check if FCERR is set to 1. If 1,
3106 * clear it and try the whole sequence
3107 * a few more times else Done
3108 */

--- 27 unchanged lines hidden (view full) ---

3136 DEBUGFUNC("e1000_valid_led_default_ich8lan");
3137
3138 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3139 if (ret_val) {
3140 DEBUGOUT("NVM Read Error\n");
3141 goto out;
3142 }
3143
3133 if (*data == ID_LED_RESERVED_0000 ||
3134 *data == ID_LED_RESERVED_FFFF)
3144 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3135 *data = ID_LED_DEFAULT_ICH8LAN;
3136
3137out:
3138 return ret_val;
3139}
3140
3141/**
3142 * e1000_id_led_init_pchlan - store LED configurations

--- 70 unchanged lines hidden (view full) ---

3213 return ret_val;
3214}
3215
3216/**
3217 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3218 * @hw: pointer to the HW structure
3219 *
3220 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3145 *data = ID_LED_DEFAULT_ICH8LAN;
3146
3147out:
3148 return ret_val;
3149}
3150
3151/**
3152 * e1000_id_led_init_pchlan - store LED configurations

--- 70 unchanged lines hidden (view full) ---

3223 return ret_val;
3224}
3225
3226/**
3227 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3228 * @hw: pointer to the HW structure
3229 *
3230 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3221 * register, so the bus width is hard coded.
3231 * register, so the the bus width is hard coded.
3222 **/
3223static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3224{
3225 struct e1000_bus_info *bus = &hw->bus;
3226 s32 ret_val;
3227
3228 DEBUGFUNC("e1000_get_bus_info_ich8lan");
3229

--- 85 unchanged lines hidden (view full) ---

3315 */
3316 if ((hw->mac.type == e1000_pch2lan) &&
3317 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3318 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3319 }
3320 ret_val = e1000_acquire_swflag_ich8lan(hw);
3321 DEBUGOUT("Issuing a global reset to ich8lan\n");
3322 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
3232 **/
3233static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3234{
3235 struct e1000_bus_info *bus = &hw->bus;
3236 s32 ret_val;
3237
3238 DEBUGFUNC("e1000_get_bus_info_ich8lan");
3239

--- 85 unchanged lines hidden (view full) ---

3325 */
3326 if ((hw->mac.type == e1000_pch2lan) &&
3327 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3328 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3329 }
3330 ret_val = e1000_acquire_swflag_ich8lan(hw);
3331 DEBUGOUT("Issuing a global reset to ich8lan\n");
3332 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
3333 /* cannot issue a flush here because it hangs the hardware */
3323 msec_delay(20);
3324
3325 if (!ret_val)
3334 msec_delay(20);
3335
3336 if (!ret_val)
3326 e1000_release_swflag_ich8lan(hw);
3337 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
3327
3328 if (ctrl & E1000_CTRL_PHY_RST) {
3329 ret_val = hw->phy.ops.get_cfg_done(hw);
3330 if (ret_val)
3331 goto out;
3332
3333 ret_val = e1000_post_phy_reset_ich8lan(hw);
3334 if (ret_val)

--- 53 unchanged lines hidden (view full) ---

3388
3389 /* Zero out the Multicast HASH table */
3390 DEBUGOUT("Zeroing the MTA\n");
3391 for (i = 0; i < mac->mta_reg_count; i++)
3392 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3393
3394 /*
3395 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3338
3339 if (ctrl & E1000_CTRL_PHY_RST) {
3340 ret_val = hw->phy.ops.get_cfg_done(hw);
3341 if (ret_val)
3342 goto out;
3343
3344 ret_val = e1000_post_phy_reset_ich8lan(hw);
3345 if (ret_val)

--- 53 unchanged lines hidden (view full) ---

3399
3400 /* Zero out the Multicast HASH table */
3401 DEBUGOUT("Zeroing the MTA\n");
3402 for (i = 0; i < mac->mta_reg_count; i++)
3403 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3404
3405 /*
3406 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3396 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3407 * the ME. Disable wakeup by clearing the host wakeup bit.
3397 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3398 */
3399 if (hw->phy.type == e1000_phy_82578) {
3408 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3409 */
3410 if (hw->phy.type == e1000_phy_82578) {
3400 hw->phy.ops.read_reg(hw, BM_WUC, &i);
3411 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
3412 i &= ~BM_WUC_HOST_WU_BIT;
3413 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
3401 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3402 if (ret_val)
3403 return ret_val;
3404 }
3405
3406 /* Setup link and flow control */
3407 ret_val = mac->ops.setup_link(hw);
3408
3409 /* Set the transmit descriptor write-back policy for both queues */
3410 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
3411 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3412 E1000_TXDCTL_FULL_TX_DESC_WB;
3413 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3414 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3415 if (ret_val)
3416 return ret_val;
3417 }
3418
3419 /* Setup link and flow control */
3420 ret_val = mac->ops.setup_link(hw);
3421
3422 /* Set the transmit descriptor write-back policy for both queues */
3423 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
3424 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3425 E1000_TXDCTL_FULL_TX_DESC_WB;
3426 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3414 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3427 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3415 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
3416 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
3417 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3418 E1000_TXDCTL_FULL_TX_DESC_WB;
3419 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3428 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
3429 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
3430 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3431 E1000_TXDCTL_FULL_TX_DESC_WB;
3432 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3420 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3433 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3421 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
3422
3423 /*
3424 * ICH8 has opposite polarity of no_snoop bits.
3425 * By default, we should use snoop behavior.
3426 */
3427 if (mac->type == e1000_ich8lan)
3428 snoop = PCIE_ICH8_SNOOP_ALL;

--- 123 unchanged lines hidden (view full) ---

3552
3553 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
3554 if ((hw->phy.type == e1000_phy_82578) ||
3555 (hw->phy.type == e1000_phy_82579) ||
3556 (hw->phy.type == e1000_phy_82577)) {
3557 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
3558
3559 ret_val = hw->phy.ops.write_reg(hw,
3434 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
3435
3436 /*
3437 * ICH8 has opposite polarity of no_snoop bits.
3438 * By default, we should use snoop behavior.
3439 */
3440 if (mac->type == e1000_ich8lan)
3441 snoop = PCIE_ICH8_SNOOP_ALL;

--- 123 unchanged lines hidden (view full) ---

3565
3566 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
3567 if ((hw->phy.type == e1000_phy_82578) ||
3568 (hw->phy.type == e1000_phy_82579) ||
3569 (hw->phy.type == e1000_phy_82577)) {
3570 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
3571
3572 ret_val = hw->phy.ops.write_reg(hw,
3560 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3561 hw->fc.pause_time);
3573 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3574 hw->fc.pause_time);
3562 if (ret_val)
3563 goto out;
3564 }
3565
3566 ret_val = e1000_set_fc_watermarks_generic(hw);
3567
3568out:
3569 return ret_val;

--- 21 unchanged lines hidden (view full) ---

3591 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3592
3593 /*
3594 * Set the mac to wait the maximum time between each iteration
3595 * and increase the max iterations when polling the phy;
3596 * this fixes erroneous timeouts at 10Mbps.
3597 */
3598 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
3575 if (ret_val)
3576 goto out;
3577 }
3578
3579 ret_val = e1000_set_fc_watermarks_generic(hw);
3580
3581out:
3582 return ret_val;

--- 21 unchanged lines hidden (view full) ---

3604 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3605
3606 /*
3607 * Set the mac to wait the maximum time between each iteration
3608 * and increase the max iterations when polling the phy;
3609 * this fixes erroneous timeouts at 10Mbps.
3610 */
3611 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
3599 0xFFFF);
3612 0xFFFF);
3600 if (ret_val)
3601 goto out;
3602 ret_val = e1000_read_kmrn_reg_generic(hw,
3613 if (ret_val)
3614 goto out;
3615 ret_val = e1000_read_kmrn_reg_generic(hw,
3603 E1000_KMRNCTRLSTA_INBAND_PARAM,
3604 &reg_data);
3616 E1000_KMRNCTRLSTA_INBAND_PARAM,
3617 &reg_data);
3605 if (ret_val)
3606 goto out;
3607 reg_data |= 0x3F;
3608 ret_val = e1000_write_kmrn_reg_generic(hw,
3618 if (ret_val)
3619 goto out;
3620 reg_data |= 0x3F;
3621 ret_val = e1000_write_kmrn_reg_generic(hw,
3609 E1000_KMRNCTRLSTA_INBAND_PARAM,
3610 reg_data);
3622 E1000_KMRNCTRLSTA_INBAND_PARAM,
3623 reg_data);
3611 if (ret_val)
3612 goto out;
3613
3614 switch (hw->phy.type) {
3615 case e1000_phy_igp_3:
3616 ret_val = e1000_copper_link_setup_igp(hw);
3617 if (ret_val)
3618 goto out;

--- 7 unchanged lines hidden (view full) ---

3626 case e1000_phy_82577:
3627 case e1000_phy_82579:
3628 ret_val = e1000_copper_link_setup_82577(hw);
3629 if (ret_val)
3630 goto out;
3631 break;
3632 case e1000_phy_ife:
3633 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3624 if (ret_val)
3625 goto out;
3626
3627 switch (hw->phy.type) {
3628 case e1000_phy_igp_3:
3629 ret_val = e1000_copper_link_setup_igp(hw);
3630 if (ret_val)
3631 goto out;

--- 7 unchanged lines hidden (view full) ---

3639 case e1000_phy_82577:
3640 case e1000_phy_82579:
3641 ret_val = e1000_copper_link_setup_82577(hw);
3642 if (ret_val)
3643 goto out;
3644 break;
3645 case e1000_phy_ife:
3646 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3634 &reg_data);
3647 &reg_data);
3635 if (ret_val)
3636 goto out;
3637
3638 reg_data &= ~IFE_PMC_AUTO_MDIX;
3639
3640 switch (hw->phy.mdix) {
3641 case 1:
3642 reg_data &= ~IFE_PMC_FORCE_MDIX;
3643 break;
3644 case 2:
3645 reg_data |= IFE_PMC_FORCE_MDIX;
3646 break;
3647 case 0:
3648 default:
3649 reg_data |= IFE_PMC_AUTO_MDIX;
3650 break;
3651 }
3652 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3648 if (ret_val)
3649 goto out;
3650
3651 reg_data &= ~IFE_PMC_AUTO_MDIX;
3652
3653 switch (hw->phy.mdix) {
3654 case 1:
3655 reg_data &= ~IFE_PMC_FORCE_MDIX;
3656 break;
3657 case 2:
3658 reg_data |= IFE_PMC_FORCE_MDIX;
3659 break;
3660 case 0:
3661 default:
3662 reg_data |= IFE_PMC_AUTO_MDIX;
3663 break;
3664 }
3665 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3653 reg_data);
3666 reg_data);
3654 if (ret_val)
3655 goto out;
3656 break;
3657 default:
3658 break;
3659 }
3660 ret_val = e1000_setup_copper_link_generic(hw);
3661

--- 7 unchanged lines hidden (view full) ---

3669 * @speed: pointer to store current link speed
3670 * @duplex: pointer to store the current link duplex
3671 *
3672 * Calls the generic get_speed_and_duplex to retrieve the current link
3673 * information and then calls the Kumeran lock loss workaround for links at
3674 * gigabit speeds.
3675 **/
3676static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3667 if (ret_val)
3668 goto out;
3669 break;
3670 default:
3671 break;
3672 }
3673 ret_val = e1000_setup_copper_link_generic(hw);
3674

--- 7 unchanged lines hidden (view full) ---

3682 * @speed: pointer to store current link speed
3683 * @duplex: pointer to store the current link duplex
3684 *
3685 * Calls the generic get_speed_and_duplex to retrieve the current link
3686 * information and then calls the Kumeran lock loss workaround for links at
3687 * gigabit speeds.
3688 **/
3689static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3677 u16 *duplex)
3690 u16 *duplex)
3678{
3679 s32 ret_val;
3680
3681 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
3682
3683 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
3684 if (ret_val)
3685 goto out;

--- 65 unchanged lines hidden (view full) ---

3751
3752 /* Issue PHY reset */
3753 hw->phy.ops.reset(hw);
3754 msec_delay_irq(5);
3755 }
3756 /* Disable GigE link negotiation */
3757 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3758 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3691{
3692 s32 ret_val;
3693
3694 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
3695
3696 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
3697 if (ret_val)
3698 goto out;

--- 65 unchanged lines hidden (view full) ---

3764
3765 /* Issue PHY reset */
3766 hw->phy.ops.reset(hw);
3767 msec_delay_irq(5);
3768 }
3769 /* Disable GigE link negotiation */
3770 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3771 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3759 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3772 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3760 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3761
3762 /*
3763 * Call gig speed drop workaround on Gig disable before accessing
3764 * any PHY registers
3765 */
3766 e1000_gig_downshift_workaround_ich8lan(hw);
3767

--- 8 unchanged lines hidden (view full) ---

3776 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3777 * @hw: pointer to the HW structure
3778 * @state: boolean value used to set the current Kumeran workaround state
3779 *
3780 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
3781 * /disabled - FALSE).
3782 **/
3783void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3773 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3774
3775 /*
3776 * Call gig speed drop workaround on Gig disable before accessing
3777 * any PHY registers
3778 */
3779 e1000_gig_downshift_workaround_ich8lan(hw);
3780

--- 8 unchanged lines hidden (view full) ---

3789 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3790 * @hw: pointer to the HW structure
3791 * @state: boolean value used to set the current Kumeran workaround state
3792 *
3793 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
3794 * /disabled - FALSE).
3795 **/
3796void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3784 bool state)
3797 bool state)
3785{
3786 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3787
3788 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
3789
3790 if (hw->mac.type != e1000_ich8lan) {
3791 DEBUGOUT("Workaround applies to ICH8 only.\n");
3792 return;

--- 25 unchanged lines hidden (view full) ---

3818 if (hw->phy.type != e1000_phy_igp_3)
3819 goto out;
3820
3821 /* Try the workaround twice (if needed) */
3822 do {
3823 /* Disable link */
3824 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
3825 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3798{
3799 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3800
3801 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
3802
3803 if (hw->mac.type != e1000_ich8lan) {
3804 DEBUGOUT("Workaround applies to ICH8 only.\n");
3805 return;

--- 25 unchanged lines hidden (view full) ---

3831 if (hw->phy.type != e1000_phy_igp_3)
3832 goto out;
3833
3834 /* Try the workaround twice (if needed) */
3835 do {
3836 /* Disable link */
3837 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
3838 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3826 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3839 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3827 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
3828
3829 /*
3830 * Call gig speed drop workaround on Gig disable before
3831 * accessing any PHY registers
3832 */
3833 if (hw->mac.type == e1000_ich8lan)
3834 e1000_gig_downshift_workaround_ich8lan(hw);
3835
3836 /* Write VR power-down enable */
3837 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3838 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3839 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
3840 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
3841
3842 /*
3843 * Call gig speed drop workaround on Gig disable before
3844 * accessing any PHY registers
3845 */
3846 if (hw->mac.type == e1000_ich8lan)
3847 e1000_gig_downshift_workaround_ich8lan(hw);
3848
3849 /* Write VR power-down enable */
3850 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3851 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3852 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
3840 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3853 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3841
3842 /* Read it back and test */
3843 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3844 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3845 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3846 break;
3847
3848 /* Issue PHY reset and repeat at most one more time */

--- 9 unchanged lines hidden (view full) ---

3858/**
3859 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3860 * @hw: pointer to the HW structure
3861 *
3862 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3863 * LPLU, Gig disable, MDIC PHY reset):
3864 * 1) Set Kumeran Near-end loopback
3865 * 2) Clear Kumeran Near-end loopback
3854
3855 /* Read it back and test */
3856 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3857 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3858 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3859 break;
3860
3861 /* Issue PHY reset and repeat at most one more time */

--- 9 unchanged lines hidden (view full) ---

3871/**
3872 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3873 * @hw: pointer to the HW structure
3874 *
3875 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3876 * LPLU, Gig disable, MDIC PHY reset):
3877 * 1) Set Kumeran Near-end loopback
3878 * 2) Clear Kumeran Near-end loopback
3866 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3879 * Should only be called for ICH8[m] devices with any 1G Phy.
3867 **/
3868void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3869{
3870 s32 ret_val = E1000_SUCCESS;
3871 u16 reg_data;
3872
3873 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
3874
3875 if ((hw->mac.type != e1000_ich8lan) ||
3880 **/
3881void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3882{
3883 s32 ret_val = E1000_SUCCESS;
3884 u16 reg_data;
3885
3886 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
3887
3888 if ((hw->mac.type != e1000_ich8lan) ||
3876 (hw->phy.type != e1000_phy_igp_3))
3889 (hw->phy.type == e1000_phy_ife))
3877 goto out;
3878
3879 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3890 goto out;
3891
3892 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3880 &reg_data);
3893 &reg_data);
3881 if (ret_val)
3882 goto out;
3883 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3884 ret_val = e1000_write_kmrn_reg_generic(hw,
3894 if (ret_val)
3895 goto out;
3896 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3897 ret_val = e1000_write_kmrn_reg_generic(hw,
3885 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3886 reg_data);
3898 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3899 reg_data);
3887 if (ret_val)
3888 goto out;
3889 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3890 ret_val = e1000_write_kmrn_reg_generic(hw,
3900 if (ret_val)
3901 goto out;
3902 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3903 ret_val = e1000_write_kmrn_reg_generic(hw,
3891 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3892 reg_data);
3904 E1000_KMRNCTRLSTA_DIAG_OFFSET,
3905 reg_data);
3893out:
3894 return;
3895}
3896
3897/**
3906out:
3907 return;
3908}
3909
3910/**
3898 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
3911 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3899 * @hw: pointer to the HW structure
3900 *
3901 * During S0 to Sx transition, it is possible the link remains at gig
3902 * instead of negotiating to a lower speed. Before going to Sx, set
3912 * @hw: pointer to the HW structure
3913 *
3914 * During S0 to Sx transition, it is possible the link remains at gig
3915 * instead of negotiating to a lower speed. Before going to Sx, set
3903 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3904 * to a lower speed.
3905 *
3906 * Should only be called for applicable parts.
3916 * 'Gig Disable' to force link speed negotiation to a lower speed based on
3917 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
3918 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3919 * needs to be written.
3907 **/
3920 **/
3908void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3921void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3909{
3910 u32 phy_ctrl;
3911 s32 ret_val;
3912
3922{
3923 u32 phy_ctrl;
3924 s32 ret_val;
3925
3913 DEBUGFUNC("e1000_disable_gig_wol_ich8lan");
3926 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
3914
3915 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3927
3928 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3916 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3929 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
3917 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3930 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3931 if (hw->mac.type == e1000_ich8lan)
3932 e1000_gig_downshift_workaround_ich8lan(hw);
3918
3919 if (hw->mac.type >= e1000_pchlan) {
3920 e1000_oem_bits_config_ich8lan(hw, FALSE);
3933
3934 if (hw->mac.type >= e1000_pchlan) {
3935 e1000_oem_bits_config_ich8lan(hw, FALSE);
3936 e1000_phy_hw_reset_ich8lan(hw);
3921 ret_val = hw->phy.ops.acquire(hw);
3922 if (ret_val)
3923 return;
3924 e1000_write_smbus_addr(hw);
3925 hw->phy.ops.release(hw);
3926 }
3927
3928 return;
3929}
3930
3931/**
3937 ret_val = hw->phy.ops.acquire(hw);
3938 if (ret_val)
3939 return;
3940 e1000_write_smbus_addr(hw);
3941 hw->phy.ops.release(hw);
3942 }
3943
3944 return;
3945}
3946
3947/**
3948 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3949 * @hw: pointer to the HW structure
3950 *
3951 * During Sx to S0 transitions on non-managed devices or managed devices
3952 * on which PHY resets are not blocked, if the PHY registers cannot be
3953 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3954 * the PHY.
3955 **/
3956void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3957{
3958 u16 phy_id1, phy_id2;
3959 s32 ret_val;
3960
3961 DEBUGFUNC("e1000_resume_workarounds_pchlan");
3962
3963 if ((hw->mac.type != e1000_pch2lan) ||
3964 hw->phy.ops.check_reset_block(hw))
3965 return;
3966
3967 ret_val = hw->phy.ops.acquire(hw);
3968 if (ret_val) {
3969 DEBUGOUT("Failed to acquire PHY semaphore in resume\n");
3970 return;
3971 }
3972
3973 /* Test access to the PHY registers by reading the ID regs */
3974 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3975 if (ret_val)
3976 goto release;
3977 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3978 if (ret_val)
3979 goto release;
3980
3981 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3982 (u32)(phy_id2 & PHY_REVISION_MASK)))
3983 goto release;
3984
3985 e1000_toggle_lanphypc_value_ich8lan(hw);
3986
3987 hw->phy.ops.release(hw);
3988 msec_delay(50);
3989 hw->phy.ops.reset(hw);
3990 msec_delay(50);
3991 return;
3992
3993release:
3994 hw->phy.ops.release(hw);
3995
3996 return;
3997}
3998
3999/**
3932 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3933 * @hw: pointer to the HW structure
3934 *
3935 * Return the LED back to the default configuration.
3936 **/
3937static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3938{
3939 DEBUGFUNC("e1000_cleanup_led_ich8lan");
3940
3941 if (hw->phy.type == e1000_phy_ife)
3942 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4000 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4001 * @hw: pointer to the HW structure
4002 *
4003 * Return the LED back to the default configuration.
4004 **/
4005static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4006{
4007 DEBUGFUNC("e1000_cleanup_led_ich8lan");
4008
4009 if (hw->phy.type == e1000_phy_ife)
4010 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3943 0);
4011 0);
3944
3945 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
3946 return E1000_SUCCESS;
3947}
3948
3949/**
3950 * e1000_led_on_ich8lan - Turn LEDs on
3951 * @hw: pointer to the HW structure
3952 *
3953 * Turn on the LEDs.
3954 **/
3955static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3956{
3957 DEBUGFUNC("e1000_led_on_ich8lan");
3958
3959 if (hw->phy.type == e1000_phy_ife)
3960 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4012
4013 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
4014 return E1000_SUCCESS;
4015}
4016
4017/**
4018 * e1000_led_on_ich8lan - Turn LEDs on
4019 * @hw: pointer to the HW structure
4020 *
4021 * Turn on the LEDs.
4022 **/
4023static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4024{
4025 DEBUGFUNC("e1000_led_on_ich8lan");
4026
4027 if (hw->phy.type == e1000_phy_ife)
4028 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3961 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4029 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3962
3963 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
3964 return E1000_SUCCESS;
3965}
3966
3967/**
3968 * e1000_led_off_ich8lan - Turn LEDs off
3969 * @hw: pointer to the HW structure
3970 *
3971 * Turn off the LEDs.
3972 **/
3973static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3974{
3975 DEBUGFUNC("e1000_led_off_ich8lan");
3976
3977 if (hw->phy.type == e1000_phy_ife)
3978 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4030
4031 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
4032 return E1000_SUCCESS;
4033}
4034
4035/**
4036 * e1000_led_off_ich8lan - Turn LEDs off
4037 * @hw: pointer to the HW structure
4038 *
4039 * Turn off the LEDs.
4040 **/
4041static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4042{
4043 DEBUGFUNC("e1000_led_off_ich8lan");
4044
4045 if (hw->phy.type == e1000_phy_ife)
4046 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3979 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
4047 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3980
3981 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
3982 return E1000_SUCCESS;
3983}
3984
3985/**
3986 * e1000_setup_led_pchlan - Configures SW controllable LED
3987 * @hw: pointer to the HW structure
3988 *
3989 * This prepares the SW controllable LED for use.
3990 **/
3991static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3992{
3993 DEBUGFUNC("e1000_setup_led_pchlan");
3994
3995 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4048
4049 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
4050 return E1000_SUCCESS;
4051}
4052
4053/**
4054 * e1000_setup_led_pchlan - Configures SW controllable LED
4055 * @hw: pointer to the HW structure
4056 *
4057 * This prepares the SW controllable LED for use.
4058 **/
4059static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4060{
4061 DEBUGFUNC("e1000_setup_led_pchlan");
4062
4063 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3996 (u16)hw->mac.ledctl_mode1);
4064 (u16)hw->mac.ledctl_mode1);
3997}
3998
3999/**
4000 * e1000_cleanup_led_pchlan - Restore the default LED operation
4001 * @hw: pointer to the HW structure
4002 *
4003 * Return the LED back to the default configuration.
4004 **/
4005static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4006{
4007 DEBUGFUNC("e1000_cleanup_led_pchlan");
4008
4009 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4065}
4066
4067/**
4068 * e1000_cleanup_led_pchlan - Restore the default LED operation
4069 * @hw: pointer to the HW structure
4070 *
4071 * Return the LED back to the default configuration.
4072 **/
4073static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4074{
4075 DEBUGFUNC("e1000_cleanup_led_pchlan");
4076
4077 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4010 (u16)hw->mac.ledctl_default);
4078 (u16)hw->mac.ledctl_default);
4011}
4012
4013/**
4014 * e1000_led_on_pchlan - Turn LEDs on
4015 * @hw: pointer to the HW structure
4016 *
4017 * Turn on the LEDs.
4018 **/

--- 141 unchanged lines hidden (view full) ---

4160 * @hw: pointer to the HW structure
4161 *
4162 * Clears hardware counters specific to the silicon family and calls
4163 * clear_hw_cntrs_generic to clear all general purpose counters.
4164 **/
4165static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4166{
4167 u16 phy_data;
4079}
4080
4081/**
4082 * e1000_led_on_pchlan - Turn LEDs on
4083 * @hw: pointer to the HW structure
4084 *
4085 * Turn on the LEDs.
4086 **/

--- 141 unchanged lines hidden (view full) ---

4228 * @hw: pointer to the HW structure
4229 *
4230 * Clears hardware counters specific to the silicon family and calls
4231 * clear_hw_cntrs_generic to clear all general purpose counters.
4232 **/
4233static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4234{
4235 u16 phy_data;
4236 s32 ret_val;
4168
4169 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
4170
4171 e1000_clear_hw_cntrs_base_generic(hw);
4172
4173 E1000_READ_REG(hw, E1000_ALGNERRC);
4174 E1000_READ_REG(hw, E1000_RXERRC);
4175 E1000_READ_REG(hw, E1000_TNCRS);

--- 7 unchanged lines hidden (view full) ---

4183
4184 E1000_READ_REG(hw, E1000_IAC);
4185 E1000_READ_REG(hw, E1000_ICRXOC);
4186
4187 /* Clear PHY statistics registers */
4188 if ((hw->phy.type == e1000_phy_82578) ||
4189 (hw->phy.type == e1000_phy_82579) ||
4190 (hw->phy.type == e1000_phy_82577)) {
4237
4238 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
4239
4240 e1000_clear_hw_cntrs_base_generic(hw);
4241
4242 E1000_READ_REG(hw, E1000_ALGNERRC);
4243 E1000_READ_REG(hw, E1000_RXERRC);
4244 E1000_READ_REG(hw, E1000_TNCRS);

--- 7 unchanged lines hidden (view full) ---

4252
4253 E1000_READ_REG(hw, E1000_IAC);
4254 E1000_READ_REG(hw, E1000_ICRXOC);
4255
4256 /* Clear PHY statistics registers */
4257 if ((hw->phy.type == e1000_phy_82578) ||
4258 (hw->phy.type == e1000_phy_82579) ||
4259 (hw->phy.type == e1000_phy_82577)) {
4191 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
4192 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
4193 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
4194 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
4195 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
4196 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
4197 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
4198 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
4199 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
4200 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
4201 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
4202 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
4203 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
4204 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
4260 ret_val = hw->phy.ops.acquire(hw);
4261 if (ret_val)
4262 return;
4263 ret_val = hw->phy.ops.set_page(hw,
4264 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4265 if (ret_val)
4266 goto release;
4267 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4268 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4269 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4270 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4271 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4272 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4273 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4274 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4275 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4276 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4277 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4278 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4279 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4280 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4281release:
4282 hw->phy.ops.release(hw);
4205 }
4206}
4207
4283 }
4284}
4285